A Comparative study of Different Configurations in Triple-Sided

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A Comparative study of Different Configurations in Triple-Sided Charged Plasma Symmetric Lateral Heterojunction Bipolar Transistors on SOI Lourembam Beloni Devi, and Asutosh Srivastava ACS Appl. Electron. Mater., Just Accepted Manuscript • DOI: 10.1021/acsaelm.8b00129 • Publication Date (Web): 05 Apr 2019 Downloaded from http://pubs.acs.org on April 12, 2019

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ACS Applied Electronic Materials

A Comparative study of Different Configurations in Triple-Sided Charged Plasma Symmetric Lateral Heterojunction Bipolar Transistors on SOI Lourembam Beloni Devi*,⸸ and Asutosh Srivastava⸸ ⁓School

of Computer & Systems Sciences, Jawaharlal Nehru University, New Delhi -110067,

India.

KEYWORDS: Triple-Sided Charged Plasma (3SCP), Charged plasma (CP), Symmetric Lateral Heterojunction Bipolar Transistor (SLHBT), uniform 0.3 Ge content, linearly graded SiGe, Germanium. ABSTRACT: A comparative simulation study of Triple Sided Charged Plasma Symmetric Lateral Heterojunction Bipolar Transistor (3SCP SLHBT) on SOI is performed for the first time. A 3SCP SLHBT has all the advantages that a conventional Charge Plasma (cCP) Lateral Bipolar on SOI have namely in overcoming the issue related to thermal budget along with improvement in current gain and speed. Our new design along with heterojunction configuration is able to further improve upon the performances of cCP design by inducing carriers from bottom, side and top w.r.t. cCP design where the carrier concentration is low towards bottom region of active device layer. Our novel 3SCP SLHBT design shows huge improvement in current gain, fT and fmax by almost 1092 percent, 80.6 percent and 51.6 percent respectively w.r.t. cCP SLHBT design. In this paper we carried out a systematic study of heterojunction bipolar structure of the 3SCP device design with three different HBT configurations and presented a comparative study of their performances. The different 3SCP SLHBT configurations studied here as Emitter-BaseCollector are “Si-0.3Ge-Si”, “Si-linearly graded SiGe-Si” and “Si-Ge-Si” respectively. We are able to achieve same Collector current but with lower VBE by ⁓320mV when device having “SiACS Paragon Plus Environment

ACS Applied Electronic Materials 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

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linearly graded SiGe-Si” configuration is replaced by device having “Si-Ge-Si” configuration. We are able to achieve and demonstrate this novel HBT device with best optimal performance parameters for “Si-0.3Ge-Si” configuration. This device shows a current gain of 8.4×105, fT = 428.87GHz and fmax = 2.38 THz. We are also able to successively demonstrate Symmetric Complementary 3SCP SLHBT inverter using “Si-0.3Ge-Si” configuration having optimal digital circuit performance parameters. The inverter show switching voltage (VM) of 0.505V, low noise margin (NML) of 0.47V and high noise margin (NMH) of 0.45V at 1V. 1 INTRODUCTION: Many advantages in Symmetric lateral bipolar transistor on SOI which include CMOS compatible process flow, improved performances like higher gain and higher cut-off frequency have made this device a choice for extremely low power mixed signal/ analog applications1-8. With the device dimensions reaching nanometer range, the thermal budget involved in the process technology is posing a tough challenge in the VLSI industry. cCP bipolar transistor was able to overcome the thermal budget requirements as it is dopingless.9-15 Literature on the novelty of 3SCP Symmetric lateral bipolar transistor (SLBT) on SiGe-OI over the conventional CP SLBT on SiGe-OI is reported.16 In this paper we presented for the first time the dopingless 3SCP device structure in three different HBT configurations. A comparative simulation study of this novel 3SCP SLHBT with three different configurations in Emitter-Base-Collector viz. “Si-0.3Ge-Si”, “Si-linearly graded SiGe-Si” and “Si-Ge-Si” is presented to analyze the impact on different performances in the analog/ mixed signal circuits. Here 0.3Ge means the active layer in Base is comprised of uniform 0.3Ge mole fraction content in Silicon while graded SiGe means the active layer in Base is comprised of Ge content linearly increasing in Silicon from 0 Ge at E-B junction to 0.5 Ge at B-

ACS Paragon Plus Environment

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C junction. As the device presented here is a dopingless HBT design, the issue of boron out diffusion leading to the parasitic barrier effect or also known as heterojunction barrier effect (HBE),17-20 is overcome in our novel 3SCP SLHBT design. In the cCP design,10-12 and in our novel 3SCP design, the Base metal electrode is directly deposited above the active device layer. Above the management of thermal budget, these designs would have an additional advantage over the symmetric lateral bipolar transistors,1-8 and the lateral symmetric transistor with electrostatic polarity control approach,14 due to the absence of the polysilicon doped extrinsic Base placed above the intrinsic Base.21 In our novel 3SCP design, metal electrodes for Emitter/Collector are in three sides of the active device layer. Therefore, in this design the charge plasma induction of carriers are from all three sides unlike only from top side as in cCP design. To better understand the difference between 3SCP SLHBT and cCP SLHBT, schematic diagrams of both the designs are given in section 2 along with comparison of their performances in tabular form. By choosing heterojunction configuration along with Triple Sided Charged Plasma would push the limits of speed and gain. There have been literatures on how to fabricate charged plasma device,9 on techniques and processes to perform Ge ion implantation to create SiGe region.22-25 A probable process flow for the novel 3SCP SLBT on SiGe-OI is reported.16 A potential suitable process flow for our novel 3SCP SLHBT on SOI device structure is proposed in section 4 of this paper. 2 SIMULATION SETUP: DEVICE STRUCTURE / CONCEPT We carried out a systematic simulation study on 3SCP SLHBT (NPN) with three different configurations as mention above. But before we carry out the comparative study of the three


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different HBT configurations in 3SCP SLHBT design, we first made a comparison between the cCP SLHBT (NPN) and our 3SCP SLHBT (NPN) with “Si-0.3Ge-Si” configuration in EmitterBase-Collector in both the designs. For this comparison we perform simulations on both the devices under same setup/conditions. Sentaurus TCAD simulator is used to realize our 2D simulation study. We have incorporated all the essential physics models known to us in the simulator. Models included are Fermi-Dirac distribution along with Hydrodynamic equations to account for transport of carrier energy. Philips unified model to account for carrier-carrier scattering and High field saturation models for low and high field carrier transport. Doping dependent SRH and Auger recombination models are also incorporated. To account for the plasma effect/carrier momentum at the bandedge discontinuity standard thermionic emission model is also included. To account for screening effect at inversion ThinLayer – Lombardi model is invoked.26 We calibrate the tool by targeting the e-h distribution plot and output characteristic plot,9 and our simulation results matched with the published results.

(a)

(b)

Figure 1. Schematic diagram of (a) 3SCP SLHBT and (b) conventional CP SLHBT

Figure 1(a) show schematic diagram of the 3SCP SLHBT (NPN) structure and figure 1(b) show


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schematic diagram of the cCP SLHBT (NPN) structure, where the semiconductor I and II denotes the different semiconductor materials used in the active device layer of the HBT configuration. The major difference between the two device structures are the additional bottom Emitter & Collector metal electrodes along with the associated bottom gateOX layers in our novel design from the conventional design.16 A background Boron doping (NBck) of 1×1015 cm-3 is used for the active device layer (adl) which comprise of the heterojunctions viz. semiconductor region I for Emitter and Collector and semiconductor region II for Base (as in figure 1 (a) and figure 1 (b)) and for the Silicon back substrate. With dopingless charged plasma technique, electrons and holes are induced to create n-type and p-type regions respectively depending on the difference of work-functions between the intrinsic semiconductor and the metal electrode. For an NPN device the workfunction of the Emitter/Collector electrode should be (φmE,C χadlB+Eg/2), where χadlB is the electron affinity of the intrinsic semiconductor region II. We choose Platinum electrode with workfunction 5.65eV,9 as electrode for Base (for n-p-n device). To achieve a more uniform charge carrier distribution beneath the metal electrode a thin oxide layer is used between the metal electrode and the active device layer.9 HfO2 is used as gate-oxide (gateOX) material. Inclusion of gateOX reduces the fermi pining. Another basic requirement of charged plasma technique is that the thickness of active device layer should be less than the Debye length, LD = (єadl .Vt / q·N)1/2; where єadl is the dielectric constant of semiconductor making up the active device layer, Vt is thermal voltage and


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N is the carrier concentration inside the active device layer.9 All simulation studies presented in this paper are for devices without back substrate biasing, i.e. the back substrate is grounded. As mentioned above, before we go ahead with the comparative study of the three HBT configurations in 3SCP SLHBT design, we highlight here the advantages of this novel 3SCP SLHBT over the cCP SLHBT. For this study we have chosen Si-0.3Ge-Si HBT configuration in both the designs. Table 1 below lists the design parameters used in our simulation studies, both for comparison between 3SCP SLHBT (Si-0.3Ge-Si) and cCP SLHBT (Si-0.3Ge-Si) and for comparison between three different configurations in 3SCP SLHBT design. Table 1 Design parameters of the 3SCP and cCP SLHBT for simulation study Parameters

Unit

3SCP SLHBT

cCP SLHBT

WI

(nm)

47.5

47.5

WII

(nm)

45

45

WSpacer

(nm)

5

5

Tadl

(nm)

10

10

TBOX(SiO2)

(nm)

25

25

TSub(Si)

(nm)

25

25

TgateOX(HfO2)

(nm)

5

5

TMetal (E/C)

(nm)

10

10

TMetal (Base)

(nm)

15

15

WB(Physical)

(nm)

40

40

WE,WC

(nm)

45

45

We have chosen a thickness of 10nm for the active device layer, Tadl for our simulation study which is within the Debye length for different 3SCP SLHBT configurations as well as for the


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cCP SLHBT. In figure 2 (a) and 2 (b) we have compared the energy band diagrams, under thermal equilibrium condition, captured at cutline 2nm below TOP gateOX and 2nm above BOX/active device layer interface respectively for both 3SCP SLHBT and cCP SLHBT designs.

(a)

(b)

Figure 2. Comparison of energy band diagram at thermal equilibrium between cCP SLHBT and 3SCP SLHBT designs (a) as captured 2nm below Top gateOX and (b) as captured 2nm above BOX

From figure 2(a) we observed that there is no significant difference in the two energy band diagrams. Due to the presence of the top metal electrodes in similar fashion in both the device structures, induced carriers (electrons in Emitter & Collector and holes in Base) have same concentrations towards the TOP regions of the devices and hence we observe similar energy band diagrams. But from figure 2(b) we observe a significant difference in the conduction and valence energy bands between the two designs towards the bottom region of the active device layer, i.e. bottom E-B-C regions. Energy bands (EC & EV) in Emitter & Collector regions of cCP SLHBT design


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has higher energy level and the energy bands in Base region are spread over a wider range with respect to 3SCP SLHBT design. From these observations we can conclude that the electron concentrations in Emitter (NE) & Collector (NC) regions of 3SCP SLHBT are significantly higher with respect to those of cCP SLHBT design. These higher NE & NC in 3SCP SLHBT design may be attributed to the induction of electrons from the bottom metal electrodes.16 In cCP SLHBT due to the absence of these bottom metal electrodes, the NE & NC (due to top metal electrode) gradually decrease along the depth of the device. Since there is no bottom Base metal electrode in both the designs, gradual decrease in NB (induced due to Top metal electrode) would be same in both the designs. Towards the bottom region of the device structure, due to the higher NE & NC more electron-hole recombine at the E-B and B-C junctions of 3SCP SLHBT with respect to cCP SLHBT16. This results into lesser quasi-neutral Base width, WB, and hence we observe a narrower EC & EV in Base region for 3SCP SLBHT with respect to cCP SLHBT. A design having higher NE & NC w.r.t. NB and lesser WB is desired for higher gain and higher speed. Therefore, a 3SCP SLHBT design shows better performance over cCP SLHBT. Table 2 below list the device performances of 3SCP SLHBT and cCP SLHBT for “Si-0.3Ge-Si” HBT configuration. Table 2 Comparison of performances between 3SCP SLHBT and cCP SLHBT for “Si-0.3GeSi” configurations. 3SCP SLHBT

cCP SLHBT

Current gain@ IC=10-5 (A/µm)

6.2×105

5.2×104

Peak fT (GHz)

428.9

237.5

Peak fmax (THz)

2.38

1.57

Parameters

Now that we have shown the advantages of 3SCP SLHBT over the cCP SLHBT we carry out


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the comparative study on the three different configurations of 3SCP SLHBT. Relatively small lattice mismatch between Si and Si0.7Ge0.3 (⁓3%) and between Si and Ge (⁓4%) seem to show small strain at the epitaxial Si/SiGe and Si/Ge interfaces respectively.27 So for simplicity we have assume, in our study, that the quality of heterojunction interfaces in the three 3SCP SLHBT configurations are same in terms of the stress/strain, scattering due to surface roughness and charge trapping. 3 SIMULATED RESULTS & DISCUSSIONS

(a)

(b)

(c)


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Figure 3 e-h Concentration under thermal equilibrium (a) along Device length at 2nm from gateOX/active device layer interface, (b) along Device depth at 20nm from emitter edge and (c) along Device depth at the center of Base.

Figure 3(a) shows comparison of e-h distribution amongst the three differently configured novel 3SCP SLHBT devices under thermal equilibrium. Throughout the paper we have used the legends “Si-0.3Ge-Si” for 3SCP SLHBT having configuration as Silicon in Emitter/Collector with 0.3Ge content in Silicon in Base; “Si-graded-Si” for Silicon in Emitter/Collector with linearly graded SiGe in Base and “Si-Ge-Si” for Silicon in Emitter/Collector with pure Ge in Base. The plot is captured at 2nm from top gateOX/active device layer interface and is listed in table 3 below. Table 3 e-h concentration for the three 3SCP SLHBTs. Region

Si-0.3Ge-Si

Si-graded-Si

Si-Ge-Si

E/C (e)

1.263e19

1.263e19

1.263e19

B (h)

5.277e19

2.426e19

9.546e19

Device with pure Ge Base see highest induction of holes owing to the higher difference in the work-function between Pt and pure Ge (φmB >χadlB+Eg/2). Figure 3(b) shows comparison of electron concentration amongst the three differently configured HBT devices along the device depth at cutline 20nm from Emitter edge under thermal equilibrium condition. In our novel 3SCP SLHBT design, metal electrodes are on top, side edge and bottom of the active device layer. Due to this device structure the induction of electrons by plasma technique is from three sides justifying the name Triple-sided charge plasma. The equally high e-concentration in the top and bottom regions gives the U-shaped e-profile as seen in figure 3(b) in lieu of the gradually decreasing carrier concentration from top to bottom in case of CP


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bipolar device.10 The figure show same plots for all the three devices as the conditions in Emitter electrode and Emitter device layer are same. Figure 3(c) shows the e-h distribution along the device depth measured at cutline exactly at the center of Base under thermal equilibrium condition. Different Base material has resulted in the different hole concentration and also as the device design has Base electrode only on Top, we see a gradual decrease in the hole concentration from top to bottom of Base. In all the three HBT configurations, the silicon back substrate which was initially doped with Boron at 1×1015 cm-3 saw a higher electron concentration. This is due to the Emitter/Collector bottom electrode just above BOX. This electron concentration gradually decreases along the device depth as we approach the bottom substrate edge.

Figure 4 e-h Concentration along Device length measured at 2nm from gateOX/active device layer interface under forward bias condition (VBE=1V, VCE=1.2V).

Figure 4 shows comparison of e-h concentration under same forward biased condition for all the devices along the device length (E-B-C). From the figure (inset) we observe that more number of electrons reach the Collector region in “Si-Ge-Si” device despite of showing largest NB and WB as can be inferred from e-h distribution at equilibrium condition in figure 3(a). This may be


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attributed to the higher diffusion co-efficient of minority carriers in pure Ge Base w.r.t. SiGe Base.28-29

Figure 5 Comparison of output characteristics at IB=0.1µA. Figure 5 shows output characteristics of the three differently configured 3SCP SLHBTs at IB=0.1µA. From the figure we observe that “Si-Ge-Si” configuration shows highest output current at constant input current amongst the three HBTs under study. This is followed by “Si0.3Ge-Si” configuration followed by “Si-graded-Si” configuration. This observation of higher output current for “Si-Ge-Si” configuration may be attributed to the higher effective intrinsic carrier concentration in Base, nieB and higher diffusion of minority carrier (electrons) in Base, DnB for pure Ge Base w.r.t. 0.3Ge Base and linearly graded SiGe Base.28-31 We extrapolate the ICVC curves in order to get an idea of the early voltage, VA of the individual HBT devices. The VA values of the three devices under study are listed in table 4. Table 4 VA for the three 3SCP SLHBTs. Parameter VA (V)

Si-0.3Ge-Si

Si-graded-Si

Si-Ge-Si

2.43

4.1

2.39


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(a) (b) Figure 6 Comparison of (a) Gummel plot and (b) Current Gain plot.(Measured at VBC = 0).

From the gummel at figure 6(a) we observe that the same IC is achieved by device with pure Ge Base but at much lower Base voltage, VBE w.r.t. device with 0.3Ge and graded SiGe Base. We are able to achieve the same collector current, say @ IC = ⁓2µA/µm with ⁓320mV lesser VBE by device with pure Ge Base and ⁓158mV lesser VBE by device with 0.3Ge Base w.r.t. linearly graded SiGe Base. This observation proves the scaling of VBE with Eg of Base material.32 We also observe that at same VBE, the IB of the device with pure Ge Base is shifted to left the most. This is followed by device with 0.3Ge Base w.r.t. device with graded SiGe Base. For lateral bipolar transistor, the three Base current components are given by equations below.7 JB(VBE') = (JB0,inj+JB0,rec) exp(VBE'/kT)+JB0,SC exp(qVBE'/2kT), (1) with JB0,inj = (qDpE nieE2)/(NEWE), JB0,rec = (qWBnieB2)/( 2τnBNB), JB0,SC = (qniWdBE)/( τn,SC+ τp,SC); where τnB is minority electron lifetime in WB (quasi-neutral base), DpE is the diffusion of hole in Emitter, nieE and nieB are the effective intrinsic carrier density in Emitter and Base respectively. nieB2 is also exponentially dependent on the energy bandgap narrowing in Base from Emitter due


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to Ge content, ΔEgB. τn,SC and τp,SC are electron and hole recombination lifetime in diode space charge region respectively. JB,inj is the component of IB due to injection of holes from Base into Emitter, JB,rec is the component due to recombination in WB and JB,SC is the component due to recombination in depletion region, WdBE (as no base component arise at depletion region, WdBC when measured at VBC=0V).7 The term nieB2 would be more in “Si-Ge-Si” configuration owing to the higher ΔEgB but we know from table 3 that NB is highest for this device configuration from the other two device configurations. The Auger recombination coefficient of Si, SiGe and Ge are very small and almost similar (⁓10-32cm6/s for Si and SiGe while ⁓10-31cm6/s for Ge).26,32 So Auger recombination of minority carrier lifetime in WB that comprise the Base current component JB,rec is very small as compared to the other two components. The ideal base component JB,inj (after neglecting JB,rec) is dependent on geometry and the properties of the material in Emitter region. The Ge content in Base does not affect the energy barrier for hole injection into the Emitter from Base so, this component of Base current would be same for all the three device configurations.33 The third non-ideal (120mV/decade) component of Base current i.e. JB,SC is dependent on the intrinsic carrier density of the Base material along with other parameters. Ratio of ni for Ge to ni for SiGe (0.3Ge) is ⁓3-4.30-31 Since the dWBE (E-B diode space charge region) would lie around the heterojunction interface, ni of both the adjoining semiconductors would attribute to the JB,SC. The dWBE under equilibrium condition (as can be seen from figure 3(a)) is widest in “Si-gradedSi” configuration and narrowest in “Si-Ge-Si” configuration. But under forward bias condition, (as can be seen from the e-h distribution under forward bias condition in figure 4) the recombination volume, dWBE is almost similar for all the device configurations. The higher ni in


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pure Ge along with lesser minority carrier lifetime by almost half w.r.t. SiGe (0.3Ge),30-31 would have attributed to the very high JB,SC for “Si-Ge-Si” configuration. The more the percent of Ge in Silicon more would be this component of Base current i.e. JB,SC. And uniform 0.3Ge content in Silicon has more Ge percent than the graded SiGe (which vary from 0 to 0.5Ge along the length of 40nm Base). Therefore we observe that for the same IB, corresponding VBE for device with “Si-Ge-Si” configuration shows maximum shift towards left in the gummel plot followed by the device with “Si-0.3Ge-Si” configuration. Figure 6(b) shows comparison of current gain plot for the 3SCP SLHBT devices under study. From the current gain plot at lower IC range (below 10-5A/ µm) we observe highest gain for device with “Si-0.3Ge-Si” configuration and lowest current gain for device with Si-Ge-Si configuration. From IC = ⁓20µA/µm upwards, the device with “Si-Ge-Si” configuration show higher current gain over device with “Si-graded-Si” configuration and from IC = ⁓0.27mA/µm upwards device with “Si-Ge-Si” configuration dominates the other two devices. The device with “Si-0.3Ge-Si” configuration exhibits peak gain of 8.4×105, device with “Si-graded-Si” configuration exhibits peak gain of 5.5×105 and device with “Si-Ge-Si” configuration exhibits peak gain of 5.1×105 @ IC ⁓ 3.0µA/µm. The values in the gain also show that our novel 3SCP SLHBT design exhibit better current gain than the Lateral SiGe HBT with partially depleted Base.6 To explain the above observation in current gain plot let us break the data in two regions- (a) lower IC range where Si-0.3Ge-Si configuration shows higher current gain. This is the range after which current gain fall-off sharply; and (b) higher IC range where the device with pure Ge as Base show dominance over the other two. This range is the high injection regime where current gain start to roll-off.


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For all injection levels, collector current, IC is given by:3 IC = AEJC0(VBE') exp(qVBE'/kT)

(2)

where at low VBE JC0(VBE') = qDnBnieB2/WBNB

(3)

and at high VBE JC0(VBE') → (2qDnBnieB/WB)exp(-qVBE'/2kT)

IB = AEJB0 exp(qVBE'/kT)

(4)

(5)

where JB0 is given by the three components JB0,inj , JB0,rec and JB0,SC; pp is the hole density in the ptype base, x = distance from E-B boundary into Base, nieB = effective intrinsic carriers in Base and is exponentially dependent on the energy bandgap narrowing in Base from Emitter due to Ge content, ΔEgB, nieE = effective intrinsic carriers in Emitter, DnB = diffusion co-efficient of electrons in Base, DpE = diffusion co-efficient of holes in Emitter and kT/q = thermal voltage. From figure 3(a) and table 3 we understand that both WB and NB are slightly higher in device with “Si-Ge-Si” configuration w.r.t. the other two devices. The device with “Si-graded-Si” configuration has the least values for WB and NB. But the terms nieB2 and DnB for pure Ge Base configured device is higher than of 0.3Ge Base configured device and least for linearly graded SiGe Base configured device. From gummel plot we observe a that for a particular VBE, IC(Si-Ge-Si) > IC(Si-0.3Ge-Si) > IC(Si-gradedSiGe-Si). We can also say that same collector current, say IC = 10-5A/ µm is achieved at VBE = 0.56V in Si-Ge-Si device, at 0.73V in Si-0.3Ge-Si device and at 0.88V in Sigraded SiGe-Si device.

We also observe similar trend for Base current i.e. for same IB,


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corresponding VBE is least for Si-Ge-Si device followed by Si-0.3Ge-Si device and maximum for Si-graded SiGe-Si device. But what we also observe from the gummel plot is that, at lower VBE i.e. before the onset of high injection regime (current gain roll-off), the amount by which IC(Si-Ge-Si) > IC(Si-0.3Ge-Si) is lesser than the amount by which IB(Si-Ge-Si) > IB(Si-0.3Ge-Si). Hence, for this range we see that the current gain of Si-0.3Ge-Si device is higher than that of Si-Ge-Si device. The probable reason for the higher IB in Si-Ge-Si device may be attributed to the higher contribution of the 120mV/decade behavior of the Base component in Si-Ge-Si device w.r.t. Si-0.3Ge-Si device. Thus the gain for “Si-Ge-Si” configuration, at low VBE (from equation (2) and (5)), would be comparatively lower than from the other two devices and this is observed from the current gain plot. For the device with “Si-0.3Ge-Si” configurations the JC0 at low VBE seem to be slightly higher than “Si-graded-Si” mostly due to the square term to the nieB in equation (3) (nieB would be more for 0.3Ge than linearly graded SiGe owing to higher content of Ge). With the onset of high injection regime i.e., at higher IC range (>10-4) the devices with “Si-GeSi” configuration show dominance over the other two device configurations. This range is also the range where current gain fall-off rapidly. At high VBE, current gain reduces majorly due to exp(-VBE/2kT).3 The remaining factor causing the current gain to reduce is the base-width modulation by VBE and VBC. In this regime 120mV/decade behavior of Base current ceases and increases with the 60mV/decade behavior.7 From the gummel plot, we also observed that the device having “Si-Ge-Si” configuration show same IC and/or same IB at much lower VBE w.r.t. to the other devices having Si-0.3Ge-Si and Si-graded-Si configurations. Thus the rate by which current gain reduces i.e. by exp(-VBE/2kT) would be slower. The VBE corresponding to same IC


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for device with “Si-graded-Si” configuration would be the maximum (see gummel plot in fig 6(a)) and this may be the possible reason for this device having Si-graded-Si configuration showing faster current gain roll-off.

(a)

(b)

Figure 7 Comparison of (a) fT – Vs – IC and (b) fmax – Vs – IC; amongst the three differently configured HBTs. Figure 7(a) shows comparison of fT Vs IC and 7(b) shows comparison of fmax Vs IC. We observe highest fT for device with “Si-Ge-Si” configuration followed by device with Si-0.3Ge-Si and least for device with Si-graded-Si configuration. From figure 7(b) we observe highest and the lowest fmax in the same devices as for fT. The above graphs shows early roll-off for “Si-graded-Si” device which indicates that this configuration is less immune to high injection w.r.t. the other two configurations. A peak fT of 428.87GHz is observed @ IC = ⁓1.3mA/µm for Si-0.3Ge-Si device, 242.03GHz @ IC = ⁓0.2mA/µm for Si-graded-Si device and 702.1GHz @ IC = ⁓9mA/µm for Si-Ge-Si device. Peak fmax for “Si-graded-Si” device is observed at a much lower IC as compared to the other two devices. At IC = ⁓0.23µA/µm “Si-graded-Si” device shows peak fmax of 1.27THz. Peak fmax


18

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of 2.38 THz @ IC = ⁓0.9×10-4 A/µm is observed for device with “Si-0.3Ge-Si” configuration and peak fmax of 2.6THz @ IC = ⁓1.45×10-4 A/µm is observed for device with “Si-Ge-Si” configuration.

Figure 8 Comparison of C-B effective junction capacitances. Figure 8 shows comparison of effective CB junction capacitances with varying frequencies. From the figure we observe that the effective CB junction capacitance is lowest for device with Si-graded-Si and the highest for device with Si-Ge-Si configuration. There is a difference in effective junction CdBC by factor of ⁓1.12 from highest to lowest value. To better understand the above observation we discuss the small signal equations for lateral bipolar transistor.2, 34-35 (2πfT)−1 = τF + kT(CdBE + CdBC)/qIC + CdBC(re + rc) fmax = √(fT/8πrbCdBC)

(6) (7)

τB(HBT) ∞ (WB2.kT)/(DnBΔEgB) × [ 1- (kT/ΔEgB){1-exp(-ΔEgB/kT)}]

(8)

where fT = cut-off frequency, fmax = maximum oscillation frequency, τB(HBT) = base transit time of the HBT which contributes almost half of forward transit time, τF; CdBE and CdBC = B-E and B-C junction depletion layer capacitances respectively; re, rc and rb = emitter, collector and base


19


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resistances respectively; IC = collector current; kT/q = thermal voltage; WB = quasi-neutral base width, DnB = diffusion co-efficient of electrons in base and ΔEgB = Ge induced reduction in bandgap at Emitter-Base edge of the quasi-neutral Base. ΔEgB for the case of graded SiGe Base HBT device would be given by ΔEgB(x=0) - ΔEgB(x=WB) with x being the position from EmitterBase edge to Base-Collector edge. The intrinsic resistivity of 0.3Ge and linearly graded SiGe is few order higher than of pure Ge.30-31 Therefore, rb of device with pure Ge in Base would be much lesser w.r.t. devices with 0.3Ge and linearly graded SiGe in Base. re and rc of devices will remain same as Emitter/Collector is Silicon for all the devices. The value of effective C-B junction capacitance is in fF so the difference in CdBC values for the three device configurations are negligible. Hence we observe highest fmax for device having “Si-Ge-Si” configuration (as can be deduce from equation (7)). Under forward biased condition (as inferred from figure 4) WB for all devices seem comparable, with WB of “Si-graded-Si” device slightly smaller than the rest. However, DnB in the pure Ge Base material is higher w.r.t. DnB in 0.3Ge Base material and linearly graded SiGe Base material. Also the ΔEgB of Si-Ge-Si device is higher than of Si-0.3Ge-Si device and is lowest for Si-graded SiGe-Si device. Thus from equation (8) Base transit time for the device with Ge as Base would be smallest followed by that of device with 0.3Ge as Base and highest by device with linearly graded SiGe as Base and hence is for the forward transit time. The difference in fT for the three device configurations would majorly depend on the τF. The above arguments (and from equation (6) to (8)) support our simulation results where we observe highest fT and fmax for device with Ge Base configuration and lowest for device with linearly graded SiGe Base.


20

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4

PROPOSED PROCESS FLOW FOR THE FABRICATION OF 3SCP SLHBT

DEVICE STRUCTURE This novel 3SCP SLHBT on SOI device design would be fabricated in Semiconductor Industry just as FinFETs, SOI have been realized and matured over a period of time. As mentioned above, a probable process flow for the novel 3SCP SLBT on SiGe-OI is reported.16 A potential suitable process flow for fabrication of the novel 3SCP SLHBT on SOI is shown in figure 9.


21


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Figure 9 Proposed process flow for fabrication of the 3SCP SLHBT on SOI device structure. Successful epitaxial Silicon growth on a few A° thick ALD of BeO is reported.36 Ge ion implantation into the 45nm length WII region of the 10nm thick SOI would yield uniform SiGe Base.22-25 A multiple masking and patterning of the WII region for increasing doses of Ge ion implantation would result into small step-wise graded SiGe WII region (from 0 to 0.5 Ge in SOI). This small step-wise graded Ge in Silicon would closely resemble the linearly graded SiGe as the length of Base is very small. A better optimized technology for achieving linearly graded SiGe in lateral direction would also be realized over a period of time. 5

DIGITAL APPLICATION: SYMMETRIC COMPLEMENTARY INVERTER

CIRCUITS We extend our study in 3SCP SLHBT with the three different configurations for digital signal application by carrying out simulation on complementary 3SCP SLHBT Inverter circuit. We have maintained the geometric symmetry amongst Emitter and Collector of n-p-n and of p-n-p of all the inverters and so the name Symmetric Complementary Inverter circuit.37-38 This symmetric geometry would increase the cell density at chip level.38 We were able to achieve comparable gain for PNP and NPN having same geometry by using same metal electrodes for corresponding


22

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n-type regions and p-type regions i.e. metals used for n-p-n are Gadolinium (Gd) for Emitter/Collector and Platinum (Pt) for Base and for p-n-p metals used are Platinum for Emitter/Collector and Gadolinium (Gd) for Base.16 A load capacitance of 0.1fF is used in all the complementary inverter circuits. Table 5 lists the e-h concentrations under thermal equilibrium in Emitter/Collector and Base of the three differently configured PNP 3SCP SLHBT devices. e-h concentrations are captured at 2nm from top gateOX-active device layer interface. And table 6 lists the peak current gain for the NPN & PNP of the 3 differently configured complementary 3SCP SLHBT inverters. Table 5 e-h concentrations for the PNP 3SCP SLHBTs Configuration

units

Base(e)

E/C(h)

Si-0.3Ge-Si

(1/cm3)

5.49e19

9.35e18

Si-graded-Si

(1/cm3)

3.65e19

9.35e18

Si-Ge-Si

(1/cm3)

8.41e19

9.35e18

Table 6 Peak Gain for the NPN & PNP of the 3 differently configured complementary 3SCP SLHBT inverters. Configuration Si-0.3Ge-Si

NPN 11e5

PNP 7.2e5

Si-graded-Si

8.6e5

2.6e5

Si-Ge-Si

7.1e5

4e5


23


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(a) (b) Figure 10 Comparison of the three differently configured Complementary inverters (a) VTC (b) Butterfly. Figure 10(a) show comparison of the VTC curves amongst the three differently configured complementary 3SCP SLHBT inverters and figure 10(b) shows the butterfly curves. The butterfly curves are obtained by superimposing the VTC curves with their corresponding inverse VTC curves.

(a)

(b)


24

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(c) Figure 11 Comparison of DC (Static) Current plots for the three differently configured Complementary inverters (a) Si-0.3Ge-Si configuration (b) Si-graded-Si configuration and (c) Si-Ge-Si configuration Figure 11 (a), (b) and (c) shows the DC (Static) current plots for the inverters with “Si-0.3GeSi”, “Si-graded-Si” and “Si-Ge-Si” configurations respectively. From the plots the quiescent leakage current, IDDQ of the inverter with Si-Ge-Si seem to be higher than the rest but the order is too small that this high value might hardly impact the overall performances. A summary of the DC parameters of the three inverters are listed in table 7 below. Table 7 Summary of the complementary inverters NML NMH IDDQ Config VM(V) (V) (V) (nA/µm) Si-0.3Ge-Si 0.505 0.47 0.45 2.07e-7 Si-graded-Si

0.477

0.43

0.46

2.74e-9

Si-Ge-Si

0.497

0.48

0.43

2.12e-5

From table 7 we observe that the switching voltage VM, low and high noise margin NML and NMH of the three device configurations are almost comparable. The Quiescent leakage current, IDDQ is higher in “Si-Ge-Si” configuration by few orders than in “Si-0.3Ge-Si” configuration. “Si-graded-Si” configuration shows the least IDDQ with 2.74×10-18 A/µm. From the negligibly low IDDQ values of all the three devices we can conclude that in this novel design there is no static power loss which is a huge advantage for ultra low power design application. We also


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observe from the DC current plots that the Ipeak is highest in “Si-Ge-Si” configuration touching almost 1µA/µm. Ipeak for “Si-0.3Ge-Si” is ⁓3.5nA/µm and for “Si-graded-Si” is the lowest at ⁓6.5pA/µm.

Figure 12 Comparison of AC switching for the three differently configured Complementary inverters. Figure 12 shows the AC switching characteristics of the inverters. From the figure we observe that the inverter with “Si-Ge-Si” configuration show faster fall time but slower rise time w.r.t. inverter with “Si-0.3Ge-Si” configuration. The inverter with “Si-graded-Si” configuration seem to have higher delay in both rise and fall time among the three inverter configurations. During rise time, “Si-0.3Ge-Si” inverter is observed to advance by 19.36ps while “Si-graded-Si” is observed with a delay of 3.63ps w.r.t. “Si-Ge-Si” inverter. During fall time, a delay of 0.79ps is observed for “Si-0.3Ge-Si” inverter and a delay of 9.24ps is observed for “Si-graded-Si” inverter w.r.t. “Si-Ge-Si” inverter. From the above observations made for the inverter circuits, better performance seem to depend mainly on the ratio of n-p-n gain, βn to p-n-p gain, βp approaching close to unity w.r.t. the heterojunction configurations. With the design parameters used in our study, βn/βp for “Si-0.3GeSi” is ⁓1.53, for “Si-graded-Si” is ⁓3.31 and for “Si-Ge-Si” is ⁓1.78. We conclude that the


26

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inverter circuit with Si-0.3Ge-Si HBT configuration has optimal performance for fall and rise time. 6

CONCLUSION

In this paper we have presented a comparative simulation study of three different configurations of Triple Sided Charged Plasma Symmetric Lateral Heterojunction Bipolar Transistor on SOI. We observed and conclude that there is a trade-off between device configured for high speed and device configured for high gain. Despite having ⁓320mV lesser VBE by device with pure Ge in Base than device with linearly graded SiGe in Base, we conclude that the 3SCP SLHBT with Si0.3Ge-Si configuration being the optimum device with maximum gain of 8.4×105 @ IC = ⁓3.0µA/µm and peak fmax of 2.38 THz @ IC = 0.9×10-4 A/µm and peak fT of 428.87 GHz @ IC = 1.3mA/µm. This configuration at digital circuit level shows better noise margins with improvement in overall delays in terms of rise and fall time as compared to the other configurations. Corresponding Author *E-mail: [email protected] ORCID Beloni Lourembam: https://orcid.org/0000-0002-4028-9086 Author Contributions The manuscript was written through contributions of all authors. All authors have given approval to the final version of the manuscript. ACKNOWLEDGMENT The Authors are thankful to the DST PURSE by Department of Science and Technology,


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Government of India and UGC-UPE-II: 64, JNU by University Grant Commission, Government of India for the financial support. One author, Lourembam Beloni Devi, would like to thank University Grant Commission, Government of India for the research fellowship. Lourembam Beloni Devi would also like to thank Kundan Singh, Amit Sharma and Jitendra Kumar for the useful discussion and help. REFERENCES (1) Cai, J.; Ning, T.H.; Chris D’Emic, Chan, K.K.; Haensch, W.E.; Yau, J. –B.; Park, D.-G. Complementary thin-base symmetric lateral bipolar transistor on SOI. In: Proceedings IEEE IEDM Technical Digest, Washington, DC, USA, Dec. 2011, pp. 386–389. (2) Ning, T.H.; Cai, J. On the performance and scaling of symmetric lateral bipolar transistors on SOI. IEEE Journal Electron Devices Society, Jan. 2013, 1(1), pp.21–27. (3) Cai, J.; Ning, T. H.; D’Emic, C. P.; Yau, J.-B.; Chan, K. K.; Yoon, J.; Muralidhar, R.; Park, D.-G. On the Device Design and Drive-Current Capability of SOI Lateral Bipolar Transistors. IEEE Journal of the Electron Devices Society, Sept. 2014, 2(5), pp. 105-113. (DOI: 10.1109/JEDS.2014.2331053) (4) Ning, T.H.; Cai, J. A Perspective on Symmetric Lateral Bipolar Transistors on SOI as a Complementary Bipolar Logic Technology. IEEE Journal of the Electron Devices Society, Jan. 2015, 3(1), pp. 24-36. (5) Yau, J.-B.; Cai, J.; Yoon, J.; D’Emic, C.; Chan, K. K.; Ning, T. H.; Engelmann, S. U.; Park, D.-G.; Mo, R. T. SiGe-on-Insulator Symmetric Lateral Bipolar Transistors. In: Proceedings on SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE, Rohnert Park, CA, Oct. 2015, pp. 1-2. (6) Raman, S.; Sharma, P.; Neogi, T. G.; LeRoy, M. R.; Clarke R.; McDonald, J. F. On the Performance of Lateral SiGe Heterojunction Bipolar Transistors With Partially Depleted Base. IEEE Transactions on Electron Devices, Aug. 2015, 62(8), pp. 2377-2383. (DOI: 10.1109/TED.2015.2438819) (7) Yau, J.-B.; Cai, J.; Ning, T.H. On the Base Current Components in SOI Symmetric Lateral Bipolar Transistors. IEEE Journal of the Electron Devices Society, May 2016, vol.4, no.3, pp. 116-123. (DOI: 10.1109/JEDS.2016.2545859) (8) Ning, T. H. A perspective on SOI Symmetric Lateral Bipolar Transistors for Ultra-LowPower Systems. Journal of the Electron Devices Society, Sept. 2016, 4(5), pp.227-235. (9) Hueting, R. J. E.; Rajasekharan, B.; Salm, C.; Schmitz, J. The charge plasma P-N diode.


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A Comparative study of Different Configurations in Triple-Sided

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