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A Nonlithographic Top-Down Electrochemical Approach for Creating Hierarchical (Micro-Nano) Superhydrophobic Silicon Surfaces Ming-Fang Wang, Nithin Raghunathan, and Babak Ziaie* School of Electrical and Computer Engineering, Purdue UniVersity, West Lafayette, Indiana 47907 ReceiVed NoVember 4, 2006. In Final Form: January 15, 2007 Superhydrophobic surfaces are biomimetic structures with potential applications in several key technological areas. In the past decade, several top-down and bottom-up fabrication methods have been developed to create such surfaces. These typically combine a hierarchical structure and low surface energy coatings to increase the contact angle and decrease the rolling angles. Silicon-based superhydrophobic surfaces are particularly attractive since they can be integrated with active electronics in order to protect them from the detrimental effects of environmental water and moisture. In this work, we introduce a simple and inexpensive process incorporating electrochemical surface modification (to create a fractal shape micro-nano topography) in combination with a final wet etching step to fabricate a superhydrophobic silicon surface with a contact angle of 160° and a sliding angle of less than 1°.
Introduction In recent years, superhydrophobic surfaces (SHP) have attracted a considerable amount of attention. These surfaces, which occur naturally in some plant leaves (e.g., lotus and rice) and insect wings (e.g., butterfly and cicada), are characterized by a high contact angle (usually >150°) and low sliding angle (low flow resistance).1-5 This makes them suitable for applications in microfluidics, lab-on-a-chip systems, and self-cleaning surfaces and coatings. SHP surfaces can be fabricated by modifying the surface morphology (i.e., creating micro-nano pillars), by coating the surface with a low surface energy layer (e.g., fluoroalkylsilane), or by combining both. Top-down and bottom-up fabrication methods have been used to create such surfaces on various polymers, semiconductors, and ceramic substrates.6-11 From a practical standpoint, SHP surfaces on silicon are particularly attractive since they can be integrated with other electronic components to protect them from the deleterious effects of water and moisture in the environment. Although photolithography has been used to pattern uniform micro-nanoscale pillar arrays on silicon surfaces and obtain high contact and low sliding angles, a non-lithographic approach is also highly desirable. For example, Baldacchhini et al. recently used femtosecond laser pulses to modify silicon surface morphology in order to create an SHP surface.12 However, this method requires access to sophisticated laser setups and is serial in nature (i.e., time-consuming). Although porous silicon has been intensively studied for siliconbased optical devices and sensing applications, its properties * Corresponding author. Phone: (765) 494-0725. E-mail: bziaie@ purdue.edu. (1) Sun, T.; Feng, L.; Gao, X.; Jiang, L. Acc. Chem. Res. 2005, 38, 644. (2) Miwa, M.; Nakajima, A.; Fujishima, A.; Hashimoto, K.; Watanabe, T. Langmuir 2000, 16, 5754. (3) Patankar, N. A. Langmuir 2003, 19, 1249. (4) Patankar, N. A. Langmuir 2004, 20, 8209. (5) Patankar, N. A. Langmuir 2004, 20, 7097. (6) Erlebacher, J.; Sieradzki, K.; Searson, P. C. J. Appl. Phys. 1994, 76, 182. (7) Feng, L.; Li, S.; Li, Y.; Li, H.; Zhang, L.; Zhai, J. AdV. Mater. 2002, 14, 1857 (8) Sun, M.; Luo, C.; Xu, L.; Ji, H.; Ouyang, Q.; Yu, D.; Chen, Y. Langmuir 2005, 21, 8978. (9) Nakajima, A.; Fujishima, A.; Hashimoto, K.; Watanabe, T. AdV. Mater. 1999, 11, 1365. (10) Lau, K. K. S.; Bico, J.; Teo, K. B. K.; Chhowalla, M.; Amaratunga, G. A. J. Nano Lett. 2003, 3, 1701. (11) Shastry, A; Case, M. J.; Bo¨hringer, K. F. Langmuir 2006, 22, 6161. (12) Baldacchini, T.; Carey, J. E.; Zhou, M.; Mazur, M. Langmuir 2006, 22, 4917.
relevant to SHP surfaces have not been investigated. Porous silicon was accidentally discovered by Uhlir during studies of the electropolishing of silicon in hydrofluoric acid (HF)-based solutions in the mid 1950s.13 Under electrochemical14 reaction, the silicon did not dissolve uniformly, but instead fine holes were generated, which propagated primarily in the 〈100〉 direction in the wafer.15-18 The overall structure of porous silicon layers depended very strongly upon anodization conditions and the resistivity (magnitude and type) of silicon itself.19-24 Two important parameters that characterize porous silicon are porosity (defined as the fraction of void within porous silicon layer) and thickness.25,26 Our goal here is to develop a porous silicon-based SHP surface using a convenient and simple method based on micro-nano hierarchical morphology. The approach we demonstrate in this paper is nonlithographic, inexpensive, and can be integrated with silicon-based processes.27,28 In our process, first a hierarchical porous silicon is produced by etching crystalline silicon in aqueous ethanolic HF acid electrolytes with a high current density (only current densities higher than a critical value result in a hierarchical structure). Then, an additional wet etching step is used to modify the porous layer further by converting pores to pillar-like structures. This structural transformation results from the positional dependence of the silicon etch rate; that is, pore-pillar transformation occurs due to the varied sidewall thickness obtained in the electrochemical step. This results in a micro-nano hierarchical pillarlike morphology on the silicon surface after the two-step etching (13) Uhlir, A. Bell Syst. Tech. J. 1956, 35, 333. (14) Ronkel, F.; Schultze, J. W. J. Porous Mater. 2000, 7, 11. (15) Gullis, A. G. J. Appl. Phys. 1997, 82, 909. (16) Ottow, S.; Lehmann, V.; Foll, H. J. Electrochem. Soc. 1996, 143, 385. (17) Lehmann, V.; Ronnebeck, S. J. Electrochem. Soc. 1999, 146, 2968. (18) Erlebacher, J.; Sieradzki, K.; Searson, P. C. J. Appl. Phys. 1994, 76, 182. (19) Lang, W.; Steiner, P.; Sandmaier, H. Sens. Actuators, A 1995, 51, 31. (20) Zhang, X. G. J. Electrochem. Soc. 2004, 151 (1), C69. (21) Smith, R. L.; Collin, S. D. J. Appl. Phys. 1992, 71 (8), R1. (22) Bley, R. A.; Kauzlarich, S. M.; Davis, J. E.; Lee, W. H. Chem. Mater. 1996, 8, 1888. (23) Canham, L. T.; Houlton, M. R.; Leong, W. Y.; Pickering, C.; Keen, J. M. J. Appl. Phys. 1991, 70, 422. (24) Lemann, V.; Jobst, B.; Muschik, T.; Kux, A.; Petrova-koch, V. J. Appl. Phys. 1993, 32, 2095. (25) Canham, L. T. Appl. Phys. Lett. 1990, 57, 1048. (26) Lehmann, V.; Gosele, U. Appl. Phys. Lett. 1991, 58, 856. (27) Schoning, M.; Simonis, A.; Ruge, C.; Ecken, H.; Veggian, M.; Luth, H. Sensors 2002, 2, 11. (28) Thust, M.; Schoning, M.; Frohnhoff, S.; Kordos, P.; Luth, H. Meas. Sci. Technol. 1996, 7, 26.
10.1021/la063230l CCC: $37.00 © 2007 American Chemical Society Published on Web 02/01/2007
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sequence. It is interesting to note that the pillar peaks are not on the same horizontal level in our experiment. This fact has important implications for the surface stability (rolling angle) of water droplets. Materials and Methods Wafer Preparation. The porous silicon samples are formed by anodizing p-type and n-type (100) oriented silicon wafers with a resistivity of 5-20 Ω‚cm. Before anodization, the wafers are cut in a precision dicing machine into a 1 in. square area and cleaned in a sulfuric acid-oxidant mixture for 15 min, then rinsed in deionized water for 5 min. To make sure that the native oxide is removed, wafers are submerged in a mixture of 1 vol HF acid (49% electronic grade) and 10 vol deionized water for 10 s. Porous Silicon Formation. The anodization cell29,30 is a conventional single-tank cell (dimensions and material). A metal contact (aluminum plate) is made to the back-side of the wafer and sealed with an O-ring so that only the front side of the sample is exposed to the anodizing electrolyte. Platinum wire is used as the cathode and immersed in the electrolyte, a mixture of 1 vol HF acid (49% electronic grade) and 1 vol pure ethanol (100% electronic grade). After anodization, the samples are cleaned with pure ethanol for 5 min to avoid possible damage from water surface tension. The current densities used for porous silicon formation are 48 mA/cm2 (low current density for normal porous silicon formation) and 170 mA/cm2 (high current density for hierarchical porous silicon formation). An Agilent E3640 DC current source is used for porous silicon formation. Contact Angle Measurement. The contact angles of water droplets are measured by a contact angle analyzer (DSA 100, KRUSS, Germany), and the values are averaged with seven different positions in each condition. The water droplet volume we use is 8 µL. Optic and Scanning Electron Microscope (SEM) Photos. Regular and modified porous silicon structures are visually inspected by optical (Eclipse, Nikon) and SEM (S-4800, Hitachi) microscopes. Digital Camera Image. In order to demonstrate the droplet movement and self-cleaning property of the SHP unstable silicon surface, consecutive pictures are taken at 1/5 s intervals by a digital camera (COOLPIX 8800, Nikon). Several short movies are also recorded and are included in the Supporting Information.
Results and Discussion Regular and Hierarchical Macroporous Silicon. As mentioned in the introduction, several types of porous silicon structures can be created depending on the processing conditions and wafer characteristics (doping and type). Generally, these structures are classified according to their pore size as (1) microporous (50 nm). Microporous and mesoporous silicon have high porosity and hydrophobic features. In order to create SHP surfaces on porous silicon surface, we used macroporous morphology in p-type and n-type wafers. The current density and etching time were 48 mA/cm2 and 8 min (a total charge of ∼35 C for a 1.4 cm diameter silicon piece), respectively. SEM photos of p-type and n-type macroporous silicon layers are shown in Figure 1a,b. In p-type samples, the pore diameters ranged from 0.5 to 2 µm and sidewall thicknesses were between 0.5 and 1 µm (the pore diameters were larger than the thicknesses of the sidewalls in the p-type wafer). Macroporous silicon generated in n-type wafers had a different morphology, with a small pore diameter (around 1 µm) and uniform distribution. Moreover, the sidewall thicknesses ranged from 0.5 to 4 µm. (29) Kurowski, A.; Schultze, J. W.; Luth, H.; Schoning, M. J. The 11th International Conference on Solid-State Sensors and Actuators, Munich, Germany, 1997. (30) Drot, J.; Lindstrom, K.; Rosengren, L.; Laurell, T. J. Micromech. Microeng. 1997, 7, 14.
Figure 1. SEM photos of (a) macroporous p-type silicon, (b) macroporous n-type silicon, (c) fractal-shaped hierarchical p-type silicon after the high current density etch, (d) fractal-shaped hierarchical n-type silicon after the high current density etch, (e) submicron pillar structures in p-type silicon after the BOE etch, and (f) submicron pillar structures in n-type silicon after the BOE etch.
Higher current density results in cracking the porous silicon layer upon formation in both p-type and n-type samples. Figure 1c,d shows SEM photos of fractal-shaped hierarchical macroporous silicon structures in p-type and n-type wafers fabricated using a current density of 170 mA/cm2 and an etching time of 12 min (a total charge of ∼188 C for a 1.4 cm diameter silicon piece). The dimensions of fractal-shaped silicon islands were between 20 and 50 µm, and their thicknesses were around 100 µm in a p-type wafer. In this fractal-shaped hierarchical structure, micron-sized silicon islands have nanosized (or submicron-sized) pores. The next step in the process was to convert the pores in the fractal-shaped silicon islands into pillar-like structures, therefore creating a micro-nano hierarchical SHP silicon surface morphology. Structure Transformation from Pore to Pillar. The simplest way to achieve this goal is to etch fractal-shaped hierarchical macroporous silicon in a controlled manner, that is, to partially remove the sidewalls in the pore structures to form pillar-like structures. Here, we used a wet etching method. The etchant combined nitric acid and buffered oxide etch (BOE) in the ratio 1:2, and etching time was 10 min. BOE is a mixture of NH4F and HF (7:1 in ratio) and etches SiO2 at about 1000 Å/min at room temperature. Figure 1e,f shows SEM pictures of submicron pillar-like structures subsequent to the BOE etch. Figure 2a depicts the pore structures of macroporous silicon formed in a p-type wafer. As remarked earlier, the pore sizes ranged from 0.5 to 2 µm, and the sidewall thicknesses were between 0.5 and 1 µm. During the wet etch, larger pores provide easier access for the etchant, while the smaller ones tend to restrict the penetration
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Figure 2. The pore structures in a p-type wafer are depicted to explain the structure’s transformation after wet etching. The corresponding shapes (type A, type B, and type C) found in the SEM pictures are used to support their formation mechanism.
Figure 4. Droplet movement on an SHP unstable silicon surface (a-d). The water droplet moves in a random direction and leaves the macroporous area unless trapped by a defect. The self-cleaning property of an SHP silicon surface is demonstrated with silica powder (e-h). The silica powder-covered (10 µm in diameter) silicon surface is easily cleaned using water droplets.
Figure 3. Contact angle (a) and sliding angle (b) for regular macroporous silicon, macroporous silicon with fractal-shape hierarchical structure, and fractal-shape hierarchical macroporous silicon after the wet etching step.
of the etchant. In addition, thinner sidewalls of macroporous silicon are etched faster (sometimes completely) than the thicker ones (the bold lines in Figure 2 represent thicker sidewalls). We found corresponding shapes in the SEM pictures to support our assumptions of pore-to-pillar transformation. These SEM images
are shown in Figure 2b-e. As can be seen, they are similar to the A, B, and C morphologies indicated in Figure 2a. The same phenomena happen in n-type wafers with a somehow dissimilar surface morphology after wet etching. This is due to the fact that n-type macroporous silicon has smaller diameter pores and thicker sidewalls. Contact and Rolling Angle Analysis. The contact and rolling angles were measured for (1) regular macroporous silicon, (2) macroporous silicon with fractal-shape hierarchical structure, and (3) fractal-shaped hierarchical macroporous silicon after the wet etching step. Figure 3 summarizes the results. For both p-type and n-type wafers, the contact angles of regular macroporous silicon (nonhierarchical) were around 120° with a rolling angle of 90°. With fractal-shaped hierarchical structure, the contact angle increased to 135°, and after additional wet etching, the contact angle approached 160°. Additionally, after the wet etching step, the surface became extremely unstable, showing a very low rolling angle (
