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A Vertically Integrated Junctionless Nanowire Transistor Byung-Hyun Lee, Jae Hur, Min-Ho Kang, Tewook Bang, DaeChul Ahn, Dongil Lee, Kwang-Hee Kim, and Yang-Kyu Choi Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.5b04926 • Publication Date (Web): 17 Feb 2016 Downloaded from http://pubs.acs.org on February 27, 2016

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A Vertically Integrated Junctionless Nanowire Transistor Byung-Hyun Lee a,b, Jae Hur a, Min-Ho Kang c, Tewook Bang a, Dae-Chul Ahn a, Dongil Lee a , Kwang-Hee Kim c, and Yang-Kyu Choi a* a

School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea

b

Memory Business, Samsung Electronics, San #16 Banwol-Dong, Hwasung-City, Gyeonggi-Do 18448, Republic of Korea

c

Department of Nano-process, National Nanofab Center (NNFC), 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea

Byung-Hyun Lee: [email protected] Jae Hur: [email protected] Min-Ho Kang: [email protected] Tewook Bang: [email protected] Dae-Chul Ahn: [email protected] Dongil Lee: [email protected] Kwang-Hee Kim: [email protected]

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Yang-Kyu Choi: [email protected] * Address correspondence to [email protected].


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Abstract A vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure, is demonstrated on a bulk silicon wafer for the first time. The proposed VJ-FET mitigates the issues of variability and fabrication complexity that are encountered in the vertically integrated multi-NW FET (VM-FET) based on an identical structure in which the VM-FET, as recently reported, harnesses a source and drain (S/D) junction for its operation and is thus based on the inversion mode. Variability is alleviated by bulk conduction in a junctionless FET (JL-FET), where current flows through the core of the SiNW, whereas it is not mitigated by surface conduction in an inversion mode FET (IMFET), where current flows via the surface of the SiNW. The fabrication complexity is reduced by the inherent junctionless (JL) structure of the JL-FET because S/D formation is not required. In contrast, it is very difficult to dope the S/D when it is positioned at each floor of a tall SiNW with greater uniformity and with less damage to the crystalline structure of the SiNW in a VM-FET. Moreover, when the proposed VJ-FET is used as nonvolatile flash memory, the endurance and retention characteristics are improved due to the abovementioned bulk conduction.

Keywords: Silicon nanowire (SiNW), Gate-all-around (GAA), Vertical integration, Junctionless transistor, Three-dimensional nonvolatile memory, One-route all-dry etch.


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Over the past five decades, the aggressive miniaturization of transistors based on metaloxide-semiconductor field-effect transistors (MOSFETs) has led to noteworthy achievements, such as lower costs, improved productivity, and upgraded performance capabilities.1 Consequently, the transistor is today’s chief workhorse powering the semiconductor industry and serves as a fundamental building block for a variety of electronic systems. The short-channel effects (SCEs) that have arisen in conjunction with the aggressive miniaturization efforts have been the most difficult technical challenge in relation to maintaining Moore’s law; hence, much effort has been devoted to suppressing these effects during the fabrication of complementary metal-oxide-semiconductor (CMOS) devices.2,3 One approach is to employ a three-dimensional (3-D) structured transistor beyond the conventional two-dimensional (2-D) transistor.4 Among the various 3-D structures investigated recently5-7, the gate-all-around (GAA)-based silicon nanowire (SiNW), which is positioned at the end of the roadmap and has been applied in a range of uses,8-11 has shown the strongest gate controllability to effectively suppress SCEs.12-14 In the structure, SiNWs with smaller diameters are preferred to suppress the SCEs more effectively, i.e., to lower the off-state leakage current. However, this inevitably sacrifices the on-state current.15 In this regard, the vertical stacking of SiNWs compensates for the decreased on-state current without increasing the footprint of the transistor.16-20 The on-state current can be further increased by increasing the number of SiNWs. This can serve as a strategy to ‘kill two birds with one stone’, i.e., the vertically stacked SiNWs provide both high on-state and low off-state currents. Very recently, a vertically integrated multi-NW FET (VM-FET) with a five-story nanowire based on inversion mode (IM) operation enabled by a p-n junction in the source and drain (S/D) region was reported. The five-story nanowire was fabricated using the one-route alldry etching process (ORADEP). It showed good feasibility for use in a 3-D integration-based


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high-performance transistor.21 Nevertheless, the variability originating from vertically stacked SiNWs is problematic because the geometric shape and size of each nanowire are not always identical. Additionally, the S/D resistance and effective channel length can vary for each SiNW. These concerns would become more serious with a greater number of SiNWs. Thus, a novel approach is required to resolve the previously mentioned problems. A conventional MOSFET consists of a junction and its connection. The junction facilitates the flow and cut-off of charges in the transistor and thereby enables the switching operation. However, in terms of the literal meaning of a transistor, that is, a combination of ‘trans-’ and ‘resistor’, the transistor does not directly connote the existence of a junction. In other words, the junction is optional in the transistor but not essential. Such a paradigm shift from a conventional junction-embedded transistor resulted in the invention of a MOSFET based on the configuration of a gated resistor without a junction, referred to as a junctionless FET (JL-FET).2225

Due to the various advantages originating from its inherent process simplicity and unique

operation mechanism,26-28 the JL-FET has attracted considerable attention from both academia and industry. An S/D region for the JL-FET that is homogeneously doped with the channel (e.g., n (source)-n (channel)-n (drain)) is formed simultaneously with an ion implantation process for the formation of the channel, simplifying the process because it is not necessary to create a p-n junction for the S/D. Thus, due to its intrinsic junction-free structure, variability issues such as the fluctuation of the junction profile are no longer a concern. The charge transport occurs at the core of the Si channel in the JL-FET, whereas it occurs at the surface of the Si channel in a conventional junction-embedded MOSFET, i.e., an inversion-mode FET (IM-FET). Mobile charges in the JL-FET are therefore less sensitive to the corner effect arising from the intensified electric field at the apex of the Si channel while also being less sensitive to surface roughness


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and Si-to-SiO2 interface traps.22 On the basis of these advantages, the JL-FET is a promising candidate for future CMOS technology. Prior to the actual implementation of the JL-FET for mass production, a few concerns should be resolved to enhance its performance. Because the performance of the JL-FET strongly depends on the channel resistance, 29 the doping concentration should be as high as possible for low resistance. However, it is difficult to fully deplete a heavily doped channel; consequently, the JL-FET is not effectively turned off and produces a high level of off-state leakage current. Note that the increased off-state leakage gives rise to an undesirable increase in the amount of stand-by power consumption. In this regard, the channel should be as thin as possible to form a fully depleted body, and the thinned channel thereby suppresses the off-state leakage current. In terms of the performance and power consumption, a 3-D simulation analysis of the correlation between the channel doping concentration and the channel thickness is included in the Supporting Information. While a silicon-on-insulator (SOI) wafer has been used for this purpose, it is costly compared to a bulk-Si wafer. Therefore, the fabrication of the JL-FET on a bulk-Si wafer has been attempted as an alternative approach.30-32 A GAA structure that completely wraps bridge-type SiNWs, separate from bulk-Si, can lead to the realization of a bulk-Si-based JL-FET with high performance and good switching capability due to the enhanced gate controllability of such a structure.33,34 Despite the use of the GAA SiNW structure, the use of a heavily doped channel will inevitably lead to another problem that prevents high performance. Heavy doping for low channel resistance can reduce the mobility owing to the increased amount of impurity scattering and hence may result in performance degradation.22,29 Therefore, two counteracting factors, i.e., the channel resistance and impurity scattering, should be carefully optimized to achieve high performance. An additional S/D implantation process was applied to achieve a


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compromise between the two competing factors, but it aggravated the SCEs and increased the degree of process complexity.35 The dimensions of the SiNWs also demand a proper compromise between the gate controllability to minimize the off-state current by decreasing the SiNW diameter and the current drivability to maximize the on-state current by increasing the SiNW diameter, as mentioned above. Under these circumstances, an innovative JL-FET structure is required to achieve high performance and good switching capability simultaneously. In this study, a vertically integrated junctionless FET (simply referred to as a VJ-FET) with a five-story nanowire is demonstrated for the first time on a bulk-Si substrate. The VM-FET, which is based on an IM with p-n junctions, was reported in our previous work.21 In the present study, a VM-FET with a junctionless (junction–free) structure, i.e., the VJ-FET, that reduces the variability and process complexity, is proposed. The VJ-FET is a revamped structure derived from the previous VM-FET in which the p-n junction is removed from the S/D region. In the VM-FET, there are five technical challenges that need to be addressed: (1) achieving a uniform shape and size for each nanowire among the five-story nanowires, (2) obtaining a uniform doping concentration for each nanowire, (3) achieving a uniform S/D and channel resistance, (4) mitigating the corner effect of the sharpened nanowire, and (5) creating the S/D at the exterior of the gate straddling the five-story nanowire. First, it is difficult to realize a uniform shape and size for each nanowire among the five-story nanowires when using the previously mentioned ORADEP owing to the intrinsic variability of the plasma etching process. Second, it is challenging to ensure a uniform doping concentration for each nanowire because the energy and dose during the ion implantation step must account for changes in the vertical depth of the SiNW at each level. Third, it is accordingly problematic to achieve a uniform S/D and proper channel resistance. Fourth, the corner effect can be serious in the VM-FET, especially because it is based


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on IM operation, when the cross-sectional shape of the nanowire has a sharpened apex.36 The electric field stemming from the gate voltage is intensified at the apex, causing the distribution of the mobile charges (inversion carriers) to be uneven over the cross-sectional area of the channel. This becomes more severe in the IM-FET because the flow of carriers primarily occurs at the surface of the nanowire rather than in the core. Fifth, the fabrication process used to make the pn junction in the S/D becomes increasingly complicated as the number of SiNWs is increased. This necessitates additional lithography, harsh implantation conditions with high energy and dose levels, and high throughput. Given that the fabricated five-story nanowire has a height of 1.2 µm, the need for high-energy implantation with a high dose and high throughput, which is not yet commercially available, gives rise to process complexity stemming from the multiple ion implantation steps customized for each level of the nanowire. The damage to the crystalline structure of the SiNWs during the harsh ion implantation step, which requires a recrystallization process, can increase the complexity even further. In general, recrystallization is possible when there is a referenced bulky crystalline substrate that provides a well-ordered reference lattice. However, it is difficult to apply the recrystallization process to small-scale and suspended SiNWs, which have a very limited reference crystalline phase only in the channel covered by the gate. In comparison, the VJ-FET, which does not require the formation of an S/D, can fundamentally solve the abovementioned problems of variability and process complexity. The immunity of the JL-FET based on bulk charge transport against variability is verified by the simulations in this study. Simplified fabrication is achieved by avoiding the formation of an S/D. Furthermore, compared to the JL-FET with a single nanowire, the VJ-FET with five-story SiNW channels experimentally exhibits five-fold improved performance without significant


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degradation. The VJ-FET with oxide/nitride/oxide (ONO) gate dielectrics is successfully applied to nonvolatile memory (NVM), improving its endurance and retention characteristics. Considering the continuous miniaturization trend of transistors, the combination of the junctionless structure, the vertically stacked multi-nanowire structure, and the GAA SiNW structure is a very timely approach. The synergy arising from this combination can allow the realization of an ultimately scaled CMOS device capable of high performance, suppressed SCEs, and reduced variability for use in future electronics. The fabrication process for the VJ-FET is nearly identical to that of the VM-FET described in our previous work, except for the absence of an S/D formation step.21 Details of the fabrication processes are provided in the Supporting Information. To complete the VJ-FET fabrication, one of the most important steps is to create the vertically integrated multi-nanowire structure using a bulk-Si substrate. In this study, this was formed with the aid of the optimized one-route all-dry etching process (ORADEP) illustrated in Figure 1a. There is no stiction failure caused by the all-dry etching process, whereas this was problematic in previous works reported by other groups.16-20 One cycle of the ORADEP shown in Figure 1a is a one-route etching consisting of two steps: (1) a C4F8-based polymer passivation process to protect the sidewalls of the SiNW and (2) a SF6-based isotropic dry etching process to carve and gradually separate the vertically adjacent SiNWs. As shown in Figure 1a, the C4F8-based polymer begins to passivate the entire region, including the sidewalls of the HM. The suspended nanowire is then formed by means of SF6-based isotropic dry etching. The vertically integrated multi-nanowires are achieved via iterative etching cycles, i.e., the number of etching cycles is equal to the number of SiNWs (see the Supporting Information). In the ORADEP, various parameters, including the etching time, the gas flow amount, and the plasma power, impact the shape of the final SiNWs.


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Mismatches of such parameters can result in undesirable formations of nanowires, such as broken nanowires, non-separated nanowires, and even unformed nanowires (see the Supporting Information). Therefore, the critical parameters in the ORADEP should carefully be optimized. The ORADEP conditions optimized in this study and promising approaches for further improvement with regard to the uniformity of the SiNWs are provided in the Supporting Information. Relevant images of the vertically integrated multi-nanowire structure achieved by the optimized ORADEP are shown in Figure 1b. The image on the left, obtained from a scanning electron microscope (SEM), shows the stable formation of a vertically integrated multi-nanowire without stiction. The image on the right displays a cross-sectional transmission electron microscope (TEM) image along the a-a' direction of the SEM image in Figure 1b. Doping by an iterative, high-energy and high-dose implantation process were carried out prior to the formation of the five-story SiNW. Afterwards, thermal annealing was applied at 900 °C for 60 minutes to activate the dopants and flatten the multi-peaked Gaussian doping, i.e., the dopants are uniformly distributed along the vertical direction of the wafer, as shown in Figure 1c. This process flow achieved channel doping and S/D doping at the same time, removing the need to separately form an extra S/D. A uniform doping profile throughout the five-story SiNW was verified by secondary ion mass spectrometry (SIMS), as shown in Figure 1c. In contrast, S/D implantation and a subsequent posterior annealing process are indispensable in a conventional junction-embedded IM-FET. Therefore, the effective channel length of the FET is strongly influenced by the post S/D formation and annealing step because the overlap length between the metallurgical S/D junction boundary and the gate can vary depending on the lateral straggling of the dopants originating from high-energy ion implantation and the lateral diffusion of the dopants in the subsequent annealing step. As a result, there may be extra variability in the


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conventional junction-embedded IM-FET. This problem becomes more severe as the implantation energy and the dose are increased with an increase in the number of vertically integrated nanowires. In comparison, the VJ-FET without the S/D formation process after gate patterning has strong immunity against this type of variability. Moreover, the VJ-FET does not require a process to make gate spacers and to form a thick masking layer to protect the channel region during the high-energy S/D implantation step. These reductions of cost and time realized by the simplicity of the process make this process suitable for mass production in CMOS manufacturing. Considering the mitigation of the technical challenges commonly encountered during the fabrication of a VM-FET, it is very timely to demonstrate the VJ-FET, which fully exploits the abovementioned advantages. Figure 1d schematically shows the fabricated VJ-FET. High-resolution images of the fabricated VJ-FET harnessing the five-story SiNWs are shown in Figure 2a for a logic application and in Figure 2b for an NVM application device. They show cross-sectional TEM images along the a-a' direction of the schematic in Figure 1d. The polycrystalline Si (poly-Si) used for the gate electrode completely wraps the five-story SiNWs, showing a successful GAA configuration. Close-up views of the SiNW with the oxide gate dielectric and the oxide/nitride/oxide (ONO) gate dielectrics are shown in Figure 2c and Figure 2d, respectively. Each layer is clearly distinguished via an energy-dispersive X-ray spectroscopy (EDS) mapping analysis, as shown in Figure 2e and Figure 2f. Figure 2g shows fast Fourier transform (FFT) images of each layer, i.e., SiNWs for the channel, poly-Si for the gate electrode, and oxide for the gate dielectric. A plain crystalline phase of the SiNW is observed compared to that of the other layers, supporting the stability of the ORADEP and the junction-free structure. The corner effect of the GAA MOSFET is a crucial problem due to the inverted surface, and it becomes more severe as the doping concentration is increased.36,37 A novel strategy is thus


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required to mitigate it. Owing to the non-uniformity of the SiNW shape originating from the process variability, the corner effect can be increasingly severe with a greater number of SiNWs in the VM-FET. However, when bulk conduction occurs in the core of the SiNW, this effect is weakened. A junctionless transistor is then a possible solution. This claim is supported by numerical 3-D simulations. Four different cross-sectional geometric shapes of SiNWs with the same channel area and the same gate oxide thickness are prepared for a fair comparison: (1) a circle, (2) a rectangle, (3) a triangle, and (4) a rhombus. Figure 3a shows the peak electron concentrations of the four differently shaped devices under the IM and the junctionless (JL) mode. The peak electron concentration is placed at the sharpened corner of the SiNW in the IMFET, whereas it is positioned in the core of the SiNW in the JL-FET. This is attributed to the different operating mechanisms of each FET, which are responsible for the surface charge transport in the IM-FET and the bulk charge transport in the JL-FET. In Figures 3b to 3c, the simulated results show the variation of the threshold voltage (VT) and its fluctuation (∆VT) resulting from the SiNW shape and channel doping concentration under the IM and JL mode, where ∆VT denotes the maximum difference in VT caused by the change of the SiNW shape at the same channel doping concentration, i.e., ∆VT=VT(circle shape)-VT(polygon shape: rhombus, rectangle, triangle). Both are increased as the doping concentration is increased, as expected. However, ∆VT is insensitive to the change in the doping concentration regardless of the SiNW shape in the JL-FET, while ∆VT is sensitive to this factor in the IM-FET. This trend can be understood by considering that the carriers are flowing through the core of the SiNW in the JLFET, causing ∆VT to be less sensitive to changes in the doping concentration and the SiNW shape in the JL-FET compared to in the IM-FET. If the cross-sectional channel size of the JLFET is small enough such that the gate completely controls the potential of the core SiNW in the


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fully depleted state, the peak electron concentration would be more confined at the center compared to other locations. Thus, the VT variation is no longer a concern as the cross-sectional size of the SiNW is more aggressively scaled down for the suppression of SCEs because more carriers are flowing through the area far from the corner. Therefore, robust immunity to the corner effect makes the JL-FET suitable for the implementation of the VJ-FET with a great number of SiNWs. Figure 4 exhibits the electrical characteristics of the fabricated VJ-FET. Compared to a single-nanowire-based JL-FET, the remarkably improved performance of the VJ-FET with the five-story SiNW is identified from the drain current (ID)-drain voltage (VD) characteristic shown in Figure 4a. These results are summarized in Figure 4b at the same overdrive voltage (VOD=VG – VT) for a fair comparison of the performance between two FETs with different VT values. Figure 4c exhibits the ID-VG characteristics of the two FETs, showing that the current drivability of the VJ-FET is improved by more than five-fold. With the improvement of the performance, there was no noticeable variation in the crucial parameters that can severely degrade the device performance. This high performance is favorable for the configuration of a logic circuit. However, too low a value of VT to normally maintain an ON state at a zero gate voltage may be a severe obstacle preventing practical applications. Although this low VT value of the JL-FET can be increased by reducing the channel doping concentration and the SiNW dimensions, this cannot be a fundamental solution due to the direct degradation of the current drivability.38 In this regard, the design of the VJ-FET with vertically integrated multiple-SiNW channels is suitable for the optimization of VT and the enhancement of the performance. In addition, compared to a conventional IM-FET, the scaling of the gate oxide is also a good suggestion for controlling the VT without severe degradation of the performance, which is attributed to the unique operation of


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the JL-FET as differentiated from that of an IM-FET.26,38 The inset in Figure 4c shows a comparison of the current drivability of each FET with regard to the operation mode and the number of nanowire channels. Although the JL-FET exhibits lower current drivability than the IM-FET, the design of the VJ-FET, which is based on a vertically integrated multi-nanowire channel, shows remarkably improved current drivability compared to a typical IM-FET with a single nanowire channel. Considering the attractive advantages of the JL-FET22,26 and the synergistic effects originating from the combination of the JL mode and the vertical integration of the nanowire channel, this result is meaningful for future CMOS architectures. A VJ-FET with ONO gate dielectrics was applied to NVM. Figure 5a shows the change in VT, which corresponds to the memory window, as a function of the pulse time. The VJ-FET shows stable transition characteristics, i.e., a parallel shift without degradation of SS for the programming and erasing of data, and a large memory window wider than 5 V (See the Supporting Information). In particular, the distinctive change of the memory window according to the various voltages for programming and erasing proves the adaptability of the VJ-FET for multi-level cell (MLC) operation. Figure 5b and Figure 5c show the data retention and switching endurance characteristics. Despite the vertical integration of the five-story SiNWs, the robust retention time and switching endurance in the VJ-FET are comparable to those in the single nanowire-based JL-FET (Figure 5b and Figure 5c). These results show the potential for the effective mitigation of critical problems that can stem from the use of a great number of SiNWs in multi-nanowire FETs. This immunity to variability was accomplished by employing a junctionless structure. Compared to the VM-FET, the VJ-FET has advantages in flash memory operation, including the ease of the program inhibition mode and a robust switching endurance. Figures 5d to 5f present these strengths. Because the body of the VJ-FET including the S/D


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region is homogeneously doped, i.e., n+ throughout the entire nanowire, program inhibition at an adjacent cell can be easily achieved by enhancing the potential of the S/D region, which serves as a bit line in practical memory. That is, an increase in the drain voltage reduces the potential of the gate to the SiNW for charge trapping, thereby prohibiting the programming operation (Figure 5d). Hence, the VJ-FET does not need an additional self-boosting operation39 to retain the data of the other cells during the programming operation. The suitability of the VJ-FET for MLC operation is verified by the high incremental step pulse programming (ISPP) of 0.7 V, as shown in Figure 5d. Figure 5e shows a comparison of the switching endurance capabilities of the VJFET and the VM-FET. The VJ-FET shows more reliable switching endurance than the VM-FET. This results in a larger memory window for a long retention time of 108 seconds after switching cycles (Figure 5f). Because the flash memory operates based on the movement of charges between the silicon body and the charge-trapping layer, damage to the Si/SiO2 interface inevitably occurs, which can give rise to the reliability problem. In this regard, compared to a conventional IM-FET with surface conduction, because the charge transport of the JL-FET with bulk conduction inherently occurs in the center of the SiNW channel, it can be less sensitive to the Si/SiO2 interface damage caused by repetitive programming and erasing operations. Therefore, this result is ascribed to the bulk charge transport of the VJ-FET, which is less susceptible to the Si-to-SiO2 interface characteristics being degraded by identical FowlerNordheim (FN) stress levels.40,41 In summary, a VJ-FET with a five-story GAA SiNW channel was demonstrated on a bulk-Si substrate for the first time. The proposed VJ-FET based on the inherent characteristics of the JL-FET showed strong immunity to process variability and a simple fabrication process stemming from the absence of the need to create an S/D. These aspects were proven by


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experiments and simulations. The VM-FET suggested in our previous study,21 which offers high performance, good scalability, and effective suppression of SCEs, may have a few possible vulnerabilities originating from the 3-D S/D formation onto the tall vertically integrated multinanowires and the variation of the geometric shape and size of each nanowire. However, the proposed VJ-FET fundamentally resolves these concerns via its use of a junctionless structure, maximizing the strengths of the VM-FET. Compared to the JL-FET composed of a singlenanowire channel, the VJ-FET with the five-story GAA SiNW channels exhibited a five-fold improvement in its performance without significant degradation, even after the vertical stacking of multiple nanowires. Moreover, the VJ-FET with ONO gate dielectrics was successfully applied to nonvolatile flash memory, which automatically harnessed the simplified programinhibition mode and improved the switching endurance compared to the VM-FET with five-story SiNWs. This will indeed increase the feasibility of the reliable memory based on 3-D integration with high packing density levels. The synergy effect originating from the combination of the junctionless structure and the vertically integrated GAA SiNW structure can advance an extremely scaled CMOS with high performance, effective suppression of SCEs, good scalability, and reduced process variability based on a low-cost fabrication process, prolonging the validity of Moore’s law into the next decade. More generally, this work will steadily gain acceptance as an attractive option in versatile electronics that can change our lives in the future.

Acknowledgments This work was supported by the Center for Integrated Smart Sensors funded by the Ministry of Science, ICT & Future Planning as Global Frontier Project (CISS-2011-0031848) in part. This research was partially sponsored by the Pioneer Research Center Program through the National


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Research Foundation of Korea funded by the Ministry of Science, ICT & Future Planning (Grant 2012-0009594). This work was also partially supported by Open Innovation Lab Project from the National Nanofab Center (NNFC). Supporting Information -

Fabrication process

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Optimization of the one-route all-dry etching process (ORADEP)

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Experimental equipment

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Flash memory operation

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Promising approaches to improve the uniformity of the SiNWs in the ORADEP.

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Simulation on the correlation of the channel doping concentration and the channel thickness for the performance of the JL-FET


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19. Sacchetto, D.; Ben-Jamaa, M. H.; Micheli, G. D.; Leblebici, Y. ESSDERC. Proceedings of the European 2009, 245—248.


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20. Ng, R. M. Y.; Wang, T.; Liu, F.; Zuo, X.; He, J.; Chan, M. IEEE Electron Device Lett. 2009, 30, 520—522. 21. Lee, B.-H.; Kang, M.-H.; Ahn, D.-C.; Park, J.-Y.; Bang, T.; Jeon, S.-B.; Hur, J.; Lee, D.; Choi, Y.-K. Nano Lett. 2015, DOI: 10.1021/acs.nanolett.5b03460 22. Colinge, J.-P.; Lee, C.-W.; Afzalian, A.; Akhavan, N. D.; Yan, R.; Ferain, I.; Razavi, P.; O'Neill, B.; Blake, A.; White, M.; Kelleher, A.-M.; McCarthy, B.; Murphy, R. Nature Nanotechnol. 2010, 5, 225—229. 23. Sore´e, B.; Magnus, W.; Pourtois, G. J. Comput. Electron. 2008, 7, 380–383. 24. Lee, C.-W.; Afzalian, A.; Dehdashti, N.; Yan, R.; Ferain, I.; Colinge, J.-P. Appl. Phys. Lett. 2009, 94, 0535111-1—0535111-2. 25. Migita, S.; Morita, Y.; Matsukawa, T.; Masahara, M.; Ota, H. IEEE T. Nanotechnol. 2014, 13, 208—214. 26. Ionescu, A. M. Nature Nanotechnol. 2010, 5, 178–179. 27. Lee, C.-W.; Ferain, I.; Afzalian, A.; Yan, R.; Akhavan, N. D.; Razavi, P.; Colinge, J.-P. Solid-State Electron. 2010, 54, 97–103. 28. Colinge, J.-P.; Lee, C.-W.; Ferain, I.; Akhavan, N. D.; Yan, R.; Razavi, P.; Yu, R.; Nazarov, A. N.; Doriac, R. T. Appl. Phys. Lett. 2010, 96, 073510-1—073510-3. 29. Colinge, J.-P.; Kranti, A.; Yan, R.; Lee, C.-W.; Ferain, I.; Yu, R.; Dehdashti, A.; Razavi, P. Solid-State Electron. 2011, 66, 33–37.


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30. Kranti, A.; Lee, C.-W.; Ferain, I.; Yu, R.; Akhavan, N. D.; Razavi, P.; Colinge, J.-P. Proc. IEEE Eur. Solid-State Device Res. Conf. 2010, 357–360. 31. Tai, C.-H.; Lin, J.-T.; Eng, Y.-C.; Lin, P.-H. Proc. IEEE Eur. Solid-State Device Res. Conf. 2010, 108–110. 32. Gundapaneni, S.; Ganguly, S.; Kottantharayil, A. IEEE Electron Device Lett. 2011, 32, 261—263. 33. Liu, T.-Y.; Pan, F.-M.; Sheu, J.-T. IEEE J. Electron Devices Soc. 2015, 3, 405—409. 34. Su, C.-J.; Tsai, T.-I.; Liou, Y.-L.; Lin, Z.-M.; Lin, H.-C.; Chao, T.-S. IEEE Electron Device Lett. 2011, 32, 521—523. 35. Moon, D.-I.; Choi, S.-J.; Duarte, J. P.; Choi, Y.-K. IEEE T. Electron Dev. 2013, 60, 1355— 1360.

36. Michielis, L. D.; Moselund, K. E.; Selmi, L.; Ionescu, A. M. IEEE T. Nanotechnol. 2011, 10, 810—816. 37. Yu, Y. L. J.; Cai, F. X.; Tang, W. M.; Lai, P. T.; Electron Devices and Solid-State Circuits (EDSSC). In 2013 IEEE International Conference of, 2013, 1—2. 38. Trevisoli, R. D.; Doria, R. T.; Souza, M.; Pavanello, M. A. Semicond. Sci. Tech. 2011, 26, 1—8. 39. Suh, K.-D.; Suh, B.-H.; Lim, Y.-H.; Kim, J.-K.; Choi, Y.-J.; Koh, Y.-N.; Lee, S.-S.; Kwon, S.-C.; Choi, B.-S.; Yum, J.-S.; Choi, J.-H.; Kim, J.-R.; Lim, H.-K. IEEE J. Solid-ST. Circ. 1995, 30, 1149—1156.


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40. Singh, P.; Singh, N.; Miao, J.; Park, W.-T.; Kwong, D.-L. IEEE Electron Device Lett. 2011, 32, 1752—1754. 41. Choi, S.-J.; Moon, D.-I.; Duarte, J. P.; Kim, S.; Choi, Y.-K. VLSI Symp. Tech. Dig. 20011, 74—75.

Figure Captions Figure 1. Overall process flow and device structure of the VJ-FET. (a) Schematic of the oneroute all-dry etching process (ORADEP). “HM” denotes the oxide hard mask layer pre-patterned to form a stable nanowire during the ORADEP. The ORADEP does not require carving oxidation or a sequential wet etching process to separate each nanowire. Thus, a vertically integrated multi-nanowire structure without stiction is achieved with good process simplicity. (b) SEM and TEM images of the vertically integrated multi-nanowire structure. The left and right images show a tilted SEM image and cross-sectional TEM image along the a-a' direction of the SEM image, respectively. The ORADEP permits the formation of uniform multiple nanowires via the complete separation of each nanowire. In the TEM image, silicon nitride (Si3N4) surrounding the SiNW serves as a passivation layer to protect the device during the focused-ionbeam (FIB) process for the preparation of the TEM sample. (c) Comparative SIMS results showing the doping profile by iterative channel implantation processes with different energy levels in the case of no annealing versus annealing. (d) Schematics of the fabricated VJ-FET along the channel direction (a-a') and the gate direction (b-b'). Figure 2. TEM images of the fabricated VJ-FET and various analysis results. (a) Cross-sectional TEM image of the VJ-FET along the b-b' direction in Figure 1d, where thermally grown oxide is


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employed as the gate dielectric. Five vertically integrated SiNWs with a uniform rhombus type profile were identified, showing a complete GAA configuration for all SiNWs. (b) Crosssectional TEM image of the VJ-FET with the ONO gate dielectrics to serve as flash NVM. (c), (d) Enlarged TEM images of individual SiNWs in Figure 2a and Figure 2b, respectively. A fivenm-thick gate oxide is identified in Figure 2c. In Figure 2d, the thickness of the tunnel oxide is 3 nm, that of the charge-trapping nitride is 6 nm and that of the barrier oxide is 8 nm, as clearly defined within the ONO structure. (e), (f) EDS mapping images of (c) and (d). These images clearly identify each layer. (g) FFT image of each layer.

Figure 3. 3-D numerical simulation results. (a) Cross-sectional images of the electron concentration in the variously shaped SiNWs (circle, rhombus, rectangle, and triangle) with the same gate oxide thickness. Red and violet colors signify the highest and lowest electron concentrations, respectively. The direction of the arrow indicates an increase in the electron concentration. The electron concentration is highest at the corner of the SiNW in the IM-FET, while it is highest at the core of the SiNW in the JL-FET. Thus, the JL-FET is less sensitive to the corner effect in terms of the charge transport behavior. (b) Transfer curves of the GAA SiNW FET with various shapes and channel doping concentrations. Boron was used for the IM-FET and phosphorus was used for the JL-FET, with the same doping concentration. The direction of the arrow denotes an increase in the doping concentration. (c) Changes in ∆VT and VT as a function of the channel doping concentration of each FET (IM-FET and JL-FET), where the bar for ∆VT (left Y-axis) and the line for VT (right Y-axis) are illustrated together. ∆VT=VT(circle shape)-VT(triangle shape) and VT in the JL-FET are presented as absolute values. Regardless of the shape of the SiNW, the JL-FET shows negligible values of ∆VT at the same channel doping


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concentration, proving its high immunity to variability arising from fluctuations of the geometric shape of the SiNW.

Figure 4. I-V characteristics (a) ID-VD characteristics of the JL-FET with the single nanowire and the VJ-FET with five nanowires. LG, WNW, and HNW denote the gate length, nanowire width, and height, respectively. (b) Comparison of ID with identical VOD values (=VG-VT). The VJ-FET shows high current drivability, increased by nearly fivefold. (c) ID-VG characteristics of the JLFET with the single nanowire and the VJ-FET with five nanowires. The VJ-FET shows remarkably improved performance without a significant degradation of the important switching parameters, such as the SS and the off-state leakage current. Even in the five-level stacked multinanowire structure, robust immunity to process variability is verified. Compared to a typical IMFET with a single nanowire channel, enhanced current drivability of the VJ-FET is shown in the inset of Figure 4c.

Figure 5. Memory effects of the VJ-FET with ONO gate dielectrics. (a) Programming and erasing transient characteristics of the VJ-FET. ‘PV” and “EV” denote the gate biases for the programming and erasing of the data, respectively. A high memory window of 5 V was achieved from the device without erasing saturation. (b) Comparison of the data retention characteristics between the JL-FET with the single nanowire and the VJ-FET with five nanowires. VPGM and VERS are the voltage levels for programming and erasing, respectively. Similarly, tPGM and tERS denote the times for programming and erasing, respectively. (c) Comparison of the switching endurance characteristics between the two devices in (b). A negligible difference is found


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between the two sets of experimental results, proving the high stability of the overall fabrication process. (d) ISPP programming and program inhibition mode of the VJ-FET, where VPGM is the gate bias applied for the programming operation. The program inhibition mode of the VJ-FET is easily attained by raising the potential of the drain, where the drain can be considered as an unselected bit line in practical flash NVM. A high ISPP of 0.7 V proves the suitability of the MLC operation of the VJ-FET, supported by the result of (a). (e) Comparison of the switching endurance characteristic between the VM-FET operating in inversion mode and the VJ-FET operating in junctionless mode. From the optimum conditions for the programming and erasing of each device, the initial memory window was adjusted to fairly compare the switching endurance. Compared with the VM-FET relying on the surface charge transport, negligible variation of the memory window is identified in the VJ-FET by virtue of the bulk charge transport, which is attractive for the reliability of the flash NVM. Here, “P/E” represents the programming and erasing operations of the data. (f) Comparison of post-cycling data retention characteristic between devices in two modes in (e). Due to the reliable switching endurance, the VJ-FET shows a larger memory window for the same retention time.


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Figure 1. Overall process flow and device structure of the VJ-FET. (a) Schematic of the one-route all-dry etching process (ORADEP). “HM” denotes the oxide hard mask layer pre-patterned to form a stable nanowire during the ORADEP. The ORADEP does not require carving oxidation or a sequential wet etching process to separate each nanowire. Thus, a vertically integrated multi-nanowire structure without stiction is achieved with good process simplicity. (b) SEM and TEM images of the vertically integrated multi-nanowire structure. The left and right images show a tilted SEM image and cross-sectional TEM image along the a-a' direction of the SEM image, respectively. The ORADEP permits the formation of uniform multiple nanowires via the complete separation of each nanowire. In the TEM image, silicon nitride (Si3N4) surrounding the SiNW serves as a passivation layer to protect the device during the focused-ion-beam (FIB) process for the preparation of the TEM sample. (c) Comparative SIMS results showing the doping profile by iterative channel implantation processes with different energy levels in the case of no annealing versus annealing. (d) Schematics of the fabricated VJ-FET along the channel direction (a-a') and the gate direction (b-b'). 114x70mm (300 x 300 DPI)


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Figure 2. TEM images of the fabricated VJ-FET and various analysis results. (a) Cross-sectional TEM image of the VJ-FET along the b-b' direction in Figure 1d, where thermally grown oxide is employed as the gate dielectric. Five vertically integrated SiNWs with a uniform rhombus type profile were identified, showing a complete GAA configuration for all SiNWs. (b) Cross-sectional TEM image of the VJ-FET with the ONO gate dielectrics to serve as flash NVM. (c), (d) Enlarged TEM images of individual SiNWs in Figure 2a and Figure 2b, respectively. A five-nm-thick gate oxide is identified in Figure 2c. In Figure 2d, the thickness of the tunnel oxide is 3 nm, that of the charge-trapping nitride is 6 nm and that of the barrier oxide is 8 nm, as clearly defined within the ONO structure. (e), (f) EDS mapping images of (c) and (d). These images clearly identify each layer. (g) FFT image of each layer. 88x43mm (300 x 300 DPI)


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3-D numerical simulation results. (a) Cross-sectional images of the electron concentration in the variously shaped SiNWs (circle, rhombus, rectangle, and triangle) with the same gate oxide thickness. Red and violet colors signify the highest and lowest electron concentrations, respectively. The direction of the arrow indicates an increase in the electron concentration. The electron concentration is highest at the corner of the SiNW in the IM-FET, while it is highest at the core of the SiNW in the JL-FET. Thus, the JL-FET is less sensitive to the corner effect in terms of the charge transport behavior. (b) Transfer curves of the GAA SiNW FET with various shapes and channel doping concentrations. Boron was used for the IM-FET and phosphorus was used for the JL-FET, with the same doping concentration. The direction of the arrow denotes an increase in the doping concentration. (c) Changes in ∆VT and VT as a function of the channel doping concentration of each FET (IM-FET and JL-FET), where the bar for ∆VT (left Y-axis) and the line for VT (right Y-axis) are illustrated together. ∆VT=VT(circle shape)-VT(triangle shape) and VT in the JL-FET are presented as absolute values. Regardless of the shape of the SiNW, the JL-FET shows negligible values of ∆VT at the same channel doping concentration, proving its high immunity to variability arising from fluctuations of the geometric shape of the SiNW. 132x99mm (300 x 300 DPI)


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Figure 4. I-V characteristics (a) ID-VD characteristics of the JL-FET with the single nanowire and the VJ-FET with five nanowires. LG, WNW, and HNW denote the gate length, nanowire width, and height, respectively. (b) Comparison of ID with identical VOD values (=VG-VT). The VJ-FET shows high current drivability, increased by nearly fivefold. (c) ID-VG characteristics of the JL-FET with the single nanowire and the VJ-FET with five nanowires. The VJ-FET shows remarkably improved performance without a significant degradation of the important switching parameters, such as the SS and the off-state leakage current. Even in the fivelevel stacked multi-nanowire structure, robust immunity to process variability is verified. Compared to a typical IM-FET with a single nanowire channel, enhanced current drivability of the VJ-FET is shown in the inset of Figure 4c. 143x114mm (300 x 300 DPI)


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Figure 5. Memory effects of the VJ-FET with ONO gate dielectrics. (a) Programming and erasing transient characteristics of the VJ-FET. ‘PV” and “EV” denote the gate biases for the programming and erasing of the data, respectively. A high memory window of 5 V was achieved from the device without erasing saturation. (b) Comparison of the data retention characteristics between the JL-FET with the single nanowire and the VJ-FET with five nanowires. VPGM and VERS are the voltage levels for programming and erasing, respectively. Similarly, tPGM and tERS denote the times for programming and erasing, respectively. (c) Comparison of the switching endurance characteristics between the two devices in (b). A negligible difference is found between the two sets of experimental results, proving the high stability of the overall fabrication process. (d) ISPP programming and program inhibition mode of the VJ-FET, where VPGM is the gate bias applied for the programming operation. The program inhibition mode of the VJ-FET is easily attained by raising the potential of the drain, where the drain can be considered as an unselected bit line in practical flash NVM. A high ISPP of 0.7 V proves the suitability of the MLC operation of the VJ-FET, supported by the result of (a). (e) Comparison of the switching endurance characteristic between the VM-FET operating in inversion mode and the VJ-FET operating in junctionless mode. From the optimum conditions for the programming and erasing of each device, the initial memory window was adjusted to fairly compare the switching endurance. Compared with the VM-FET relying on the surface charge transport, negligible variation of the memory window is identified in the VJ-FET by virtue of the bulk charge transport, which is attractive for the reliability of the flash NVM. Here, “P/E” represents the programming and erasing operations of the data. (f) Comparison of post-cycling data retention characteristic between devices in two modes in (e). Due to the reliable switching endurance, the VJ-FET shows a larger memory window for the same retention time. 131x96mm (300 x 300 DPI)


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