All-Inkjet-Printed Vertical Heterostructure for Wafer-Scale Electronics

Jul 1, 2019 - The channel current was controlled by adjusting the SB height at the rGO/IGZO heterojunction under application of an external gate volta...
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All-Inkjet-Printed Vertical Heterostructure for Wafer-Scale Electronics Dong Un Lim,†,⊥ Seungbeom Choi,‡,⊥ Seongchan Kim,‡ Young Jin Choi,‡ Sungjoo Lee,‡ Moon Sung Kang,∥ Yong-Hoon Kim,*,‡,§ and Jeong Ho Cho*,† †

Department of Chemical and Biomolecular Engineering, Yonsei University, Seoul 03722, Korea SKKU Advanced Institute of Nanotechnology (SAINT) and §School of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon 440-746, Korea ∥ Department of Chemical and Biomolecular Engineering, Sogang University, Seoul 04107, Korea

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‡

S Supporting Information *

ABSTRACT: In this study, we fabricated an array of all-inkjet-printed vertical Schottky barrier (SB) transistors and various logic gates on a large-area substrate. All of the electronic components, including the indium−gallium−zinc−oxide (IGZO) semiconductor, reduced graphene oxide (rGO), and indium−tin−oxide (ITO) electrodes, and the ion-gel gate dielectric, were directly and uniformly printed onto a 4 in. wafer. The vertical SB transistors had a vertically stacked structure, with the inkjet-printed IGZO semiconductor layer placed between the rGO source electrode and the ITO drain electrode. The ion-gel gate dielectric was also inkjet-printed in a coplanar gate geometry. The channel current was controlled by adjusting the SB height at the rGO/IGZO heterojunction under application of an external gate voltage. The high intrinsic capacitance of the ion-gel gate dielectric facilitated modulation of the SB height at the source/channel heterojunction to around 0.5 eV at a gate voltage lower than 2 V. The resulting vertical SB transistors exhibited a high current density of 2.0 A·cm−2, a high on−off current ratio of 106, and excellent operational and environmental stabilities. The simple device structure of the vertical SB transistors was beneficial for the fabrication of all-inkjet-printed low-power logic circuits such as the NOT, NAND, and NOR gates on a large-area substrate. KEYWORDS: inkjet printing, reduced graphene oxide, Schottky barrier, vertical transistor, heterostructure, work-function tunability

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of device architectures and logic circuits different from conventional silicon-based integrated circuits. Furthermore, unlike the channel length in conventional lateral transistors, the channel length in vertical SB transistors is defined by the thickness of the semiconductor layer; therefore, vertical SB transistors overcome the challenge of achieving a nanoscale channel length. An ultrashort channel leads to a high current density and enables fast device operation as well as low-voltage driving, the latter of which results in reduced power

raphene, which has a gapless energy band structure and a linear energy dispersion relation near the charge neutrality point, can provide a device structure that transcends the conceptual limitations of silicon devices.1−8 In particular, as the Fermi level of graphene can be precisely tuned by the application of an external electric field, graphene can be used as an electrode that controls the injection barrier at semiconductor/electrode heterojunctions.3,8−13 This, indeed, constitutes the basis of graphene-based vertical-structure Schottky barrier (SB) transistors,14−19 in which the output current level of the device can be controlled by adjusting the SB height through application of a gate bias. These verticalstructure SB transistors provide a paradigm shift in the design © XXXX American Chemical Society

Received: May 4, 2019 Accepted: July 1, 2019 Published: July 1, 2019 A

DOI: 10.1021/acsnano.9b03428 ACS Nano XXXX, XXX, XXX−XXX

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Figure 1. (a) Schematic fabrication procedure and OM images (top-right panels) of all-inkjet-printed vertical SB transistors. (b) OM image (inset) of an inkjet-printed ITO electrode and its current−voltage curves as a function of annealing temperature. (c) OM image (inset) of an inkjet-printed rGO electrode and its current−voltage curves as a function of annealing temperature. (d) Raman spectra of inkjet-printed GO reduced at various temperatures. (e) Kelvin probe force microscopy images and surface-potential histograms of an rGO electrode in contact with the PVDF-HFP ion gel at various applied voltages. (f) Variation in surface potential of an rGO electrode with gate voltage. (g) Specific capacitance and phase angle of an inkjet-printed PVDF-HFP ion-gel gate dielectric as a function of frequency. (h) Optical image of 320 allinkjet-printed transistors fabricated on a 4 in. wafer.

consumption. In addition, the vertical structure of the transistor may enable integration of various functional elements in an unconventional configuration, thereby providing a high-density, three-dimensionally integrated transistor device. A variety of vertical SB transistors based on a heterostructure consisting of graphene and various semiconducting materials such as amorphous silicon,20 twodimensional (2D) transition-metal dichalcogenides (MoS2 and WSe2),21−24 organic semiconductors,25−27 and metal oxides28−30 have been reported in previous studies. This rapidly growing interest in graphene-based vertical SB transistors could be further accelerated through development of a direct printing method for device fabrication, which is potentially an attractive alternative to conventional fabrication methods as it enables direct, maskless fabrication and leads to a significant reduction in material waste during the manufacturing process.31−34 Despite the considerable progress made in the development of high-performance vertical SB transistors, significant challenges remain in the realization of this device over a large area via a direct printing method. In this paper, we demonstrate the realization of an array of all-inkjet-printed reduced graphene oxide/indium−gallium− zinc−oxide (rGO/IGZO) vertical SB transistors on a largearea substrate and the fabrication of various logic gates using

these transistors. A commercial inkjet printing method was utilized to print all of the functional layers, including the indium−tin−oxide (ITO) and rGO electrodes, the IGZO semiconductor, and the ion-gel gate dielectric, for the fabrication of vertical SB transistors. Here, rGO was utilized as a tunable work-function electrode, whereas the ion gel, composed of an ionic liquid and poly(vinylidene fluoride-cohexafluoropropylene) (PVDF-HFP), was utilized as a gate dielectric. The vertical SB transistors were constructed by vertically sandwiching the IGZO semiconductor layer between the ITO (drain) and rGO (source) electrodes. The output current was modulated by tuning the SB height at the rGO/ IGZO heterojunction through application of a bias to the coplanar gate electrode. The ultrahigh specific capacitance of the ion-gel gate dielectric, exceeding 1 μF·cm−2, enabled effective modulation of the SB height (∼0.5 eV) at a low gate bias lower than 2 V.35−38 The resulting all-inkjet-printed vertical SB transistors showed a high current density (∼2.0 A· cm−2), a high on−off current ratio (∼106), and excellent operational and environmental stabilities. Furthermore, the vertical SB transistors were successfully assembled to realize various logic gates, such as the NOT, NAND, and NOR gates, on a 4 in. wafer.39 The development of all printed electronic components and their application to the fabrication of vertical B

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Figure 2. (a) Linear and semilogarithmic plots of output characteristics (JDS versus VDS) of an all-inkjet-printed vertical SB transistor (VGS = 0 V). (b) Semilogarithmic plot of output characteristics of a vertical SB transistor at various VGS values. (c) Energy band diagrams of vertical SB transistor at various VDS and VGS values. (d,e) Transfer characteristics at (d) VDS > 0 V and (e) VDS < 0 V. (f) Output characteristics of a vertical SB transistor at various temperatures. (g) Plot of ln(Isat/T2) versus 1/T at various VGS values. (h) SB height as a function of VGS.

reduction consequently led to high conductivity. Finally, an ion gel composed of an ionic liquid and PVDF-HFP was inkjetprinted with a drop spacing of 20 μm in order to connect the IGZO channel layer to the ITO gate electrode (see the schematic cross-sectional device structure in Figure S1). Topview optical microscopy (OM) images of the vertical SB transistor after each fabrication step are shown in Figure 1a (top-right panels). The electrical properties of each inkjetprinted layer were optimized by varying the thermal annealing temperature under ambient conditions. First, the ITO precursor solution was inkjet-printed between two Au electrodes, as shown in the inset of Figure 1b. The width and length of the ITO pattern were 200 and 600 μm, respectively. Figure 1b shows the current−voltage curves of the inkjet-printed ITO film as a function of annealing temperature. As the annealing temperature increased, the electrical resistivity decreased substantially due to an improvement in crystallinity and an increase in the carrier concentration (Figure S2).40−42 For example, the as-printed ITO film showed an electrical resistivity of ∼108 Ω·cm; however, it decreased abruptly to 9.9 × 10−2 Ω·cm after annealing at 300 °C. A further increase in the annealing temperature up to 600 °C caused the resistivity to decrease to 5 × 10−4 Ω·cm. For

SB transistors is anticipated to be an attractive strategy for the realization of scalable graphene-based electronic devices in the future.

RESULTS AND DISCUSSION Figure 1a shows the schematic fabrication procedure of an allinkjet-printed vertical SB transistor. First, a 0.5 M ITO precursor solution was inkjet-printed with a drop spacing of 40 μm onto a 4 in. Si wafer in order to form the drain electrodes, gate electrodes, and contact pads for the rGO source electrodes. After the printed ITO ink was dry, a 0.5 M IGZO precursor solution was printed with a drop spacing of 20 μm, which functioned as a channel layer. Here, in order to simplify the fabrication procedure and shorten the fabrication time, each layer was subjected to soft baking at 60 °C without high-temperature annealing. After the printed IGZO ink was dry, GO ink was inkjet-printed with a drop spacing of 40 μm onto the IGZO surface and connected to an ITO contact pad for biasing. All three printed layers (i.e., ITO, IGZO, and rGO) were then annealed at 600 °C for 2 h in air. The thermal annealing resulted in an increase in the electrical conductivity and carrier mobility of the ITO electrodes and IGZO channel layer, respectively, and caused reduction of GO to rGO; this C

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of a conventional ionic liquid or ion-gel patterned with a photoinitiator.51,52 Figure 1h shows a photographic image of an array of all-inkjet-printed vertical SB transistors and logic gates fabricated on a 4 in. wafer. Figure 2a shows linear and semilogarithmic plots of the current−voltage characteristics of the all-inkjet-printed vertical SB transistors. The rGO source electrode was grounded, whereas the bias applied to the ITO drain electrode was swept from −2 to +2 V. The SB transistor exhibited diode-type current modulation because of the rGO/IGZO vertical heterojunction. When the drain voltage (VDS) was positive, electrons flowed from rGO to IGZO. The work function of rGO is about 4.7 eV, and the conduction band edge of IGZO is about 4.4 eV;53−55 therefore, the electrons flowed across an energy barrier of ∼0.3 eV. However, when VDS was negative, electrons flowed from ITO to IGZO and then to rGO. As the work function of ITO is about 4.5 eV, the electrons could flow more easily, which resulted in a current density (JDS) in the negative VDS region higher than that in the positive VDS region. The ideality factor (n) was extracted from the Shockley ideal diode equation:

optimization of the annealing temperature of the IGZO channel layer, the transfer characteristics of inkjet-printed IGZO thin-film transistors before and after thermal annealing were investigated. As shown in Figure S3, the electron mobility of 600 °C annealed IGZO was measured to be 1.29 cm2·V−1· s−1, which was comparable to previously reported values for solution-processed IGZO transistors.43,44 Furthermore, the thermal reduction of the inkjet-printed GO film to rGO and the variation in the electrical resistivity of the rGO electrode were investigated by varying the annealing temperature. In fact, rGO could function as a tunable workfunction electrode in the vertical SB transistors because the impurity-induced broadening of the energy states of rGO caused its density of states to be similar to that of gapless graphene.45 Figure 1c shows the current−voltage characteristics of inkjet-printed GO and rGO films as functions of the annealing temperature. As the annealing temperature increased from 100 to 600 °C, the electrical resistivity of the rGO electrode decreased from 1.8 to 1.7 × 10−2 Ω·cm (Figure S4) because of the removal of a large fraction of oxygen-containing groups by the thermal reduction.46,47 GO reacts with oxygen molecules present in air, and its mass decreases gradually.48,49 At high temperatures above 600 °C, the mass of GO can decrease sharply. To examine the annealing-temperaturedependent reduction behavior of GO, the restoration of conjugated CC bonds within the GO sheets upon thermal reduction was observed by Raman spectroscopy. The Raman spectra of inkjet-printed GO in Figure 1d show two characteristic peaks: the D peak at 1359 cm−1 and the G peak at 1605 cm−1. As the annealing temperature increased, the G band of GO red-shifted to ∼1582 cm−1 and the intensity ratio of the D peak to the G peak (ID/IG) increased (0.98 for as-printed GO and 1.07 for rGO reduced at 600 °C; see Figure S5). The red shift of the G peak and the increase in ID/IG can be explained by the restoration of sp2 carbon upon the formation of small but numerous graphitic domains.50 Furthermore, the work-function tunability of inkjet-printed rGO in contact with the ion-gel gate dielectric was investigated by Kelvin probe force microscopy (KPFM). The contact potential difference between the probe tip and the rGO electrode in contact with the ion gel was measured at various voltages (−2, −1, 0, +1, and +2 V). Figure 1e shows KPFM images and histograms depicting the surface-potential distributions at various voltages. The potential energy of rGO increased with increasing voltage from 0 V (bright shades) and decreased with decreasing voltage from 0 V (dark shades). Figure 1f shows a detailed view of changes in potential extracted from the histogram in Figure 1e. The average contact surface potential changed from −0.83 to −0.36 V, and this change is in agreement with the results of temperaturedependent transport measurement described later. The relation between the contact surface potential and the work function is described as eV = Wtip − WrGO, where e is the element charge, V is the contact surface potential, Wtip is the work function of the probe tip, and WrGO is the work function of rGO. The work-function variation of rGO can be expressed as ΔWrGO = eΔV. Therefore, the work-function variation of rGO with a change in the voltage from −2 to +2 V corresponds to 0.47 eV. Figure 1g shows the capacitance− frequency plot for the printed PVDF-HFP ion-gel gate dielectric. The gate dielectric showed an ultrahigh capacitance (∼1 μF·cm−2), which is a prerequisite for low-voltage current modulation. These electrical performances are similar to those

I = I0(e qV / nkT − 1)

where I is the diode current, I0 is the reverse-bias saturation current, V is the voltage across the diode, k is the Boltzmann constant, T is the absolute temperature, and e is the elementary charge. The calculated n for the device was around 1.17, indicating the ideal diode characteristics.56,57 Figure 2b shows the output characteristics (JDS versus VDS) of the device at different gate voltages (VGS). The SB height modulation at opposite polarities of VDS is depicted in the form of schematic band structures in Figure 2c. The heterojunction between rGO and IGZO was a Schottky barrier as the Fermi level of rGO was lower than that of IGZO. At negative VGS, the SB height at the rGO/IGZO junction increased because of the lowering of the Fermi level of rGO. On the contrary, at positive VGS, the SB height decreased because of a rise in the Fermi level of rGO. When VDS was positive (upper band diagram), electrons overcame the SB and flowed from rGO into IGZO; therefore, the current density at positive VGS was high, and that at negative VGS was low. When VDS was negative (lower band diagram), electrons were injected from ITO to IGZO, and they then flowed into rGO. As the Fermi level of rGO was lower than or similar to the conduction band edge of IGZO, both the weak gate dependence and the high current density were observed. The asymmetric current modulation at opposite polarities of VDS was also confirmed from the transfer characteristics (JD versus VGS). Figure 2d,e shows the transfer curves at positive and negative VDS, respectively. JDS was measured to be 2.0 A·cm−2 at VDS = +0.5 V and VGS = +2 V, with an on−off ratio of 106. The subthreshold swing was 106.9 mV·dec−1. These electrical performances were, in fact, better than those of previously reported vertical transistors based on the graphene-sputtered IGZO heterojunction, even though our IGZO channel was prepared with a solution process.58,59 The superior performances of our devices may be originated by the effective SB height modulation within 2 V done by the ultrahigh capacitance of ion-gel gate dielectrics (which will be discussed below). Charge injection at the rGO/IGZO heterojunction in the transistors was further investigated by examining the temperature-dependent output curves measured at various VGS values (Figures 2f and S6). The net current flowing through a D

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Figure 3. (a) Maximum current density, on−off current ratio, and subthreshold swing of 160 all-inkjet-printed vertical SB transistors. Out of the total of 160 devices, 80 were measured under vacuum and the remaining 80 were measured in air. (b) Evolution of transfer curves of allinkjet-printed vertical SB transistors with time under applied VGS (+1 V) stress. (c) Variation in maximum current density, on−off current ratio, and subthreshold swing of devices extracted from the curves in (b). (d) Cyclic test of devices under variation of VGS from +2 to −2 V (VDS = +0.5 V). (e) Evolution of transfer curves during long-term air storage.

semiconductor with a Schottky contact can be described as a model of thermionic emission of electrons across the SB formed at the heterojunction. According to the thermionic emission theory,60 the diode saturation current (Isat) is related to the SB height (φB) as shown in the Richardson equation: ij −(φ − q3V /4πε ε d j 0 r B J = A*T 2 expjjjj j kBT k 1 T

yz zz zz zz {

Isat

( ):

and ln

T2

1 T

under varying temperature and VGS. This plot

could be approximated by a linear line at all temperatures except low temperatures because the ion-gel gate dielectric froze at low temperatures. From the slopes of the linear plots in Figure 2g, the SB height was calculated for each VGS. As VGS increased from −2 to +2 V, the barrier height decreased from 0.58 to 0.05 eV. This change in the barrier height is almost identical to the value measured by KPFM (∼0.5 eV), which supports the basis of modulation of the SB height at the rGO/ IGZO heterojunction by VGS (Figure 2h). Figure 3a shows the measured electrical properties of a total of 160 all-inkjet-printed vertical SB transistors. Here, 80 devices were measured under vacuum, and the remaining 80 were measured in air. As can be seen in Figure 3a, the distributions of JDS (measured at VDS = +0.5 V and VGS = +2 V) and the subthreshold swing were almost similar in both the measurement environments. However, the on−off current ratio

This equation can be rearranged as follows by considering the relation between

Isat

( ) versus

ln

qφ 1 iI y lnjjj sat2 zzz = − B + ln(AA*) k T kT { T2

where q is the element charge, A is the junction area, and A* is the effective Richardson constant. Figure 2g shows a plot of E

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Figure 4. (a) Logic circuit diagrams of NOT gate (inverter), NAND gate, and NOR gate. (b) Voltage-transfer characteristics and signal gains of all-inkjet-printed vertical SB transistors. (c) Output voltages of NAND and NOR gates under variation of input voltages.

transistor was turned off through application of a negative input voltage (VIN), VDD became equal to the output voltage (VOUT). As VIN increased, the drive transistor was turned on and connected to the ground, which resulted in VOUT of 0 V. Similarly, a NAND gate was fabricated by connecting three identical vertical SB transistors in series. Additionally, a NOR gate was fabricated by connecting two vertical SB transistors in parallel and one vertical SB transistor in series (Figure 4a). Figure 4c shows the VOUT values of the NAND and NOR gates under variation of the two VIN values, that is, VA and VB. When VIN (VA or VB) was +2 V, the logic state was “1”, whereas it was “0” when VIN was −2 V. In the NAND gate, as the two input transistors were connected in series, the output terminal was connected to the ground when the two input transistors were turned on. When both VA and VB were in the logic state “1” [input logic state of (1, 1)], the NAND gate was in the logic state “0”. Other input logic states, that is, (0, 0), (0, 1), and (1, 0), yielded the output logic state “1”. In the NOR gate, the two input transistors were connected in parallel; therefore, the output terminal was connected to the ground when either of these two transistors was turned on. The input states of (0, 1), (1, 0), and (1, 1) yielded the output logic state “0”. VOUT was in the logic state “1” only when both VA and VB were in the logic state “0”.

of the devices measured in air was higher than that of the devices measured under vacuum. The higher on−off current ratio of the devices measured in air was thought to be a result of the p-type doping of rGO by the oxygen in air. The Fermi level of rGO was lowered by p-type doping, and as a result, the SB height at the rGO/IGZO heterojunction increased. To examine the operational stability of the vertical SB transistors, a bias stress test was performed. Figure 3b shows the evolution of transfer curves under a positive VGS stress condition (VGS = +1 V). The transfer characteristics remained almost unchanged over 5000 s and shifted very slightly. Figure 3c summarizes the variations in the maximum JDS, on−off current ratio, and subthreshold swing under a continuous VGS stress condition. All of the values were found to be extremely stable. A dynamic stress test was also performed, wherein the all-inkjet-printed vertical SB transistors were turned on and off for 10 000 cycles by changing VGS from +2 to −2 V (with VDS of +0.5 V). As shown in Figures 3d and S7, the on−off current ratio remained almost unchanged, indicating stable device operation. A longterm stability test was also performed in which the device was stored in air. The evolution of transfer curves during long-term air storage is shown in Figure 3e. The initial on-current was 8.2 × 10−5 A, which decreased to 2.8 × 10−5 A after 100 days and to 2.2 × 10−5 A after 200 days. The transfer curves of the device showed a slightly positive shift during air storage, but the on−off current ratio remained almost unchanged even after 200 days. Various logic gates, including NOT, NAND, and NOR, were fabricated using the all-inkjet-printed vertical SB transistors, and their logic functions were analyzed. A NOT gate (inverter) was constructed by connecting two identical SB transistors in series (Figures 4a and S8). Both the gate electrode and the source electrode of the load transistor were connected to the drain electrode of the drive transistor. As shown in Figure 4b, the NOT gate exhibited ideal voltage-transfer characteristics with a signal gain of ∼4 at VDD = 0.5 V. When the drive

CONCLUSION In conclusion, all-inkjet-printed vertical SB transistors were realized by printing all the electronic components, that is, ITO, IGZO, rGO, and PVDF-HFP ion gel. Through optimization of the printing parameters and fabrication process, vertical SB transistors with a high current density, large on−off current ratio, and low subthreshold swing could be successfully fabricated on a large-area substrate. In particular, the currentdriving characteristics of the SB transistors were regulated by changing the work function of rGO and the corresponding SB height at the rGO/IGZO heterojunction. Furthermore, to F

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ASSOCIATED CONTENT

demonstrate the possible applicability of the all-inkjet-printed vertical SB transistors, they were used to assemble logic gate circuits such as NOT, NAND, and NOR in a scalable manner. We note that these all-printed devices were annealed at relatively high temperature, which prevent direct application to plastic substrates. Exploiting the low-temperature processing methods of device components, printed vertical SB transistors with decent performances will bring innovative impact in the field.

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsnano.9b03428. Additional experimental details and figures; schematic cross-sectional image of the device; electrical resistivity of inkjet-printed ITO and rGO; transfer characteristics of the IGZO transistor; Raman intensity ratio (ID/IG) of inkjet-printed rGO; temperature-dependent output curves of devices; magnified plot of the initial and the final regions of the cyclic test; OM images of logic gates (PDF)

METHODS Ink Preparation. The graphene oxide (GO) was synthesized using a modified Brodie method.61,62 Ethylene glycol (20 wt %, Sigma-Aldrich) was mixed in GO solution. Indium−tin−oxide solution was prepared by adding a 0.5 M mixture of indium nitrate hydrate (Sigma-Aldrich) and tin chloride (Sigma-Aldrich, Korea) with a 9:1 ratio to 2-methoxyethanol (Sigma-Aldrich) and stirring the mixture for 24 h. Indium−gallium−zinc−oxide solution was prepared by adding a 0.5 M mixture of indium nitrate hydrate, gallium nitrate hydrate, and zinc acetate dihydrate (all from Sigma-Aldrich) with a 9:1:2 ratio to 2-methoxyethanol and stirring the mixture for 24 h. Iongel solution was prepared by adding a 4:1 mixture of 1-ethyl-3methylimidazolium bis(trifluoromethylsulfonyl)imide (Merck) and poly(vinylidene fluoride-co-hexafluoropropylene) (Sigma-Aldrich, Mn ∼ 110 000) to N,N-dimethylformamide (Sigma-Aldrich, anhydrous, 99.8%) and then stirring the resulting mixture at 60 °C for 24 h. Device Fabrication. The vertical SB transistor device was fabricated using a commercial piezoelectric Dimatix Material Printer (DMP-2850, Dimatix-Fujifilm, Inc.) equipped with a disposable cartridge (DMC-11610, Fujifilm, ∼10 pL nominal droplet volume) containing 16 nozzles (each 21 μm in diameter). The distance between nozzle and the substrate was around 1 mm. In the printing of the ITO solution, the droplet was adjusted at a nozzle temperature of 30 °C and then printed with a drop spacing of 40 μm. In the printing of the IGZO solution, the droplet was generated at a nozzle temperature of 30 °C and then printed with a drop spacing of 20 μm. In the printing of the GO solution, the droplet was adjusted at a nozzle temperature of 30 °C and then printed with a drop spacing of 40 μm. Thermal annealing was performed at 600 °C under ambient conditions. In the printing of the ion-gel solution, the droplet was adjusted at a nozzle temperature of 50 °C and then printed with a drop spacing of 20 μm. All processes except for printing of the ion-gel solution were performed on a UV-treated substrate to ensure hydrophilicity, and the substrate temperature was kept at 60 °C for all of the processes. The channel area overlapping between the top rGO and the bottom ITO electrodes was around 50 × 100 μm2. KPFM Measurement. For KPFM measurements, polydimethylsiloxane (PDMS) was spin-coated onto an ITO glass substrate to form a thin film. Then, the central part of the PDMS film was cut out, and the resulting hollow space was filled with ion gel through printing. The edge of the PDMS film was cut off to apply the voltage to the ITO electrode. Separately, GO was printed on a Si wafer and then annealed at 600 °C. The rGO formed by reduction of GO was floated by immersing the substrate in hydrofluoric acid (HF) solution by dissolving the SiO2 layer. The floated rGO was transferred to deionized water by means of a plastic film. When HF was sufficiently washed out after 2 h, rGO was transferred onto the preprepared substrate containing PDMS and the ion gel. The silver paste was applied to the rGO layer over the PDMS film for grounding. Measurements. The degree of reduction of GO was measured using a micro-Raman spectrometer (Alpha300 M+, WITec GmbH). The surface potential of rGO was measured by KPFM using an atomic force microscope (NX10, Park Systems). All devices were measured using a probe station (Keithley 4200).

AUTHOR INFORMATION Corresponding Authors

*E-mail: [email protected]. *E-mail: [email protected]. ORCID

Sungjoo Lee: 0000-0003-1284-3593 Yong-Hoon Kim: 0000-0003-0057-1893 Jeong Ho Cho: 0000-0002-1030-9920 Author Contributions ⊥

D.U.L. and S.C. contributed equally to this work.

Notes

The authors declare no competing financial interest.

ACKNOWLEDGMENTS This work was supported by a grant from the Center for Advanced Soft Electronics (CASE) under the Global Frontier Research Program (2013M3A6A5073177) and the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2017R1A2B2005790, 2017R1A4A1015400, and 2017R1E1A1A01077189). REFERENCES (1) Estrada, D.; Li, Z.; Choi, G.-M.; Dunham, S. N.; Serov, A.; Lee, J.; Meng, Y.; Lian, F.; Wang, N. C.; Perez, A.; Haasch, R. T.; Zuo, J.M.; King, W. P.; Rogers, J. A.; Cahill, D. G.; Pop, E. Thermal Transport in Layer-by-Layer Assembled Polycrystalline Graphene Films. NPJ. 2D Mater. Appl. 2019, 3, 10. (2) Yu, X.; Li, Y.; Hu, X.; Zhang, D.; Tao, Y.; Liu, Z.; He, Y.; Haque, M.. A.; Liu, Z.; Wu, T.; Wang, Q. J. Narrow Bandgap Oxide Nanoparticles Coupled with Graphene for High Performance MidInfrared Photodetection. Nat. Commun. 2018, 9, 4299. (3) Behura, S. K.; Wang, C.; Wen, Y.; Berry, V. Graphene− Semiconductor Heterojunction Sheds Light on Emerging Photovoltaics. Nat. Photonics 2019, 13, 312−318. (4) Yang, Y.; Ma, T.; Wang, Z.; Lu, Z.; Li, Y.; Fu, C.; Chen, X.; Zhao, M.; Olson, M. S.; Liu, J. Seamless Lateral Graphene P-N Junctions Formed by Selective In Situ Doping for High-Performance Photodetectors. Nat. Commun. 2018, 9, 5449. (5) Schwierz, F. Graphene Transistors. Nat. Nanotechnol. 2010, 5, 487−496. (6) Wu, Y. Q.; Lin, Y. M.; Bol, A. A.; Jenkins, K. A.; Xia, F. N.; Farmer, D. B.; Zhu, Y.; Avouris, P. High-Frequency, Scaled Graphene Transistors on Diamond-Like Carbon. Nature 2011, 472, 74−78. (7) Liao, L.; Lin, Y. C.; Bao, M. Q.; Cheng, R.; Bai, J. W.; Liu, Y. A.; Qu, Y. Q.; Wang, K. L.; Huang, Y.; Duan, X. F. High-Speed Graphene Transistors with a Self-Aligned Nanowire Gate. Nature 2010, 467, 305−308. G

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DOI: 10.1021/acsnano.9b03428 ACS Nano XXXX, XXX, XXX−XXX