Ambipolar Barristors for Reconfigurable Logic Circuits - Nano Letters

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Ambipolar Barristors for Re-configurable Logic Circuits Yuan Liu, Guo Zhang, Hailong Zhou, Zheng Li, Rui Cheng, Yang Xu, Vincent Gambin, Yu Huang, and Xiangfeng Duan Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.6b04417 • Publication Date (Web): 06 Feb 2017 Downloaded from http://pubs.acs.org on February 10, 2017

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Ambipolar Barristors for Re-configurable Logic Circuits Yuan Liu†, Guo Zhang‡, Hailong Zhou‡, Zheng Li‡, Rui Cheng†, Yang Xu‡, Vincent Gambin§, Yu Huang†,⊥*, and Xiangfeng Duan‡, ⊥* †

Department of Materials Science and Engineering, University of California, Los Angeles, CA

90095, USA; ‡Department of Chemistry and Biochemistry, University of California, Los Angeles, CA 90095, USA; §NG/NEXT, Northrop Grumman Aerospace Systems, Redondo Beach, CA 90278, USA; ⊥California Nanosystems Institute, University of California, Los Angeles, CA 90095, USA. *Corresponding email: [email protected], [email protected]

Abstract: Vertical heterostructure based on graphene have emerged as a unique architecture for novel electronic devices with unusual characteristics. Here we report a new design of vertical ambipolar barristors based on metal-graphene-silicon-graphene sandwich structure, using bottom graphene as a gate-tunable "active contact", top graphene as an adaptable Ohmic contact, and low doping thin silicon layer as the switchable channel. Importantly, with finite density of states and weak screening effect of graphene, we demonstrate, for the first time, that both the carrier concentration and majority carrier type in the sandwiched silicon can be readily modulated by gate potential penetrating through graphene. It can thus enable a new type of ambipolar barristors with an ON-OFF ratio exceeding 103. Significantly, these ambipolar barristors can be flexibly configured into either p-type or n-type transistors and used to create integrated circuits with reconfigurable logic functions. This unconventional device structure and ambipolar reconfigurable characteristics can open up exciting opportunities in future electronics based on graphene or two dimensional van der Waals heterostructures.

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Keywords: vertical transistor, van der Waals heterostructure, tunable diode, ambipolar, graphene weak screening TOC


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Graphene has emerged as an exciting material for future electronics due to its superior electrical1-5, optical and mechanical properties6-9. However, the lack of an intrinsic bandgap in graphene has limited the achievable ON-OFF ratio in transistors using graphene as the “active channel”. The creation of a transport gap in graphene nanostructures10-12 or bilayer graphene13,14 can improve the ON-OFF ratio, but often at the sacrifice of the deliverable current density. Alternatively, exploiting graphene as a unique “active contact” with tunable work function in van der Waals (vdW) heterostructures, new designs of vertical thermionic transistors15-29 (barristors) or tunneling devices30-34 have been created with greatly improved ON-OFF ratio and current density. Importantly, with finite density of states and weak screening effect, graphene is partially electrostatic transparent and can allow the use of an external gate to modulate the current injection efficiency through the graphene-semiconductor junction. To date, such vertical transistors have been limited to single carrier type determined by the intrinsic doping type of the semiconductor itself. Here we demonstrate, for the first time, that the electrical field of an external gate penetrating through graphene can readily switch the carrier type between electrons and holes in a vertical metal-graphene-silicon-graphene heterostructure, resulting in a unique type of ambipolar barristors. We further show that such ambipolar barristors can be flexibly configured into either p-type or n-type transistors with the ON-OFF ratio exceeding 103, and used to create integrated circuits with reconfigurable logic functions. This unconventional device structure and ambipolar reconfigurable device characteristics can open up exciting opportunities for future electronic devices and integrated circuit design.


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Figure 1. Schematic illustration and structural characterization of graphene-silicon ambipolar Schottky barrier device. (a, b) A three-dimensional perspective (a) and cross section (b) schematic of the device structure. The bottom graphene functions as a tunable source electrode (blue) and the top metal/graphene hybrid stack works as drain electrode (red). A 80-nm thick silicon is sandwiched in between as the switchable channel. (c) False-color SEM image of a typical device, where corresponding metal/GrT drain contact (gold), GrB source contact (blue) and silicon (gray) are clearly shown. Scale bar is 5 µm. Figure 1a, b shows the schematic illustration of the device structure. To fabricate the device, graphene, grown by chemical vapor deposition (CVD)35, is first transferred onto a silicon substrate with a 60 nm thick SiNx layer as a dielectric, followed by photolithography and oxygen plasma etching to form graphene stripe (10×50 µm) as the bottom graphene electrode (GrB). Thin film silicon stripes (~80 nm thick, p-type, 6×1014/cm3) are then created from a silicon-oninsulator (SOI) substrate and transferred onto the top of GrB stripes using a transfer technique36 (Supplementary Information S1 and S2). Next, a second layer of pre-patterned top graphene (GrT) stripes are transferred again on the top of the silicon using standard alignment transfer technique. Finally, metallization is performed by e-beam evaporation of Cr/Au (20/80 nm) on top of GrT, creating metal/GrT hybrid top contact to silicon, as shown in the schematics in Fig. 1a and 1b. This unique hybrid top contact here offers two advantages, which are essential for the operation


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of our ambipolar barristors. First, GrT functions as the top buffer layer here to avoid Fermi level pinning effects by conventional metal contact15,37, which would otherwise greatly reduce the ON-OFF ratio of the resulting device (Supplementary Information S3). Second, compared with GrB-Si contact, the top metal layer provides a large density of states for tunneling, thereby enabling more linear and Ohmic top contact. Together, the metal/GrT stack forms an adaptable Ohmic contact to both the p-channel and n-channel devices. This point will be discussed in detail below. Figure 1c shows a false-color scanning electron microscopy (SEM) image of a typical fabricated device.

Figure 2. Room temperature electrical properties of the ambipolar barristors. (a) Ids-Vds output characteristic of a ambipolar barristor under various gate voltage from -25 V to 25 V (5 V step), with a p-type SB diode behavior under negative gate voltage (-25 V, black curve) and a n-type SB diode behavior under positive gate voltage (25 V, red curve). The semi-log plot is shown in the inset with gate voltages of -25 V and 25 V. (b) Ids-Vg transfer characteristics in positive drain bias region at various bias Vds from 0.25 V to 1.5 V at a step of 0.25 V, highlighting a p-type transistor behavior. (c) Ids-Vg transfer characteristics in the negative drain bias region at various bias Vds from -0.25 V to -1.5 V with a step of 0.25 V, indicating an n-type transistor behavior. 5 ACS Paragon Plus Environment

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Electrical transport studies of the resulting devices were carried out at room temperature under ambient conditions, with the GrB grounded as the source electrode (as labeled in Fig. 1a). Under negative gate bias, the output characteristic clearly shows a rectifying behavior, with the source-drain current only passing in the positive bias regime (Fig. 2a, black curve), indicating a p-type Schottky barrier (SB) characteristics. While applying the positive gate voltage, an opposite output characteristic is observed where current can only pass in negative bias regime, suggesting an n-type SB (Fig. 2a, red curve). Semi-log plot with both positive and negative gate voltage clearly shows the switch of barrier polarity by gate voltage (Fig. 2a, inset). It is should be noted that the majority carrier type in the heterostrucuture devices remains the same at a given gate voltage (e.g., electrons at positive gate voltage and holes at negative gate voltage) regardless of bias voltage or the rectifying current-voltage relationship. We have therefore named the device as the “ambipolar barristors”. With the tunable barrier polarity in output characteristic, the ambipolar barristors exhibit a rather unique transfer behavior: under positive Vds regime, source-drain current increases with increasing negative gate voltage, mimicking a PMOS behavior (Fig. 2b); while under negative Vds regime, source-drain current increases with increasing positive gate voltage, showing a NMOS behavior (Fig. 2c). In this way, these gate tunable Schottky diodes form unique ambipolar barristors and can be configured into either a pchannel or n-channel transistors by controlling the direction of applied bias voltage. Because of the small silicon thickness, the charge transport in the vertical heterostructure is largely determined by the two silicon-graphene contact junctions, and the majority carrier type is determined by the direction of gate electrical field. The vertical carrier flow between two graphene electrodes and across thin film silicon resembles that in typical graphene based barristor behavior16, 21, 22. This is intrinsically different from conventional p-n heterostructure 6 ACS Paragon Plus Environment

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diode38, which is majorly limited by lateral charge transport. Within our device structure, asymmetric graphene contact configurations are applied, where GrB is used as an “active contact” to form a SB with silicon, and GrT acts as physical/electronic buffer layer to form an adaptable contact to either p-type or n-type silicon channel.

Figure 3. Measurement of planar Si device with different contact geometries. (a) Schematics of silicon device contacted by only GrB. (b) Ids-Vds output curve of the device shown a, demonstrating a clear back-to-back diodes characteristic. c, Ids-Vg transfer curve of the device shown in a, at various temperature from 300 K to 100 K (50 K step), and 77 K. Ids decrease with temperature, suggesting the carrier transport is dominated by thermionic emission. (d) Schematics of planar silicon device contacted by metal/GrT hybrid stacks. (e) Ids-Vds curve of the device shown d, demonstrating a more linear output characteristic compared with GrB contacted devices in both p-type region and n-type region (inset). (f) Ids-Vg transfer curve of the device shown in d, at various temperature from 300 K to 100 K (50 K step), and 77 K. Much larger Ids current (~3 orders of magnitude) is observed. Ids is insensitive to temperature, suggesting the carrier transport is dominated by tunneling/field emission process.


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To better understand the transport mechanism of our device and probe the difference between top and bottom Si-graphene contact geometries, we have fabricated and studied the planar devices (using the same transferred SOI) with only GrB contacts (Fig. 3a) or only metal/GrT hybrid contacts (Fig. 3d), respectively. The device with only GrB contacts (Fig. 3a) shows non-linear Ids-Vds output curve with relatively small saturation current level (~10 nA) at both the positive and negative bias (Fig. 3b and Fig. S4), demonstrating typical back-to-back Schottky diode characteristics. Additionally, the temperature dependent measurement shows that the measured current (Ids) decrease exponentially with temperature (Fig. 3c), suggesting the carrier transport is dominated by thermionic emission, consistent with Schottky diode behavior observed previously between graphene and silicon15. In contrast, for the planar device with top metal/GrT-Si contact, much more linear Ids-Vds output curve with larger Ids current (~3 orders of magnitude, ~10 µA) is observed (Fig. 3e, f and Supplementary Fig. S5), indicating a much better contact than the bottom GrB-Si geometry. The improved top hybrid contact can be attributed to two effects. First, the presence of the top metal layer can significantly increase the density of states in the GrT, and thus the tunneling probability, especially at large gate voltage. This tunneling/field emission mechanism is further confirmed by temperature dependent measurement (Fig. 3f and Fig. S5), where device Ids-Vg transfer curve is insensitive to reducing temperature and a much more linear Ids-Vds output can be observed under low temperature (77 K). Secondly, compared with GrB-Si interface, the deposition of the top metal layer may significantly reduce the vdW gap between GrT and silicon, thus reducing the tunneling barrier thickness, and enhancing the carrier injection. This is consistent with previous reports by using a metal/graphene hybrid contact to reduce contact resistance in various semiconductor materials (e.g. Si39, GaN40, AlGaN41, MoS242,43). It is particularly interesting to note the nearly linear Ids-


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Vds output curves are achieved in the device metal/GrT contact at both positive (n-type silicon) and negative (p-type silicon) gate voltage, demonstrating nearly Ohmic contact are achieved for both p-type and n-type silicon. Together, these studies demonstrate that the top contact (metal/GrT) forms an adaptable contact to both the p-type and n-type silicon channel with negligible contact resistance (with 3 orders of magnitude larger current injection), when compared to bottom GrB-Si contact where the carrier transport is dominated by the Schottky barrier at GrB-Si interface. Based on the different transport mechanisms observed in the GrB-Si and metal/GrT-Si system, we can plot the band diagram of the device (Figure 4a-c), in which the carrier transport across GrB-Si is controlled by the thermionic emission (TE), and the metal/GrT-Si junction is largely dictated by field emission (FE) with much smaller contact resistance for both p-type and n-type silicon, and the overall carrier transport and device electrical characteristics are dominated by the GrB-Si interface. In general, owning to the quantum capacitance and partial electrostatic transparency of the monolayer graphene1, the gate voltage applied across the vertical structure not only modulate the doping level or work function of the GrB30,31,44 (Fig. 4b,c), but can also penetrate through graphene to accumulate/inverse space charge within thin film silicon45. In our experiment, SOI with a low doping level is used (p-type, 6×1014/cm3) and electrical field as high as 4×106 V/cm is applied. With such a low doping level, the electrical field penetrating through GrB could readily control the charge concentration inside the silicon, as well as the polarity of the majority carriers (e- or h+) in the entire system. When the Vg is positive, the whole system is comprised of electrons conducting (Fig. 4b), while if the gate voltage Vg is negative, holes become the majority carriers (Fig. 4c). In this way, a negative gate voltage accumulates holes in silicon and results in a p-type SB with GrB; while a gate bias of positive voltage switches the 9 ACS Paragon Plus Environment

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majority carriers to electrons resulting in an n-type SB at GrB-Si interface. This model fits well with our experimental results shown in figure 2a-c, and is also consistent with the recent simulation report based on graphene quantum capacitance and silicon capacitance45.

Figure 4. Characterization of tunable and switchable Schottky barrier. (a-c) Band diagram schematics of device structure at positive gate voltage (b), negative gate voltage (c), and its corresponding cross-section schematics (a). Red and blue curve represent the band-diagram under negative and positive bias, respectively. (d-f) Scanning photocurrent mapping of GrBsilicon junction at different gate voltage. The optical image of mapped device is shown in d, with blue line outlining bottom graphene and red dash line outlining mapped area. Negative photocurrent is observed at -30 V gate voltage (e), indicating a p-type SB; and positive photocurrent is shown at 30 V gate voltage (f), suggesting an n-type SB. Laser power is 5 µW and wavelength is 514 nm. (g, h) Temperature dependent measurement of SB height. In(Isat/T2) is plotted at various temperature and gate voltage. Gate voltage from 10 V to 25 V (5 V step) is shown in g; and from -25V to -5 V (5 V) is shown in h. (i) Measured open circuit voltage (black square), extracted barrier (red dot) height from g, h, and simulated barrier height (blue curve). 10 ACS Paragon Plus Environment

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The ambipolar behavior and tunable Schottky barrier can be further confirmed using scanning photocurrent mapping method. For this study, only the GrB-Si junction is mapped and the top hybrid contact (metal/GrT-Si) is applied on the side without a vertical overlap with GrB (shown in device schematics in Fig. S6). Importantly, strong negative photocurrent is observed under a negative gate voltage (Fig. 4e), indicating holes are the majority carrier; while a positive photocurrent is observed under a positive gate voltage (Fig. 4f), suggesting the majority carrier is inverted into electrons. Besides the polarity of the barrier, the amplitude of the build-in potential can also be estimated using photocurrent measurements. Under laser illumination, photogenerated open circuit voltage (VOC) at various gate voltages can be determined (Fig. 4i, and see supporting information figure S7 for details), which is directly related to the Fermi level difference between GrB and silicon. Temperature dependent measurement is further conducted to investigate the modulation and switching of barrier type at GrB–Si interface of the ambipolar barristors. Under reverse bias, the Schottky barrier diode saturation current can be expressed using following equations37:

I sat = AA*T 2 exp(

− qϕb ) kT

where A is the Schottky junction area, A* is the effective Richardson constant, q is the element charge, k is the Boltzmann constant and T is the temperature. Under the reverse bias regime, the diode current is only determined by temperature T and barrier height ϕb . Thus the barrier height

ϕb under different gate voltage can be readily derived from the Arrhenius plot (shown in Fig. 4g, 4h) and summarized in Fig. 4i. The extracted barrier height varies from 0.04 eV to 0.16 eV in ptype Schottky barrier regime, switches to a negative value of -0.06 eV to -0.13 eV in the n-type 11 ACS Paragon Plus Environment

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Schottky barrier regime (red dot in Fig. 4i), qualitatively matching well with the photocurrent measurement. The unique tunable barrier height and direction by gate voltage further confirm the Schottky barrier and thermionic emission dominate the overall carrier transport. Other mechanism such as tunneling through native oxide pose little series resistance and can be neglected in our devices, consistent with previous reports about the role of native oxide in graphene-low dope silicon junction34. Furthermore, we have also calculated the barrier height at the GrB-Si junction as a function of the gate voltage (blue curve in Fig. 4i) (See Supplementary information 8 for details). Importantly, the calculated barrier height and barrier switching effect show a high degree of consistency with experimental results, confirming that our proposed working mechanism model is consistent with our device behavior. A relatively small difference of the exact values is also observed between the experimental and theoretical values. These differences might be attributed to non-ideality of the fabricated devices. In general, our theoretical model of GrB-Si interface is based on ideal thermionic emission model for an ideal device with ideal silicon-graphene interface, while the experimental conditions could be more complicated. For example, besides GrB-Si a predominant thermionic emission mechanism, other mixed mechanisms (e.g., field emission and thermionic field emission) may also contribute to carrier transport across the Schottky diode. Additionally, impurities or residue between GrB-Si interfaces may also cause partial surface pinning effect or surface doping effect, which is not considered in our ideal model and could impact the carrier transport resulting in a barrier height deviating from the ideal model. With the unique ambipolar diode and barristor characteristics, our vertical devices could function as reconfigurable transistors, with the output characteristics readily switchable by the specific gate voltage and bias voltage combinations. This unique feature can be used to create 12 ACS Paragon Plus Environment

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useful reconfigurable logic functions. For example, by connecting with a pull-down resistor, our device becomes a gate controllable filter. As shown in figure 5a, a square wave range from -1.5 V to 1.5 V is input from GrT, and a GrB electrode is connected to a 9 MΩ resistor. By applying a positive gate voltage (30 V), an n-type Schottky barrier is formed and only negative current will pass (red line, Fig. 5a); conversely, a p-type Schottky barrier is formed under a negative gate voltage (-30 V), resulting in a positive-pass filter (red line, Fig. 5a). With zero gate voltage, a high barrier height is formed in both ways and all the signals are filtered. The time constant of our wave filter is 2.5 µs (Supporting Information Fig. S9), which is largely limited by the parasite capacitance between source-drain electrodes and back gate.

Figure 5. Reconfigurable logic functions from integrated ambipolar barristors. (a) Gate tunable wave filter made by a single ambipolar barristor. Pull-down resist is 9 MΩ and the input signal is square wave ranging from 1.5 V to -1.5 V. Output filtered signal is strongly dependent on the gate voltage. Negative gate (-30 V) result in positive-pass filter (black curve) and positive gate 13 ACS Paragon Plus Environment

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will result in negative-pass filter (red curve). (b) CMOS inverter is achieved by two ambipolar barristors (as two VFETs) integrated in serial. As shown in the left inset, VFET1 works as p-type barristor and VFET2 behave as n-type barristor, with inverting output characteristics shown by red line. When the VDD and GND exchanged (right inset), VFET1 works as n-type barristor and VFET2 behave as p-type barristor, resulting similar switching curve despite the application of an opposite power supply. (c) NAND and NOR logic function achieved by one circuit with four integrated VFETs. Left schematics demonstrated NAND logic circuit, where VFET1 and VFET2 are used as p-type barristor and VFET3 and VFET4 is used as n-type barristor. When VDD and GND exchanged with each other (right schematics), VFET1 and VFET2 switch into n-type barristor and VFET3 and VFET4 switch into p-type barristor. In this case, logic NOR function is achieved. (d) Output voltage levels of logic NAND and NOR at four typical input from circuit in c . Red curve represent the NAND logic output and blue curve represent the NOR logic output. VDD is 3 V.

The ability to switch polarity of the Schottky barrier at the graphene-silicon interface can readily allow configuration of devices into either p-type or n-type vertical field effect transistors (VFETs) depending on the direction of applied source-drain bias. For example, a positive bias from GrT to GrB (grounded) will result in p-type barristor behavior (Fig. 2b), while a positive bias from GrB to GrT (grounded) will result in n-type barristor behavior (Fig. 2c). The ability to reconfigure such vertical transistors can allow the creation of complex logic functions with single types of devices. For example, CMOS function can be achieved by properly connecting and biasing such vertical transistors, which could greatly simplify the circuit design and fabrication process. Additionally, the fact that p-type barristor and n-type barristor are interchangeable can be an advantage in designing and integrating logic circuits. As a proof of concept, an inverter is achieved by connecting two ambipolar VFETs together (Fig. 5b, left schematics). VFET1 works as a p-type barristor, where metal/GrT is connected with VDD and GrB is connected with output. On the other hand, VFET2 works as a n-type barristor, where GrB is connected with output and metal/GrT is grounded. A clear switching effect is observed (Fig. 5b, 14 ACS Paragon Plus Environment

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red line). The advantage of CMOS inverters made by this way is that the inverter function is kept stable even when an opposite direction of VDD is applied, i.e., VDD is connected to the GrT of VFET2 and GND is connected to the GrB of VFET1 (Fig. 5b, right schematics). In this case, the VFET1 functions as a n-type barristor and VFET2 functions as a p-type barristor. With this inverted configuration, this circuit geometry still follows the pull-up p-type barristor and pulldown n-type barristor architecture, resulting in essentially the same switching curve despite the change of power supply (Fig. 5b, blue line). It is also noted the gain of our inverter is smaller than unity, which is limited by the relatively small Vds (1.5 V, as limited by the reverse breakdown voltage of the Schottky barrier), and relatively large Vg due to the relatively thick back gate dielectric (60 nm SiNx). This inverter gain may be further improved by using thicker channel material (allow larger Vds) and thinner gate dielectrics (allow smaller Vg). Taking a step further, more complicated logic functions could be achieved by connecting more VFETs together. For example, a same architecture of 4 integrated VFETs can be readily configured as either a logic NAND and NOR gate depending the on bias configuration (Fig. 5c, left). First, the top VFET1 and VFET2 behave as p-type barristor by connecting drain to VDD and source to Vout; and the bottom VFET3 and VFET4 behave as n-type barristor by flipping sourcedrain electrode. In this way, NAND logic function can be observed from the input and output voltage (blue line, Fig. 5d). Significantly, this logic NAND gate can be easily reconfigured into a logic NOR gate by simply exchanging VDD with GND. Under this situation, the VFET1 and VFET2 will behave as n-type barristor and VFET3 and VFET4 will behave as p-type barristor (right panel, Fig. 5c), and the input/output curve clearly demonstrated a NOR logic function (Fig. 5d, blue line). These studies clearly demonstrates that NOR and NAND function could be both accomplished using same circuit, by simply adjusting the power supply direction.


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In summary, we have demonstrated a new design of vertical devices based on a metal/graphene-silicon-graphene sandwich structure. With GrB as an "active contact", GrT as physical/electronic buffer, and the low doping thin film silicon as the effective channel, we show that both the carrier concentration and carrier type in the sandwiched silicon can be readily modulated by gate potential penetrating through graphene. It can thus enable a new type of ambipolar diodes with switchable polarity and ambipolar barristors (transistors) with switchable carrier type, which could open up a new avenue to graphene based van der Waals heterostructures, as well as logic circuit design with reconfigurable functions. Method Electrical characterization. The D.C. electrical transport studies were conducted with a probe station at room temperature under ambient conditions with a computer-controlled analogue-todigital converter. Scanning photocurrent measurement is conducted using DL 1211 low-noise current preamplifier and a computer-controlled analogue-to-digital converter, with a SP2 MP Film confocal microscope coupled with Ar / ArKr laser (wavelength 514nm). Temperature dependent measurement is conducted using Physical Properties Measurement System (PPMS) from Quantum Design. Square wave is generated by Agilent 33220A function generator and filtered signal is captured by Agilent DSO3202A oscilloscope. ASSOCIATED CONTENT Supporting Information. Detailed experimental process and supplementary information is described. This material is available free of charge via the Internet athttp://pubs.acs.org. Corresponding Author *

E-mail: [email protected] 16 ACS Paragon Plus Environment

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Notes The authors declare no conflict of interest. ACKNOWLEDGEMENTS We acknowledge the Nanoelectronics Research Facility (NRF) at UCLA for technical support. X.D. acknowledges financial support by ONR through grant number N00014-15-1-2368. Y. H. acknowledges the financial support from National Science Foundation EFRI-1433541.

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