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Analog and Digital Bipolar Resistive Switching in SolutionCombustion-Processed NiO Memristor Ya Li,† Jinxing Chu,† Weijie Duan,† Guangshuo Cai,† Xihua Fan,† Xinzhong Wang,§ Gang Wang,†,‡ and Yanli Pei*,†,§

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†

State Key Laboratory of Optoelectronic Materials and Technologies, School of Electronics and Information Technology, Sun Yat-Sen University, Guangzhou, Guangdong 510275, China ‡ Foshan Research Institute of Sun Yat-Sen University, Foshan, Guangdong 528222, China § Department of Electronic Communication and Technology, Shenzhen Institute of Information Technology, Shenzhen, Guangdong 518172, China S Supporting Information *

ABSTRACT: In this study, a NiO-based resistive memristor was manufactured using a solution combustion method. In this device, both analog and digital bipolar resistive switching were observed. They are dependent on the stressed bias voltage. Prior to the electroforming, the analog bipolar resistive switching was realized through the change of the Schottky barrier at p-type NiO/Ag junction by the local migration of the oxygen ion in the interface. On the basis of the analog resistive switching, several synaptic functions were demonstrated, such as nonlinear transmission characteristics, spike-rate-dependent plasticity, longterm/short-term memory, and “learning-experience” behavior. In addition, once the electroforming operation was carried out using a high applied voltage, the resistive switching was changed from analog to digital. The formation and rupture of the oxygen vacancy filaments is dominant. This novel memristor with the multifunction of analog and digital resistive switching is expected to decrease the manufacturing complexity of the electrocircuits containing analog/digital memristors. KEYWORDS: NiO memristor, solution combustion process, analog and digital resistive switching, synaptic plasticity

1. INTRODUCTION Memristor is defined as the 2-terminal resistive switching nonvolatile memories. Memristor can be divided into both analog and digital types. The digital-type memristors with abrupt resistive switching have been widely studied as the nextgeneration nonvolatile memory owing to their simple structure, high integration, and low power consumption.1,2 Recently, the analog-type memristors with gradual resistive switching have drawn more attention for the applications in analog nonvolatile memory,3 programmable analog circuits,4 and so on. In particular, analog memristor shows promising features in exploiting artificial synapses for implementing brain-inspired neuromorphic computing. Generally, the formation and rupture of conductive filaments is considered as the resistive switching mechanism.5−7 Most of the filamentary memristors show abrupt set/reset switching, namely it is digital-type. In contrast, there are few reports on the analog-type devices.8 The analog resistive switching mechanism is still not clear. In © XXXX American Chemical Society

general, analog and digital behaviors are present in separate devices. In fact, to improve the circuit performance, analog neuromorphic computing system also needs a digital device as assistance. Liu et al. had reported an analog neuromorphic computing system with crossbar-based analog memristor and digital-assisted noise-eliminating training circuit.9 For a circuit with mixed analog/digital memristors, integrating the analog/ digital resistive switching in a single device could greatly reduce the manufacturing complexity. However, the memristor with a multifunction of the analog/digital resistive switching in a single memristor cell is rarely reported.10,11 The synaptic functions in the multifunction memristor are still a concern. Transition-metal oxides (ZnO, NiO, TiO, TaO, NbO, and others) are promising materials for resistive switching. They Received: April 10, 2018 Accepted: June 28, 2018

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DOI: 10.1021/acsami.8b05749 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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3. RESULTS AND DISCUSSION 3.1. Analog Bipolar Resistive Switching. Figure 2a is the current−voltage (I−V) curves of the NiO memristor under consecutive positive and negative bias sweepings, respectively. During the measurement, the Ag top electrode was stressed with the bias and the bottom electrode Pt was grounded. At the initial state, the device demonstrates asymmetry rectification characteristics. It can be attributed to the Schottky-like barrier formed at the interface of the p-NiO/ Ag junction. As we know, Ag is an n-type metal and NiO is a typical p-type semiconductor. In our previous work, the NiO thin film has been employed as a p-type channel of the thin film transistor.23 Furthermore, under positive bias sweep (0 V → 1 V → 0 V), the clockwise hysteresis was observed with the decreased current at the backward sweep (1 V → 0 V). Then, the current decreased gradually when the consecutive positive bias sweeps (0 V → 1 V → 0 V) were carried out. In contrast, under negative bias sweep (0 V → −1 V → 0 V), the hysteresis was with the increased current at the backward sweep (−1 V → 0 V). The current gradually increased with the repeated negative voltage sweep. To clearly illustrate such analog resistive switching property, the voltage and current data versus time were extracted in sequential voltage sweeps and summarized in Figure 2b. The gradual conductivity change was observed obviously, especially for the negative voltage sweep. In comparison, for the memristor with the NiO treated at low temperature, no analog resistive switching was observed. The result was showed in the Supporting Information. The analog resistive switching was operated by applying the voltage pulses, also. After each repeating pulse, the current was recorded using a read voltage of 0.1 V. The small read voltage can reduce the bias stress effects as small as possible. Figure 3a records the current in the process of applying 50 identical negative pulses (−0.7 V, 2 ms) and 50 identical positive pulses (0.7 V, 2 ms) sequentially. As expected, this memristor conductivity increases gradually with applying the negative pulses and then tends to saturate. In contrast, the positive pulses cause the decrease and saturation of the conductivity. The modulation of the memristor conductance can also be achieved by adjusting the stressed pulse amplitude or duration with a fixed interval time (2 ms). As illustrated in Figure 3b,c, higher pulse amplitude and longer pulse duration will cause larger conductance changes. These nonlinear transmission spike-timing-dependent characteristics are similar to the spiketiming-dependent plasticity of the biological synapses. In addition, when pulse amplitude and duration were fixed, the device conductance can also be changed by adjusting the pulse stimulation interval. Figure 4a,c records the current value in the memristor after each pulse stimulus. Here, the pulse interval was set up in various conditions (10, 20, 50, and 100 ms). The negative stimulation pulse increases the memristor conductivity (Figure 4a), whereas the positive stimulation pulse decreases the memristor conductivity (Figure 4c). Mean values of the induced conductivity change under various stimulation rates were summarized in Figure 4b,d. We found that the high stimulation rate induces more conductance changes. Such spike-rate-dependent characteristics are similar to that of biological synapses, which are ascribed to the spike interacting with the excitatory postsynaptic current (EPSC) in temporal regions.24 In biological systems, synapses are the communication nodes between presynaptic neurons and postsynaptic neurons.

are usually fabricated using vacuum methods such as sputter, atomic layer deposition, and so on.12−17 Lately, solution methods attracted much attention owing to the advantages of low cost, simple process, and compatibility with flexible electronics. Therefore, it is of great significance to study the preparation of transition-metal oxide memristor by a solution method, which may promote the emergence of a full solutionbased flexible artificial neural network. NiO-based ReRAM is one of the earliest studied.18−22 Unlike oxides such as ZnO and TiO, the NiO is a p-type semiconductor material. Using NiO as a resistive switching layer may present some novelty performance. In this study, we manufactured NiO-based memristor using a solution combustion method. Multiple features including rectification characteristics, analog bipolar resistive switching, and digital bipolar resistive switching were obtained simultaneously in a single memristor cell. The resistive switching mechanisms were discussed for digital and analog, respectively.

2. EXPERIMENTS 2.1. Synthesis of NiO Solution Precursor. Ni(NO3)2·6H2O was used as raw materials to prepare the solution precursors of the NiO. The solvent is 2-methoxyethanol. Acetylacetonate and NH3(aq) were added as fuel and pH regulator, respectively. The mixed solution was filtered by a 0.2 μm syringe filter after stirring in air for 20 h. Finally, the precursor solution was aged for an appropriate duration for spin-coating. The detail was described in ref 23. 2.2. Preparation of NiO Memristor. Ti (50 nm)/Pt (20 nm) stack bottom electrode was fabricated using electron beam evaporation upon SiO2/Si substrate. After an oxygen plasma treatment of the Pt/Ti/SiO2/Si substrate, the nickel-containing precursor solution was spin-coated. Then, the NiO wet film was heated at 300 °C in air for 30 min. Before next spin-coating, oxygen plasma treatment was performed to improve the surface hydrophilicity. An appropriate thickness of the NiO film was achieved after repeating the spin-coating process for five times. Then, postannealing was performed in a furnace at 350 °C in air for 30 min to enhance the NiO film compactness. The NiO thin-film thickness is 50 nm, measured using an F20-UV thin-film measurement system. The NiO thin film shows good p-type semiconductor properties.23 The physical and chemical properties of the NiO thin film have been characterized in our previous work.23 For comparison, NiO treated at low temperature was fabricated, simultaneously. The NiO was heated at 250 °C and then postannealed at 250−300 °C. As reported in our previous work,23 the NiO treated at low temperature shows poor ptype semiconductor properties. Finally, Ag was deposited on the top of the NiO film as top electrodes using electron beam evaporation. The schematic structure of the NiO memristor is shown in Figure 1. An Agilent B1500A semiconductor parameter analyzer was employed to measure the electrical properties of the memristors.

Figure 1. Schematic structure of the NiO-based memristor. B


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Figure 2. (a) Consecutive five positive voltage sweeps [here 1, 2, 3, 4, and 5 are the current−voltage (I−V) curves of the NiO memristor under consecutive five positive voltage sweeps (0 V → 1 V → 0 V)] and consecutive five negative voltage sweeps [6, 7, 8, 9, and 10 are the current− voltage (I−V) curves of the NiO memristor under consecutive five negative voltage sweeps (0 V → −1 V → 0 V)] decrease and increase the memristor conductance continuously, respectively, and (b) current and voltage data vs time for the device.

Figure 3. (a) Current change at a reading voltage of 0.1 V after repeating pulses of −0.7 V for potentiation and 0.7 V for depression, (b) current through the memristor recorded after each negative stimulation pulse, at different pulse amplitude and duration, and (c) current through the memristor recorded after each positive stimulation pulse, at different pulse amplitude and duration.

The change of the synaptic connection strength (i.e., their weight) is the biological basis of the brain’s learning and memory storage.25 In psychological studies, human memory loss was usually described as a rapid initial decline [corresponding to the short-term memory (STM)] followed by a subsequent long, slow decay process [corresponding to the long-term memory (LTM)].26 What is more, STM can be transformed into LTM by repeated stimulus on a biological system.27 In this work, the conductivity of the NiO memristor can be modulated gradually by duration, amplitude, and stimulation rate of the applied voltage pulse. It is analogous to the potentiation (or depression) of the synaptic connections in neuromorphic systems. Therefore, the synaptic learning behavior was simulated by the NiO memristor with analog resistive switching. At first, a series of consecutive negative pulses (interval of 2 ms, height of −1 V, and duration of 2 ms) were employed to stimulate the NiO memristor as a learning process. After removing the pulse, the retention loss curve was recorded for 1000 s as a forgetting process. The conductivity

was read out by a small voltage of 0.1 V. The synaptic weight was defined as the conductivity change with respect to the initial state. The conductivity change value was normalized by the value after the first stimulation of 50 identical negative voltage pulses. Four cycles of the learning/forgetting process were carried out. The results are shown in Figure 5. For the first cycle, the synaptic weight increases gradually with the increase of the stimulus pulse’s number. When the applied pulse is removed and there is no external input, the synaptic weight decays spontaneously. In the initial state, the decay rate is fast, and then slows down gradually. It is interesting to note that the synaptic weight cannot return to the original state even for a long relaxation time but stabilizes at 64.8%. The result shows that the weight change of the synaptic can be divided into two parts: STM and LTM. Furthermore, when restimulus pulses were stressed to recover the device from the relaxed state, the number of stimulation pulses was reduced gradually depending on the history of learning. Compared to the 50 pulses in the first-learning process, 18, 12, and 8 pulses were C


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Figure 4. Current through the memristor recorded after each stimulation pulse (±1 V/2 ms) with various pulse interval conditions (interval of 10, 20, 50, and 100 ms), and mean values of induced conductance changes for stimulation pulse under different stimulation interval between pulses. (a,b) For negative stimulation pulse (−1 V/2 ms) and (c,d) for positive stimulation pulse (1 V/2 ms).

Figure 5. (a) First learning process, (b) first forgetting process, (c) second learning process, (d) second forgetting process, (e) third learning process, (f) third forgetting process, (g) fourth learning process, and (h) fourth forgetting process in the memristor, respectively.

required to recover the device memory for the second, third, and fourth learning process, respectively. The result demonstrates that relearning of the forgotten information is easier. In addition, as presented in Figure 5b,d,f,h, when the stressed pulse was removed, for the same relaxation time, the synaptic weights were stabilized at 64.8, 72.9, 73.4, and 77.1%, for the first, second, third, and fourth forgetting processes, respectively. These characteristics are similar to the transformation of STM to LTM through repeated stimulation in biological systems. Above interesting phenomenon indicates that this device has “learning and forgetting experiences” behavior of human beings. To evaluate the “forgetting process” clearly, the “forgetting” curves after various learning processes with different numbers of the stimulation pulse (30, 50, 70, 90, 110, and 130) were investigated and shown in Figure 6a. Here, the pulse amplitude, duration, and stimulation interval were set as −1 V, 2 ms, and 10 ms, respectively. The forgetting curves were fitted using eq 1.24 M(t ) = M + (M 0 − M )exp(−t / τ)

Figure 6. (a) Change curves of STM and LTM under the same pulses with different number; here, the number of stimuli pulse are 30, 50, 70, 90, 110, and 130, respectively. The pulses amplitude, duration, and stimulation interval were set as −1 V/2 ms/10 ms. (b) Relaxation time (τ) and the memory retention (M) obtained through the fitting in (a) as a function of the number of stimuli pulse (N).

(1)

M(t), M0, and M are the memory level at time t, t = 0, and at steady-state after a long time, and τ is the relaxation time constant. The relaxation time constant of τ was extracted to assess the forgetting rate. The relaxation time constant (τ) and memory retention at 2000 s as a function of the pulses number D


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Figure 7. (a) Double logarithmic plots of I−V for the first positive voltage scan in Ag/NiO/Pt memristor, (b) ln(I) ∝ sq(V) plots together with the linear fitting in negative and positive bias range, and (c)Schottky barrier (ϕB) changes with consecutive voltage scan.

between the top and bottom electrodes, ϕB is Schottky barrier, εi is the material dielectric constant. In this work, we used the Richardson constant of A* = 119.8 A/K2·cm2 calculated with mn* = 1.0 m0 = 9.1 × 10−31 kg.34 We get formula 3 by taking the natural logarithm of the formula 2 as below

were shown in Figure 6b. When the number of the stimulation pulses increases from 30 to 90, the relaxation time (τ) increases from 222.8 to 354.5 s. It indicates that the forgetting rate decreases gradually. Beyond 90 stimulation pulses, the relaxation time (τ) tends to saturate. Meanwhile, the memory retention increases from 60.4 to 70.76% gradually as the number of stimulation pulse (N) increases from 30 to 130. These results simulate the transition process from STM to LTM by repeated stimulation pulse again. This has a great resemblance to the biological memory function. 3.2. Analog Resistive-Switching Mechanisms. The first positive voltage I−V scan was plotted in double logarithmic coordinate and fitted by a linear relation. As shown in Figure 7a, under a low electrical field (0 V < V < 0.3 V), the slope of the linear fitting curve is 1. It indicates that Ohmic conduction is dominant at the low electrical field. Under high electrical field, the I−V curve deviates from the linear relation, and another conduction mechanism should be discussed. There are four main conductive mechanisms, including Schottky emission [ln(I) ∝ sq(V)],28 space charge-limited conduction (I ∝ V2),29 Fowler−Nordheim tunneling [ln(I/V2) ∝ V−1],30 and Poole−Frenkel (P−F) emission [ln(I/V) ∝ sq(V)].31 Through current fitting, it was conformed that the current conduction deviates from the mechanisms of the space-chargelimited conduction, the F−N tunneling, and the P−F emission. In this work, the current is low in both the direction of positive and negative bias with asymmetric rectifier characteristics. Because the top electrode (Ag) is an n-type metal, a Schottkylike barrier may exist in the interface of Ag/p-NiO junction. In addition, the p-type NiO fabricated with the solution method shows low charge-carrier mobility and low charge-carrier density. Therefore, the modified Richardson−Schottky equation can be used to describe the I−V characteristics32,33 I = AA*T 2 e(−q(ϕB −

qE /4πεi / kT )

q yz q i ln I = jjjln(AA*T 2) − ϕBzz + q/4πεid V kT kT k {

(3)

Figure 7b shows the ln(I) ∝ sq(V) plots with linear fitting in positive and negative bias directions. The good linear relationship implies that the current flow was governed by the Schottky emission. Furthermore, the Schottky barrier (ϕB) can be extracted from the intercept at the ln(I) axis, according to the eq 4 q Intercept (ln(I ), 0) = ln(AA*T 2) − ϕ (4) kT B We extracted the Schottky barriers from the consecutive I− V sweepings under positive and negative bias, respectively. This result is shown in Figure 7c. The Schottky barrier value basically coincides with the energy-band alignment (Supporting Information). It notes that the Schottky barrier is reversed under the positive bias range. We found that the Schottky barrier (ϕB) increases gradually under the consecutive positive voltage scan and decreases gradually for the consecutive negative voltage scan. Considering the low current density with gradually changing, based on the above analysis, we suggest that the mechanism of the analog resistive switching is interface leading rather than conductive-filament related. It was discussed as follows. When a positive bias (or positive pulse) is added to the top electrode (Ag), the Schottky barrier between Ag and p-NiO will be reversed to form a depletion layer in NiO side. In addition, the oxygen ions migrate toward the top electrode under a positive electrical field. The oxygen ions are attracted by a positive bias through the depletion layer. The result is that the oxygen vacancies remain in the depletion layer. The oxygen vacancies as donors will deplete the p-type NiO further. Namely, the

(2)

where A = π(50 μm) is the conduction area, A* = 4πqm*n k02/ h3 is the effective Richardson constant, T is the absolute temperature, k is the Boltzmann constant, q is the electric charge, E is electric field, V = E × d, d = 50 nm is the spacing 2

E


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Figure 8. (a) Typical bipolar resistive switching I−V curves of Ag/NiO/Pt memristor with compliance current of 1 mA, (b) Vset and Vreset distributions for memristor, and (c) endurance performance of the memristor. (d) Retention characteristics of LRS and HRS for NiO memristor and (e) distributions of the electroforming voltage for the devices with or without analog switching history.

It was called “forgetting” process. In this process, the oxygenion migration is fast at first because of the concentration gradient and then tends to saturate. Meanwhile, the diffusion of oxygen ions in the NiO bulk leads to a much lower probability of restoring the initial state. It can be used to explain the transition from STM to LTM. On the other hand, for the NiO treated at low temperature with poor p-type semiconductor properties, the Schottky barrier may be difficult to change because of the Fermi-level pinning. Therefore, the analog resistive switching has not been found. Further investigation is necessary to understand the analog resistive switching behavior. 3.3. Digital Bipolar Resistive Switching. Analog resistive switching is observed for the applied bias voltage less than 1 V. In contrast, when a higher bias voltage is stressed on the NiO memristor, an abrupt resistive switching is demonstrated. This operation is called “electrical forming” in general resistive memory. Through the electroforming process, the device transformed from analog- to digital-type. Figure 8a presents the typical I−V curves of the electroforming, set/reset cycles of this Ag/NiO/Pt structure memristor. The bipolar resistive switching was observed. Here, the forming voltage is 1.25 V and the compliance current is 1 mA. The memory window about 102 was well-kept even after 100 cycles sweeping, indicating good reproduction. Figure 8b shows the distributions of the set voltage (Vset) and the reset voltage (Vreset) for Ag/NiO/Pt memristor devices. We defined Vset as the voltage point when the current jumps to the low-resistive state (LRS),

depletion width at the Ag/p-NiO interface should be widened, resulting in the variation in the Schottky barrier width. In contrast, when the negative bias (or negative pulse) is stressed on the top electrode, the oxygen ions migrate back to the NiO bulk near the interface, which recombine with oxygen vacancies or induce Ni vacancies, resulting in the decrease in the Schottky barrier width. For the positive voltage pulse, longer duration and higher amplitude of the positive voltage pulse make more oxygen ion migrate toward the top electrode accompanied by the depletion layer broadening. In contrast, for the negative voltage pulse, the longer duration and higher amplitude make the oxygen ions return to the NiO more. As a result, the conductivity of the memristor is changed more significantly. The spike-rate-dependent characteristics can be explained that after removing the pulse, the oxygen ions can still move forward a short distance under the inertial effect. It is called EPSC. For the high spike-rate case, the EPSC effect does not disappear completely even when the next pulse arrives. EPSC and pulse will superimpose, thus accelerating ion migration. Therefore, the change of the conductivity is greater. For the “learning” process under the negative pulse stimulation, the oxygen ions will be assembled in the NiO thin film near the interface between NiO and Ag electrode. It will combine with the oxygen vacancy or induce Ni vacancy. As a result, the Schottky barrier width was narrowed with the increasing of the conductance. After removing the stimuli pulse, the oxygen ion near the interface will migrate back to the electrode side, resulting in the decreasing of the conductance. F


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Figure 9. (a) log(I) vs log(V) plots of I−V, (b) ln(I) vs V1/2 plots of I−V in the voltage region (0.3 V < V < 0.9 V), (c) ln(I) vs V plots of I−V in the high voltage region (0.9 V < V < 1.25 V) for Ag/NiO/Pt memristor, and (d) temperature dependence of LRS resistance of Ag/NiO/Pt structure memristor.

and Vreset as the voltage point where the current jumps down to high-resistive state (HRS). As shown in Figure 8b, the Vset and Vreset for 63% devices are less than 0.39 and 0.40 V, respectively. Unfortunately, the Vset and Vreset show a wide distribution. The uniformity of the NiO thin film is required to optimize in the future. Figure 8c shows the endurance characteristics. LRS and HRS are read with 0.1 V. The HRS/LRS ratio is close to 102. Importantly, the value keeps stable even after 100 cycles set/reset operation. Figure 8d presents the retention characteristics at room temperature. After the retention of 104 s, no obvious degradation was found. The retention time is longer than 104 s at room temperature. To investigate the effect of analog resistive switching history on digital resistive switching, the electroforming voltages with or without the analog resistive switching history were measured for comparison. The test result was analyzed in Figure 8e. No serious difference was observed for both. 3.4. Digital Resistive Switching Mechanisms. To determine the conduction mechanisms of the Ag/NiO/Pt memristor, the I−V curve in HRS and LRS was plotted in double logarithmic coordinate and fitted by a linear relation. As shown in Figure 9a, the slopes of the fitted line are near 1 in the low-voltage region (0 V < V < 0.3 V), indicating the Ohmic conduction behavior (I ∝ V). Then, the I−V curve of HRS deviates from the Ohmic law under higher voltage. As presented in Figure 9b, in the voltage region (0.3 V < V < 0.9 V), the plot of ln(I) versus V1/2 for HRS is linear and matches well the Schottky emission mode. In the HRS under high voltage region (0.9 V < V < 1.25 V), as shown in Figure 9c, the plot of ln(I) versus V is linear and is in accordance with the hopping conduction mode. The conduction behaviors in HRS and LRS states imply that the current in on-state is likely to be confined in a local region, rather than uniform distribution. Ohmic conduction is a bulk-dominated mechanism. The conductive filament model can be considered to explain the digital-type resistive switching. Hopping current suggests that, in the electroforming process, the bulk traps are

the major element for the formation of the conductive filaments. The electrode-size-independent LRS current also demonstrates the filament conductive model from another aspect (data not shown). The temperature characteristics of the LRS resistance were investigated. The result is shown in Figure 9d. The LRS resistance increases along with the temperature, indicating a metallic-like conducting behavior. The following equation can describe the temperature dependence of the metallic resistance R(T ) = R 0[1 + α(T − T0)]

(5)

Here, R0 is the resistance at a temperature of T0 and α is the temperature coefficient of resistance. As shown in Figure 9d, the LRS resistance was linear fitted by eq 5. The resistance temperature coefficient was obtained to be 6.7 × 10−4 K−1. The value is close to that of 5.8 × 10−4 K−1 for an oxygen vacancy filament in indium gallium zinc oxide, as reported in the literature,35,36 and 5.6 × 10−4 K−1 for the oxygen vacancy filament in NiFe2O4, as reported in the literature.37 The result suggests that the conductive filaments in the memristor are mainly composed of oxygen vacancy. In the electroforming process, the oxygen ions in Ni−O bonds can migrate to the positive electrode (Ag top electrode) under high electric fields. The oxygen vacancies (Vo2+) were left behind in the NiO. It has been reported that the formation energies of oxygen vacancies are less than that of Ni vacancies.38 Oxygen vacancies tend to cluster in certain configurations to generate the conducting path.38 In the reset process, oxygen ions will migrate back toward the bottom electrode (Pt) under the negative electric field and lead to the annihilation of oxygen vacancies. The formation/rupture of the oxygen vacancy conductive filaments was suggested to explain the resistive switching process. Because the analog resistive switching is dominated by the interface properties, the influence of the analog resistive switching history on digital resistive switching is limited. For digital resistive switching, the bulk is the main role. Furthermore, because the oxygen vacancy is easy to form G


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ACS Applied Materials & Interfaces in the NiO bulk,38 the digital resistive switching was observed in the memristor with the NiO treated at low temperature; even the analog resistive switching was not found (Supporting Information).

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4. CONCLUSIONS In summary, we fabricated the NiO-based memristor by solution combustion method with a simple process and low cost. Multiple features including analog bipolar resistive switching and digital bipolar resistive switching were obtained simultaneously in this NiO-based memristor. Prior to the electroforming, the device presents an analog resistive switching. On the basis of the analog resistive switching, several synaptic functions such as nonlinear transmission characteristics, spike-rate-dependent plasticity, LTM/STM, and “learning-experience” behavior were demonstrated. Schottky barrier change at the interface of Ag/p-NiO was used to explain the analog resistive switching mechanism, which is caused by local migration of oxygen ion under an electric field. After the electrical-forming operation, the digital bipolar resistive switching was observed. It can be explained based on the formation and rupture of the oxygen vacancies conducting path. This NiO memristor integrated with analog/ digital resistive switching in a single cell will provide a new device to development analog and digital memory hybrid system.

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ASSOCIATED CONTENT

* Supporting Information S

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.8b05749. Resistive switching characteristics of the memristor with the NiO annealed at low temperatures (250 and 300 °C) and energy band alignment of Ag/p-NiO junction (PDF)

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AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. ORCID

Yanli Pei: 0000-0003-3456-0746 Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS This work was supported in part by the National Natural Science Foundation of China (grant nos. 61774172, 51402366, and 61404177), the Science and Technology Planning Projects of Guangdong Province, China (grant nos. 2016B090918106 and 2015B010132006), the Science and Technology Planning Project of Guangzhou, China (grant no. 201607020036), the Natural Science Foundation of Guangdong Province, China (grant no. 20177612042030007), and the Basic Research Plan Program of Shenzhen City, China (grant no. JCYJ20160509100737182).

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REFERENCES

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