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Analog Synaptic Behavior of a Silicon Nitride Memristor Sungjun Kim, Hyungjin Kim, Sungmin Hwang, Min-Hwi Kim, Yao-Feng Chang, and Byung-Gook Park ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.7b11191 • Publication Date (Web): 31 Oct 2017 Downloaded from http://pubs.acs.org on October 31, 2017

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ACS Applied Materials & Interfaces

Analog Synaptic Behavior of a Silicon Nitride Memristor Sungjun Kim, *,† Hyungjin Kim, † Sungmin Hwang, † Min-Hwi Kim, † Yao-Feng Chang,‡, and Byung-Gook Park*,† †

Inter-university Semiconductor Research Center (ISRC) and the Department of Electrical and Computer

Engineering, Seoul National University, Seoul 08826, South Korea ‡

Microelectronics Research Center, Department of Electrical and Computer Engineering, University of

Texas at Austin, Austin, Texas 78758, USA

*E-mail: [email protected] *E-mail: [email protected]

ABSTRACT In this paper, we present synapse function using analog resistive switching behaviors in a SiNx-based memristor with complementary metal-oxide-semiconductor (CMOS) compatibility and expandability to 3D crossbar array architecture. A progressive conductance change is attainable as a result of the gradual growth and dissolution of the conducting path, and the series resistance of the AlOx layer in the Ni/SiNx/AlOy/TiN memristor device enhances analog switching performance by reducing current overshoot. A continuous and smooth gradual reset switching transition can be observed with a compliance current limit (> 100 µA), and is highly suitable for demonstrating synaptic characteristics. Long-term

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potentiation (LTP) and long-term depression (LTD) are obtained by means of identical pulse responses. Moreover, symmetric and linear synaptic behaviors are significantly improved by optimizing pulse response conditions, which is verified by a neural network simulation. Finally, we display the spiketiming-dependent plasticity (STDP) with the multi-pulse scheme. This work provides a possible way to mimic biological synapse function for energy efficient neuromorphic systems, by using a conventional passive SiNx layer as an active dielectric.

Keywords: Memristor, Analog resistive switching, Silicon nitride, Synapse, Spike-timing-dependent plasticity

INTRODUCTION The quantity of data used in computer systems will increase drastically in the near future, rendering existing data processing systems inadequate to cope. Thus, energy-efficient systems have become increasingly important.1 Classical computing architecture based on the von Neumman model exhibits fundamental limitations, due to the fact that the so-called von Neumman bottleneck cannot process data simultaneously. To overcome this issue, various approaches such as stateful logic circuits and neuromorphic computing are being developed by using memristor.2,3 Brain-inspired computing is believed to be more suitable for real-world environments, such as voice and image recognition, which requires complex and parallel processing, due to its energy-efficient and fault-tolerant computation compared to the von Neumman architecture. The synaptic electronic device is the most important component of a neuromorphic system, as synapses act as connecting bridges between neuron circuits; therefore, the connection strength between neurons can be modulated by synaptic weight. Above all, highly integrated low-energy synaptic devices are essential to realize more efficient neuromorphic computing.


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Among the various synaptic devices, such as phase change,4 ferroelectric,5 and field effect transistor (FET)-based6–8 devices that have been proposed, memristor-based synapses have received particular attention, due to their low energy consumption per synaptic event, high scalability, the ability to realize three-dimensional (3D) crossbar array architecture, and bi-directional multilevel capability.9–22 A twoterminal memristor device can mimic biological synaptic functions by modulating the conductance. Although a variety of memristor materials, such as HfOx, TaOx, MoOx, La1−xSrxMnO3, InGaZnO, and conducting polymer have been used for synaptic devices, only a small number of memristor devices use industry-friendly materials for both electrodes and switching materials.9–22 SiOx and SiNx, which are generally used for passive applications such as the gate dielectric and passivation layer in the BEOL process, can be used for synapse devices. These materials, which are deposited by the CVD process, show excellent wafer-scale uniformity and have effective compatibility with 3D vertical array structure in conventional CMOS technology. In our previous studies, various resistive-switching characteristics, including gradual switching and the structure and scaling effect in SiOx and SiNx-based memristor devices, were achieved.23–31 Moreover, the intrinsic nonlinear characteristics of SiNx-based memristor without selector elements is another advantage over other materials, as it helps in suppressing the sneak current paths in cross-point array.29 Here, we propose a Ni/SiNx/AlOy/TiN synaptic memristor, which possesses the above mentioned advantages. Certain biological synaptic characteristics such as LTP and LTD, which are achieved through repetitive pulse responses, are demonstrated by using a conventional passive SiNx layer as the active dielectric. The linearity and symmetry of synaptic weight are improved by pulse condition optimization. Furthermore, STDP as one of the a Hebbian synaptic learning rules can be implemented using a systematic multi-pulse scheme.

EXPERIMENTAL PROCEDURE


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The Ni/SiNx/AlOy/TiN synaptic memristors were constructed as follows. The 100 nm thick TiN bottom electrode (BE) was deposited by a physical vapor deposition system on a SiO2/Si substrate. Then, a 1.5 nm thick AlOy layer was deposited by an atomic layer deposition (ALD) using trimethylaluminum (TMA) and O3 and a 10 nm thick SiNx layer underwent plasma-enhanced chemical vapor deposition (PECVD) by reacting 5% SiH4/N2 (800 sccm), NH3 (10 sccm), and N2 (1200 sccm) at 280°C. Finally, the 100 nm thick Ni top electrode (TE) with a diameter of 100 µm was deposited on the SiNx layer by a thermal evaporator. All electrical properties were characterized by means of a DC voltage sweep and pulse modes, using a Keithley 4200-SCS semiconductor parameter analyzer (SPA) and 4225-PMU ultrafast current-voltage (I-V) module at room temperature, respectively. To enable device operation, the TiN BE was grounded, and the Ni TE bias was controlled. To analyze the composition ratio of the SiNx and AlOy materials deposited in our laboratory by different methods, X-ray photoelectron spectroscopy (XPS) analysis was performed using a Thermo VG ESCA Sigma Probe spectrometer operated at 15 kV and 100 W with a monochromatic Al-Ka radiation source. The calibration of the binding-energy scale was set by fixing the C 1s at 284.5 eV.

RESULTS AND DISCUSSION Figure 1a provides a schematic of the Ni/SiNx/AlOy/TiN device on the on SiO2/Si substrate. The thickness of two amorphous SiNx and AlOy layers was confirmed by means of a transmission electron microscopy (TEM) cross-sectional image, as shown in Figure 1b. Polycrystalline Ni TE and TiN BE were also observed by TEM. Figure 1c and 1d shows XPS of the Si 2p spectra and N 1s spectra for SiNx film, respectively. Si 2p spectra exhibits two peaks centered at 99.5 eV and 101.02 eV corresponding to Si–Si and Si–N bonding, respectively.32 N 1s spectra exhibits two peaks located at 397.35 eV and 398.32 eV, which is assigned to Si–N bonding.32 Atomic ratio N/Si of SiNx was 0.88. Figure 1e and 1f show XPS of the Al 2p spectra and O 1s spectra for AlOy film, respectively. Al 2p peak was located at 73.55 eV and O


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1s peaks centered at 530.63 eV and 532.03 eV.33 The calculated O/Al ratio of AlOy is 1.49, which nearly correspond to a stoichiometric amorphous Al2O3. Note that the SiNx and AlOy films in our device are applicable in 3D vertical structures, due to CVD deposition. We propose two 3D vertical array structures with CMOS compatibility for practical applications (Figure S1, Supporting Information). We investigate the optimized switching condition for resistive switching. Figure 2a shows the forming and on-state current-voltage (I-V) curves for Ni/SiNx/TiN and Ni/SiNx/AlOy/TiN devices. It is important to reduce the overshoot current to achieve reliable memristor device operation. The negative forming leads to high on-current when even the lowest possible compliance current limit (CCL) of 10 µA is applied to the devices, regardless of the insertion of an AlOy layer. Figure 2b shows the energy band diagram of the Ni/SiNx/TiN device in a flat band condition considering the material parameters. The electron injection from Ni TE, which has a higher work function (ΦNi: 5.1 eV)34 than TiN BE (ΦTiN: 4.3 eV),35 may be vulnerable to overshooting, since the higher electric field is initially induced by band bending within the SiNx layer. Figure 2c shows the overshoot rate depending on the forming polarity of Ni/SiNx/TiN and Ni/SiNx/AlOy/TiN devices. Here, the overshoot event occurs and then no reset switching occurs when the on-state resistance after forming is less than 200 Ω. The positive forming in the Ni/SiNx/AlOy/TiN device leads to a low on-current, suggesting that a narrow conducting path without current overshoot could be formed within the SiNx layer. The AlOy layer in the Ni/SiNx/AlOy/TiN structure, which acts as a tunnel barrier, plays an important role in reducing current overshoot during forming and set switching.36–38 However, if a barrier layer is too thick (> 3 nm), the increased switching voltage causes a hard breakdown within the barrier layer and the current overshoot is inevitable.37,38 For neuromorphic applications, gradual set and reset switching is essential. The previously reported SiNx-based memristor is rarely found to achieve both gradual set and reset at the same time.28 We examined the gradual transition regime depending on the CCL. Figure 3a shows the linear-scale I-V sweeping of the Ni/SiNx/AlOy/TiN memristor device, in which the switching loop shows bipolar resistive switching.39–45 The intrinsic resistive switching of SiN-based memristors is known to be related to the


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amount of silicon dangling bonds. The hydrogen contained in the SiNx film controls the amount of dangling bonds in accordance with the applied voltage or the initial SiNx deposition conditions.46 The SiNx film deposited by PECVD in this work is known to contain 20%–30% hydrogen in general.47 We confirmed the conduction mechanism for Ni/SiNx/AlOy/TiN memristor device through temperature dependence and I-V fitting (Figure S2, Supporting Information). With regard to the semiconducting properties based on temperature dependence, it can be concluded that the penetration of TE Ni and oxygen vacancies in AlOy are not the main conduction paths, but the intrinsic switching of SiNx film is. Moreover, the on- and off-current states within the gradual transition regime are well fitted with the tunneling mechanism and Poole-Frenkel emission, respectively, which is consistent with the previous reports on the conduction mechanisms of SiNx memristor.46 Firstly, the positive forming process with a CCL of 1 mA is required to activate the device, as shown in the inset of Figure 3a. Subsequently, during the negative voltage sweep (0 ~ −5 V), the current gradually decreases, while gradually increasing again during the positive voltage sweep (0 ~ 5 V). If CCL of more than 1 mA is applied to the device, the on-current is too high to operate reliable resistive switching due to negative-set switching (Figure S3 in the Supporting Information). Figure 3b shows the IV characteristics according to different CCLs (10 µA, 100 µA, and 1 mA). It is difficult to set the transition to obtain the multilevel using a voltage-controlled method, owing to a narrow transition voltage region. The on-resistance decreases linearly with an increasing CCL from 10 µA to 1 mA, suggesting that the conducting path size can be effectively controlled by CCL, as shown in the inset of Figure 3b.48 The variation of on-resistance distribution also decreases with increasing CCL from 10 µA to 1 mA, which is essentially in agreement with the filamentary and electrical faucet theory.49 The current flows through a strong conducting path for the on-state. Meanwhile, the conducting path will achieve the semiconducting property with decreasing CCL, and then the on-state could be easily affected by a previous switching event. It should be noted that continuous and smooth reset transition is clearly observed when CCLs of 100 µA and 1 mA are applied to the devices. Conversely, abrupt step-like reset transition is observed for a


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CCL of 10 µA. The varying reset transitions may be related to the conducting path size. A small conducting path size controlled by a low CCL, without current overshoot, can be considered as a single conducting channel, like a quantum wire.50,51 A small movement of conducting defects in a single conducting path may lead to a large resistance change. Figure 3c displays the resistance value as a function of reset stop voltage (VSTOP) when CCL of 1 mA is applied to the device during the forming process, where the resistance value is finely adjusted by the VSTOP from −3.5 V to −8 V, and a continuous and smooth reset process is observed only up to −7.4 V. Here, a change in resistance by a factor of more than 1000 is observed, which is an improvement compared to our previous report.28 This could be attributed to the thicker SiNx film, which may increase the range of the off-current level. It is noted that an abrupt and step-like reset transition is observed for a larger VSTOP. An abrupt resistance change is not suitable for neuromorphic applications, because multi-level intermediate conductance values with effective uniformity cannot be obtained by abrupt conductance change. Therefore, we conducted synaptic performance at CCL (> 100 µA) for the Ni/SiNx/AlOy/TiN memristor device. We also confirmed gradual transient characteristics for set and reset switching when repetitive pulses are applied (Figure S4, Supporting Information). We expect that the switching current is reduced in a smaller size cell of the intrinsic SiNx-based memristor, due to the confinement of the conducting path.30 Gradual switching in a scaled SiNx-based cell may be suitable for neuromorphic applications. Nevertheless, at the current levels below 10 µA, abrupt reset switching can be the predominant reset mechanism due to the quantum effects of the conducting path.30,50,51 The switching tendency, considering the scaling effects, will require additional study. In order to mimic the biological synapse behaviors of the Ni/SiNx/AlOy/TiN memristor, the LTP and LTD are demonstrated. Figure 4a and 4b indicate the gradual conductance modulation when different pulse conditions are applied. In this case, all conductance values were extracted by a read voltage of −0.2 V, in order to minimize read disturbance and ensure long-term memory application. Figure 4a shows the gradual potentiation and depression with identical pulse responses, which does not ensure symmetric


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behavior. For potentiation, identical pulses with amplitudes of 5 V, 5.5 V, 6 V, and 6.5 V and pulse widths of 100 ns and 200 ns were used. When a pulse of 100 ns is applied, the conductance change converges even if the pulse amplitude is greater than 5.5 V. On the other hand, when a pulse of 200 ns is applied, the width of the conductance change increases significantly, but at too high a voltage (6 V) there is a risk of breakdown. The depression was used by the identical pulse with amplitude from −3.5 V to −5.5 V and width of 100 ns. As the absolute value of the voltage increases, the conductance change is more nonlinear. The change rate slows remarkably with an increasing number of pulses for depression. The gradual potentiation and depression according to the pulse response with incremental pulse width are also investigated (Figure S5 in the Supporting Information). The pulse width was varied from 200 ns to 1100 ns at fixed amplitude of 5.3 V for potentiation, and from 100 ns to 1900 ns at fixed amplitude of −3.5 V for depression. The potentiation and depression characteristics are similar in the identical and incremental pulse widths, which suggests that the pulses with extended width cannot further modulate an effective conductance value at a certain threshold. However, the conductance value can be tuned more easily by increasing the pulse amplitude, as shown in Figure 4b. The pulse response with incremental amplitude can effectively change the conductance values, and near-linear and symmetric characteristics can be obtained by increasing the pulse amplitude from 5 V to 6.15 V with 0.05 V/step and width of 200 ns and from −3.1 V to −5 V with −0.05 V/step and width of 100 ns, for potentiation and depression, respectively. There are two different regimes of operation in artificial neural networks. The neural network is trained and then is ready for the inference. We believe that the energy related to inference is much more important because inference is used much more frequently than training. The energy for an inference can be calculated by taking the product of the pulse amplitude, width, and current. The energy of the intermediate state is about 2.34 pJ (0.2 V × 500 ns × 23.43 µA, Figure S6, Supporting Information). Here, time duration of 500 ns at 0.2 V is sufficient to read the current for the inference. On the other hand, the pulse of 200 ns at 5 V is enough to cause changes in conductance for training, as shown in Figure 4b.


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Compared to the energy consumption of a biological synapse (~ 1 fJ), the energy consumption of our memristor devices require further improvement. A proper electric field concentration structure and reduction in device size can reduce the power and increase the operation speed. We furthermore investigate STDP, which forms another important rule of learning and memory law in a biological neural system. Synaptic weight can be modulated by timing differences between preand post-synaptic spikes. The spike shape, which consists of consecutive pulse trains with different amplitudes (3, −3, −2.5, −2, −1.5, and −0.5 V), is systematically designed as illustrated in Figure 4c. Individual positive and negative pulses cannot affect the conductance value, while an overlapped spiking pulse leads to conductance change. When a pre-spike precedes a post-spike (∆t > 0), the synapse weight increases (potentiation); conversely, when a post-spike precedes a pre-spike (∆t < 0), the synapse weight decreases (depression). Figure 4d shows the STDP characteristics, indicating the conductance change of the Ni/SiNx/AlOy/TiN memristor as a function of the interval between the pre- and post-spike. The conductance change increases according to a decreasing timing difference. The pulse train responses results in large conductance resistance when the shortest spike timing is applied to the memristor device for potentiation and depression, respectively. It was confirmed that only an overlapped spiking pulse can lead to an effective conductance pulse (Figure S7 in the Supporting Information). After fitting the conductance modulation characteristics in Figure 4a and b, 784 × 10 single-layer neural network simulation is conducted using binary modified national institute of standards and technology (MNIST) handwritten dataset in order to compare the effect of nonlinearity and linearity of conductance modulation in neuromorphic system. The two synaptic devices are grouped as one synapse unit to represent both positive and negative synaptic weight value (W = G+ − G−).8,52 During learning process, the conductance of excitatory synaptic devices is updated depending on the error term calculated by supervised learning and gradient descent method of software-based artificial neural network using rectified linear unit (ReLU) as activation function, while the conductance of inhibitory synaptic devices is fixed. Figure 5a shows the classification accuracy as a function of the number of trained samples. When


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the conductance of synaptic devices is near-linearly modulated, the classification rate for 10000 untrained test sample is gradually increased to 87.9% after training of 60000 samples. However, the accuracy is quickly increased to 72.6% after training of 4000 samples, but degraded to 67.7% after training of 60000 samples when the conductance of synaptic devices is nonlinearly updated. This is because the nonlinear weight modulation characteristics increase or decrease the conductance of synaptic devices more than necessary. The synaptic weight maps of a total of 7840 synapses depending on nonlinear and linear weight modulation are shown in Figure 5b in the form of W = G+ − G−. Most of the synaptic weight values representing handwritten digits are significantly increased showing a big difference with other pixels in the case of nonlinear weight modulation because the conductance of synaptic devices can be quickly changed. However, only a small region, the most distinguishing area of handwritten digits, has a high value of synaptic weight in the case of linear weight modulation because of the linearity. These different weight modulation properties make a huge difference in the pattern recognition accuracy, leading us to believe that the linear weight modulation is one of the most important factors for synaptic devices considering its impact on the performance of neural network. The recent reports on memristor-based synaptic devices are summarized in Table 1. Most of the memristor devices used Pt and Ag, which are not suitable for CMOS processing. Moreover, only a small number of memristor devices were deposited using the CVD process. The operating voltage of the Ni/SiNx/AlOy/TiN memristors presented in this study can be improved by optimizing the fabrication process, device structure, and pulse scheme.

CONCLUSION The CMOS-compatible 3D crossbar array-applicable Ni/SiNx/AlOy/TiN memristor stack exhibits gradual set and reset switching characteristics, which are highly appropriate for synapse devices in neuromorphic applications. We firstly determined smooth and continuous gradual reset switching regions,


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and investigate the conduction mechanisms in order to demonstrate biological synaptic behavior. We observed symmetric and linear conductance modulation for LTP and LTD by adjusting the pulse amplitude. Furthermore, we demonstrated STDP, which is one of the important learning rules in biological synapses, by designing timing differences between pre- and post-synaptic spikes.

AUTHOR INFORMATION Corresponding Author *(S.K.): E-mail: [email protected] *(B.G.P.): E-mail: [email protected] Author Contributions B.G.P. conceived and designed the experiments. S.K. conducted the device fabrication process, performed the electrical experiments, and wrote the manuscript. H.K. and S.H. conducted simulation part and wrote it. M.H.K performed the electrical measurement. Y.F.C. helped the proposed model explanation. All authors have given approval to the final version of the manuscript.

Notes The authors declare no competing financial interest.

ACKNOWLEDGMENT This work was supported by National Research Foundation of Korea (NRF) funded by the Korean Ministry of Science, ICT&Future Planning (MSIP) with Grant No. 2015R1A2A1A01007307

SUPPORTING INFORMATION


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Two proposed 3D vertical structures; conduction mechanism; negative-set behavior when high CCL (1 m A) is applied; gradually modulated transient current by pulses with incremental amplitude for set and rese t; LTP and LTD by identical pulse and incremental pulse width; sensing current and applied voltage ampli tude for energy calculation of intermediate state; transient characteristics for STDP

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Figure Captions

Figure 1 Device Structure of Ni/SiNx/AlOy/TiN memristor and XPS analysis: (a) schematic drawing and (b) TEM image. (c) Si 2p spectra and (d) N 1s spectra for SiNx film. (e) Al 2p spectra and (f) O 1s spectra for AlOy film. Figure 2 (a) I-V characteristics depending on the forming polarity for the devices with and without Al2O3 layer. (b) The energy band diagram of Ni/SiN/TiN structure in flat band mode. (c) Overshoot rate depending on the forming polarity for the devices with and without Al2O3 layer.

Figure 3 I-V characteristics of Ni/SiNx/AlOy/TiN memristor: (a) linear-scale for set and reset switching, (b) Log-scale with different CCL (10 µA, 100 µA, and 1 mA), (c) reset transition for multilevel states.

Figure 4 Conductance modulation of Ni/SiNx/AlOy/TiN memristor in (a) identical pulse response and (b) pulse amplitude incremental response. (c) consecutive pulse trains with different amplitudes. (d) STDPlike curves.

Figure 5 Neural network simulation: (a) Classification accuracy as a function of the number of trained samples. (b) Synaptic weight (W = G+ - G-) map of 7840 synapse after training of 60000 samples.


19


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Page 20 of 24

Figure 1


20

(a) 10 Current [A]

-2 -4

10

Negative forming w/o Al2 O3

Current [A]

vacuum

(b)

Positive forming w/o Al2 O3

(c) 100

1.8 eV

10-6

ΦTiN =4.3 eV

ΦNi =5.1 eV

-8

10

10-2 Negative

Positive forming w/ Al2 O3

forming

10-4 w/ Al2O3

Eg= 5.3 eV

TiN

10-6

EF

SiN

Ni

-8

10

-10 -5 0 Voltage [V]

50

Negative forming w/o Al2O3

Positive forming w/o Al2 O3

Negative forming w/ Al2 O3

Positive forming w/ Al2 O3

0

0 5 10 Voltage [V]

Device and forming conditions

Figure 2

0.0010

10-2

(a)

10-2

(b)

(c)

10-4

0.0005

10-4

10m 100µ

-0.0010

Current [A]

-0.0005

Reset

100p 1p

-0.0015 -6

-4

-2

0

Forming

1µ 10n

10-6 100M

10-8 10-10

0

2

2

Voltage [V]

4 6 8 Voltage [V]

4

10

10M 1M 100k 10k

6

Current [A]

0.0000

Resistance [Ω]

Current [A]

Set

Current [A]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Overshoot rate [%]

Page 21 of 24

10-12

-6

10-6

Abrupt reset 10-8 10-10

10 µA

-4

100 µA CCL

-2

1 mA

CCL = 1 mA

0

2

Voltage [V]

4

6

10-12

-8

-6

-4

-2

0

Voltage [V]

Figure 3


21


(a)

LTD: 100 ns

20.0µ

100 ns (solid) 200 ns (open) 5V 5.5 V 6V 6.5 V

20.0µ LTP 15.0µ breakdown

Conductance [S]

25.0µ

-3.5 V

-4 V

10.0µ -4.5 V

5.0µ

-5 V -5.5 V

10

20

30

40

Pulse number [#]

50

0

10

20

30

40

Pre-spike

Potentiation

0.0

50

∆t < 0 Post-spike

5.0µ

0

Pulse number [#]

Post-spike

Pre-spike

Depression

10

20

30

40

50

60

70

Pulse number [#]

(c) ∆t > 0

-3.1~-5 V, 100 ns -0.05 V/step

10.0µ

0.0 0

(b)

15.0µ 5~6.15 V, 200 ns 0.05 V/step

Conductance change [%]

Conductance [S]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 22 of 24

600 400

(d) LTP

200 0 -200 LTD

-400 -600 -800 -40

-20

0

20

40

Pre/post spike interval (∆t) [µs]

Figure 4


22

Page 23 of 24

(a) 100

(b)

28

56

84

112

140

W [µS] 5.6

linear weight modulation

90

Accuracy [%]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


2.8

28

0

80 56

nonlinear weight modulation

70

-2.9

28

56

84

112

140

W [µS] 1.1

60

0.52

28

-0.07

0

10000 20000 30000 40000 50000 60000

-0.67

56

# Trained Samples

Figure 5


23


Table 1 Comparison of recent memristor-based synaptic devices. Stack

Deposition method

Gradual Set

Gradual reset

Pulse scheme

LTP pulse amplitude

LTD pulse amplitude

Weight change rate

Switching time

Pt/GeSO/TiN [9]

Sputtering

Yes

Yes

Incremental amplitude

0.7 V

–1.1 V

> 100 %

100 ns

Al/HfOx/ /CeOx/Au [10]

Evaporation

No

Yes

–

0.6 V ~ 1.6 V

–0.5 ~ –1.5 V

N/A

50 ns ~ 10 μs

TiN/TaOx/Pt [11]

Sputtering

Yes

Yes

Identical pulse

0.82 V

–0.96 V

~200 %

100 ns

Ag/MoOx/FTO [12]

CVD

Yes

Yes

Identical pulse

4V

–3 V

~200 %

100 ms

Pt/α –IGZO/Pt [13]

Sputtering

Yes

Yes

Identical pulse

5V

–5 V

~400 %

100 ms

TiN/HfOx/AlOx/Pt [14]

ALD

No

Yes

Incremental amplitude

2.2 V

–2.8 V

> 100 %

50 ns

Ag/PEDOT:PSS/Ta [22]

Solutionbased spin coating

Yes

Yes

Identical pulse

2V

–2 V

~200 %

~50 ms

Ni/SiNx/AlOy/TiN (This work)

CVD

Yes

Yes

Identical and incremental amplitude

5.3 V

–3.5 V

80 %~500 %

~200 ns

TOC

600 400 LTP

200 0 -200

20.0µ

LTD

-400 -600

Conductance [S]

Conductance change [%]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 24 of 24

15.0µ 10.0µ 5.0µ 0.0 0

-800 -40

-20

0

10 20 30 40 50 60 70 Pulse number [#]

20

40

Pre/post spike interval (∆t) [µs]


24

Analog Synaptic Behavior of a Silicon Nitride Memristor - ACS Applied

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