Artificial synaptic emulators based on MoS2 flash memory devices

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Functional Inorganic Materials and Devices

Artificial synaptic emulators based on MoS2 flash memory devices with double floating gates Sum-Gyun Yi, Myung Uk Park, Sung Hyun Kim, Chang Jun Lee, Junyoung Kwon, Gwan-Hyoung Lee, and Kyung-Hwa Yoo ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.8b10203 • Publication Date (Web): 14 Aug 2018 Downloaded from http://pubs.acs.org on August 15, 2018

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ACS Applied Materials & Interfaces

Artificial synaptic emulators based on MoS2 flash memory devices with double floating gates Sum-Gyun Yi1, Myung Uk Park1, Sung Hyun Kim1, Chang Jun Lee1, Junyoung Kwon2, GwanHyoung Lee2 and Kyung-Hwa Yoo1*. 1

Department of Physics, Yonsei University, 50 Yonsei-ro, Seoul, 03722, Republic of Korea.

2

Department of Materials Science and Engineering, Yonsei University, 50 Yonsei-ro, Seoul,

03722, Republic of Korea. KEYWORDS. synaptic emulator, neuromorphic, MoS2, double floating gate, flash memory device

Abstract

We fabricated MoS2-based flash memory devices by stacking MoS2 and hBN layers on an hBN/Au substrate, and demonstrated that these devices can emulate various biological synaptic functions, including potentiation and depression processes, spike-rate-dependent plasticity, and spike-timing dependent plasticity. In particular, compared to a flash memory device prepared on an hBN substrate, the device fabricated on the hBN/Au exhibited considerably more symmetric and linear bidirectional gradual conductance change curves, 1

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which may be attributed to the device structure incorporating double floating gate. For the device on the hBN/Au, electron transfers may occur between the floating gate MoS2 and Au, as well as between the floating gate MoS2 and the channel MoS2, allowing for more control over electron tunneling and injection. To test our hypothesis, we also fabricated a MoS2based flash memory device on an hBN/Pd substrate and found similar behavior to the device fabricated on hBN/Au. Our results demonstrate that flexible synaptic electronics may be implemented using MoS2-based flash memory devices with double floating gates.

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Introduction Significant efforts have been made to develop biologically inspired neuromorphic networks with the capacity to mimic the massive parallelism and low-power operation found in the human brain, as the human brain can outperform supercomputers in many respects.1-4 To date, a large number of reports have investigated neural networks using complementary metal-oxide-semiconductor (CMOS) technology.5-7 However, implementing the functions of biological synapses in CMOS-based circuits remains challenging because synaptic weights are non-volatile and adjustable, which is uncommon in conventional CMOS devices.8,9 Previously, a variety of two-terminal memristors have been explored for the implemention of synaptic devices, and synaptic learning rules such as spike-rate-dependent plasticity (SRDP) and spike-timing dependent plasticity (STDP) have been demonstrated in various material systems including AgS2,10,11 WOx,12 Ag-doped TiO2,13 and Ge2Sb2Te5.14 More recently, three-terminal devices have been proposed as artificial synapses for emulating biological synaptic functions since three-terminal devices can realize learning and memory functions concurrently.15-19 In recent years, atomically thin two dimensional (2D) materials such as graphene, semiconducting transition metal dichalcogenides, and insulating hexagonal boron nitride (hBN) have received considerable attention owing to their possible application in ultrathin, flexible, and nearly transparent electronic and optoelectronic devices20-23. For example, MoS2 and hBN have been incorporated into nonvolatile memory structures serving as the floating gate and tunnel barrier, respectively22,23. In this study, we investigate whether a threeterminal memory device fabricated from stacked 2D materials can be applied to emulate biological synaptic functions. To do so, we fabricated a MoS2-based flash memory device on an hBN/Au substrate and compared it to one fabricated on an hBN substrate. The former 3



exhibited symmetric characteristics of potentiation and depression, whereas the latter exhibited asymmetric and non-linear directional gradual conductance change curves. The advantage of the synaptic emulator based on the flash memory device compared to the two terminal memristor is that the floating-gate synaptic emulator allows simultaneous memory reading and writing, so additional selection devices, such as transistors and diodes, are not required to construct a synaptic array.24 In addition, the flash memory device is operated by electron injection and tunneling rather than ion movements, so the operating speed of floating-gate synaptic device will be faster than that of the ion-gated synaptic transistors.15-19 To understand the different behavior of MoS2-based flash memory devices on hBN and hBN/Au substrates, we measured the workfunction of MoS2 on hBN and hBN/metal substrates using a scanning Kelvin probe microscope (SKPM),25-27 since all of atoms are exposed to the surface in 2D materials, so their properties, such as workfunction (i.e., the energy required to extract an electron from a material to a vacuum) may be easily modulated by the surrounding environment.28 Indeed, the measurements revealed that the workfunction of MoS2 on the hBN/metal differs from that of MoS2 on hBN, and that it depends on the metal underneath the hBN layer. Based on these findings, we propose energy band diagrams showing how Au acts as another floating gate for flash memory devices on hBN/Au, resulting in more controllable electron tunneling and injection. Because the symmetry of potentiation and depression is the most important requirement among the various synaptic behaviors,29 these results demonstrate that flexible synaptic electronics may be implemented using MoS2based flash memory devices with double floating gates.

Results and discussion

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First, we investigated whether the workfunction of few-layer MoS2 is affected by metals with different workfunctions through an hBN layer. A specimen was prepared by depositing Au (42 nm) and Al (42 nm) films on a Si substrate and subsequently transferring a stacked layer consisting of hBN (3 nm) and MoS2 (5 nm) over the Au and Al films (Figures 1a and S1). The contact potential difference (VCPD) image was acquired using the SKPM (Figure 1b), since the VCPD between a SKPM tip and a sample is given by

ܸ஼௉஽ =

ఝ೟೔೛ ିఝೞೌ೘೛೗೐

(1)

ି௘

where ϕtip and ϕsample are the workfunctions of the tip and sample, respectively, and e is the electronic charge. The green line in Figure 1b represents the VCPD measured across uncovered Au and Al films with hBN (Figure 1c). The difference in VCPD values between Au and Al films was about 0.4 V, which is smaller than the reference value of 0.8-1.2 eV.30 However, when the CPD image was measured before transfer, the difference in VCPD values between the Au and Al films was estimated to be about 0.8 V (Figure S3), implying that contamination occurring during the transfer of hBN and MoS2 might decrease the VCPD difference between the Au and Al films. Figure 1d shows the line profiles of VCPD in the y - direction denoted using brown, blue, and pink lines in Figure 1b. The MoS2 flake exhibited different values of VCPD depending on the material layers. Assuming that the workfunction of MoS2 measured on hBN is close to the reported value of 4.3 – 4.6 eV,22 the workfunction of MoS2 increased by ~0.1 eV on hBN/Au, and decreased by ~0.08 eV on hBN/Al. The line profile of VCPD in the x – direction, denoted using a red line in Figure 1c, also showed that the VCPD of MoS2 on hBN/Au was higher than

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that of MoS2 on hBN/Al by ~0.18 eV. These results indicate that the workfunction of MoS2 might be modulated by Au or Al via the hBN layer. To confirm the workfunction modulation of MoS2 through the hBN layer, we fabricated MoS2 field effect transistors (FETs) with hBN as the encapsulating layer on SiO2/Si substrates, followed by depositing Au or Al pattern on the hBN (Figures 2a and 2b). Figure 2c shows the source-drain current (ISD) – gate voltage (VG) transfer curves measured before and after the deposition of the Au or Al pattern, where the highly doped Si substrate was used as a gate electrode. After depositing the Au pattern, the threshold voltage (Vth) shifted to a positive value. By contrast, the Al pattern shifted the Vth to a negative value (Figure 2d). These results corroborate the results of the SKPM analysis that is, the metals located underneath the hBN layer modulate the workfunction of MoS2. Next, we constructed a flash memory device by transferring the stacked layers of channel MoS2/upper hBN/underlying MoS2/lower hBN onto a SiO2 (300 nm)/Si substrate, as shown in Figure S1 (device I, Figure 3a). Figure 3d shows the ISD – VG transfer curve measured for device I by sweeping VG from -40 to +40 V, and back to -40 V. A large memory window (∆V) of ~20 V was observed, indicating that the underlying MoS2 in device I acts as a charge trapping layer. 22,23 To determine whether ∆V was affected by the thickness of the underlying MoS2, we fabricated various devices with different thicknesses of the underlying MoS2. However, there was no clear relationship between ∆V and the thickness of the underlying MoS2 (Figure S4). For comparison, we also fabricated a FET device on the hBN/SiO2/Si substrate. The ISD – VG transfer curve of this FET device showed no hysteresis (Figure 3e), confirming that the memory effects observed with device I were caused by the charge trapped in the underlying MoS2. Moreover, we noted that as the VG was swept, ISD changed more rapidly for device I than for the FET device. In other words, when the ISD was normalized by 6


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ISD at VG=40 V and differentiated with respect to VG, the higher values of dISD/dVG were found for device I than for the FET device. To explore whether the characteristics of the flash memory device are affected by the workfunction modulation of the underlying MoS2 layer, we fabricated device II on an hBN/Au substrate (Figures 3b, 3c, and S1). The ISD of device II depended strongly on VG, implying that the Au layer did not screen significantly the electric field induced by VG (Figures 3f). In addition, when the ISD-VG transfer curves were measured in different ranges of VG, a smaller ∆V was observed for the narrower VG sweep range, which is consistent with conventional flash memory devices (Figure S5).31,32 However, when compared to device I, device II exhibited a larger ∆V (≈ 40 V) and higher maximum values in dISD/dVG. These results suggest that the workfunction of the underlying MoS2 layer was increased by the Au layer, potentially contributing to more rapid changes in the carrier concentration of the MoS2 channel upon application of VG. To investigate the data retention property of device II, we measured ISD at VSD = 0.1 V in the low resistance state (LRS) and high resistance state (HRS) as a function of time (Figure S6). No significant change in resistance magnitudes was observed within 104 s for both the LRS and HRS. In addition to device II, we fabricated device III, which incorporated Al instead of Au, since Al decreased the workfunction of the underlying MoS2 layer (Figure 3g). In contrast to device II, the ∆V of device III was smaller than the ∆V of device I, and the maximum values in dISD/dVG of device III were comparable to those of device I. These measurements indicate that the characteristics of MoS2–based flash memory devices might be dependent on the workfunction of the underlying MoS2 layer. To further investigate this hypothesis, we fabricated another device with Pd (device IV), whose workfunction (5.22-5.6 eV) is close to that of Au.30 Similarly to device II, device IV exhibited a larger ∆V and higher maximum values in dISD/dVG when compared to device I (Figure 3h). These observations further 7



corroborate the hypothesis that the characteristics of MoS2 flash memory devices are influenced by the workfunction modulation of the underlying MoS2 layer. Figure 3i shows the values of ∆V estimated for various devices with different thicknesses of the upper hBN layer. The ∆V increased with decreasing thickness of the upper hBN layer. A relationship between ∆V and the thickness of the lower hBN layer was also investigated; however, a clear relationship was not found (Figure S7). Figure 4a illustrates the energy band diagrams of device I. The energy bandgap (Eg) and electron affinity (χ) are approximately 1.2 eV and 4 eV for the multi-layer MoS2, 6 eV and 2 eV for hBN, and 9 eV and 0.9 eV for SiO2, respectively.33-35 Therefore, the barrier height for electron tunneling from the channel MoS2 (MoS2(1)) to the underlying MoS2 (MoS2(2)) through the upper hBN layer (BN(1)) (Φe1) is approximately 2 eV. When a high positive voltage is applied to VG (VG > 0), electrons can tunnel from MoS2(1) to MoS2(2) through BN(1), most likely via the Fowler-Nordheim tunneling,36 but cannot tunnel through BN(2) because of the SiO2. The resultant accumulation of electrons in MoS2(2) acts to screen the bottom-gate electric field that can reach the MoS2 channel, which results in a positive shift in the value of the Vth. However, when a negative voltage is applied to VG (VG < 0), electrons are transferred back from MoS2(2) to MoS2(1); simultaneously, holes can tunnel through BN(1) and become trapped in MoS2(2). As a result, the Vth shifts to a negative value, leading to ∆V. In addition, this electron tunneling between MoS2(1) and MoS2(2) might cause a larger variation in the carrier concentration of the channel MoS2 for device I than for the FET device, leading to a higher dISD/dVG. According to the results of SKPM analysis, the workfunction of the underlying MoS2 is expected to increase from ~4.4 eV to ~4.5 eV for device II and to decrease to ~4.32 eV for device III. Therefore, the barrier height for electron tunneling from MoS2(2) to Au or Al 8


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through the lower hBN layer (BN(2)) (Φ e2) is estimated to be 1.9 eV for device II (Figure 4b) and 2.08 eV for device III, respectively (Figure 4c), although Φ e1 is 2 eV for both devices. In the case of device II, when VG > 0, electrons can tunnel through BN(1) as well as BN(2), and thus electrons are trapped in MoS2(2) as well as the Au film (Figure 4b). Consequently, the electric field that can reach MoS2(1) is more screened, which in turn shifts the Vth to a more positive value. When VG < 0, electrons are transferred from MoS2(2) and Au to MoS2(1), and holes are trapped in MoS2(2). As a result, device II yields larger ∆V and higher dISD/dVG when compared to device I, as shown in Figure 3. By contrast, the Φe2 of device III may be higher than the Φe2 of device II, and may increase further because of the oxide film (AlOx) formed on the Al surface (Figure 4c). Therefore, electron tunneling from MoS2 (2) to Al is most likely not permitted, resulting in a narrower ∆V for device III than for device II. Finally, we investigated whether the MoS2-based flash memory devices can be applied to synaptic devices. To mimic the potentiation and depression processes, the conductance change (∆S/S0) was measured for devices I (Figure 5a) and II (Figure 5b), while a series of 20 negative and positive voltage pulses with a width of 1 ms and a period of 1 s was applied to VG, where S0 is the initial conductance. The applied voltage amplitudes were -28 and +23 V for device I, and -12.5 and +24.2 V for device II, respectively. The application of negative (potentiating) voltage pulses resulted in a stepwise increase in ∆S/S0 for both devices, which was ascribed to a non-volatile element. However, as the voltage pulses were applied repeatedly, the ∆S/S0 of device I increased more slowly, while the ∆S/S0 of device II increased steadily. Furthermore, when the positive (depressing) voltage pulses were applied 20 times, the ∆S/S0 of device II decreased linearly down to the initial value, whereas the

∆S/S0 of device I decreased nonlinearly. Figure 5c illustrates the ∆S/S0 of device II measured 9



while a series of potentiating and depressing pulses were applied repeatedly. The measured

∆S/S0 exhibited linear and repeatable behaviors. Compared to the reported ion-gated synaptic transistors (2.5~5 V, 10 ms), 15-18 the higher voltage pulses were applied for the potentiation and depression process. However, the pulse width was shorter, so the power consumption was not higher than that of the reported ion-gated synaptic transistors. In fact, the 10 ~ 25 V requirement for device II was a consequence of the 300 nm-thick SiO2 gate oxide. If the thickness of SiO2 is reduced, the voltage pulse height and width can be significantly reduced, resulting in very low power consumption. The only difference between devices I and II is the presence of the Au layer under the lower hBN layer. It suggests that the presence of Au might contribute to improving the linearity and symmetry of bidirectional gradual conductance curves for device II. In the case of device II, charge transfer might occur between the underlying MoS2 and the Au layer, as well as between the channel MoS2 and the underlying MoS2 (Figure 4). As a result, when the voltage pulses were repeatedly applied, the stored charge on the underlying MoS2 might saturate more slowly for device II than for device I, improving the linearity of device II. To evaluate this possibility, we carried out similar measurements for device IV. Device IV exhibited bidirectional gradual conductance changes that were similar to those observed for to device II (Figure S8), supporting the hypothesis that the improved symmetry and linearity might be attributed to Au or Pd acting as another floating gate. These results demonstrate that the MoS2-based flash memory devices with double floating gates possibly simulate the potentiation and depression processes. To determine whether spike-rate-dependent plasticity (SRDP) can also be realized using device II, ∆S/S0 was measured after the application of a series of 10 identical negative voltage pulses with different delay times (∆t) to VG, in which the voltage amplitude was -29 V and 10


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the pulse width was 1 ms (Figure 5d). The ∆S/S0 remained nearly unchanged for ∆t > 15 ms. However, for ∆t < 15 ms, the ∆S/S0 increased with decreasing ∆t, thereby indicating that short-term plasticity and long-term potentiation might be mimicked using device II.37 The effects of symmetric presynaptic and postsynaptic pulses do not cancel each other and the net effect is dominated by the timing difference between the presynaptic and postsynaptic effects, leading to the learning rule STDP.13,16 To realize STDP functionality, voltage pulses with an exponentially decaying function of time difference, td = tpre - tpost, was applied to VG, where tpre and tpost are the time when the presynaptic and postsynaptic pulses spike, respectively. Figure 5e shows the ∆S/S0 measured as a function of td. When the presynaptic spike occurred before the postsynaptic spike (td > 0, potentiation), the conductance (synaptic weight) decreased with increasing ∆t. When the postsynaptic spike occurred prior to the presynaptic spike (td < 0, depression), reverse modulation was observed. In addition, the plot of ∆S/S0 versus td could be well fitted with exponential decay functions, demonstrating that neural synaptic STDP behavior may be achieved using device II.13

Conclusion SKPM analysis showed that the workfunction of MoS2 placed on hBN/metal depends on the metal. In addition, this workfunction modulation of MoS2 through the hBN layer was supported by ISD - VG transfer curves measured for MoS2-based FET devices. To investigate whether the characteristics of MoS2-based flash memory device are affected by the workfunction modulation of MoS2 acting as a floating gate, we fabricated MoS2-based flash memory devices on hBN, hBN/Au, and hBN/Al substrates. The device fabricated on hBN/Au yielded larger memory windows than the device prepared on hBN, whereas the device fabricated on hBN/Al showed comparable memory 11



windows to the device on hBN. Furthermore, the symmetry and linearity of the bidirectional gradual conductance change curves improved significantly with the device fabricated on the hBN/Au substrate compared to the devices prepared on hBN or hBN/Al. To explain this, we proposed energy band diagrams that show how Au acts as another floating gate, while Al does not, owing to the oxide film that forms on the Al surface. For flash memory devices with double floating gates, electron transfers occur between the underlying MoS2 and Au, as well as between the underlying MoS2 and the channel MoS2. Thus, electron tunneling and injection may be more controllable, leading to the symmetry of potentiation and depression processes. This hypothesis was investigated by fabricating a device on an hBN/Pd substrate. This device exhibited behavior similar to that of the device fabricated on hBN/Au. In addition, various synaptic functions, including potentiation and depression processes, SRDP, and STDP, could be emulated using flash memory devices fabricated on hBN/Au, demonstrating that MoS2-based flash devices with double floating gates may be applied to synaptic emulators. To show proof- of-concept, we fabricated devices using the pick-up method. However, if large scale MoS2 and hBN layers are available, the synaptic array may be constructed using conventional lithography techniques.

Methods Device fabrication The flash memory devices were fabricated as shown in Figure S1. First, MoS2 and hBN flakes were mechanically exfoliated from MoS2 (SPI supply) and hBN (HQ graphene) single crystals onto a SiO2/Si substrate. Subsequently, they were transferred to another substrate using a hot pick-up method with a polypropylene carbonate film (PPC, Sigma-Aldrich, CAS 25511-85-7).38 Briefly, 1-µm thick PPC film was spin-coated onto a SiO2/Si substrate and 12


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peeled off from the substrate using a scotch-tape with a center hole. The PPC film was transferred onto a polydimethylsiloxane (PDMS) block on a slide glass, followed by heating at 120 °C for 1 min to enhance the adhesion of PPC to PDMS. The hBN flake prepared on the SiO2/Si substrate was picked up using the PPC film on the PDMS block, and the MoS2 flake was picked up by placing the hBN layer on the MoS2 flake. In the same way, the hBN flake was picked up, affording an hBN/MoS2/hBN stacked layer. This layer was released onto a metal/SiO2/Si or SiO2/Si substrate at 180°C by dissolving the PPC film in chloroform, where metals such as Au (30 nm), Al (30 nm), and Pd (30 nm) were deposited using an electron-beam evaporator. Next, the channel MoS2 flake was transferred onto the stacked sheets (hBN/MoS2/hBN) using the PDMS stamping method to avoid contamination. Finally, Cr (3 nm)/Au (30 nm) electrodes were made using electron-beam lithography and lift-off techniques. The thicknesses of the MoS2 and hBN flakes measured using AFM were approximately 10 ~14 nm and 10 ~ 34 nm, respectively, as summarized in Table S1. Contact potential difference (CPD) and electrical measurements The CPD was measured using a scanning Kelvin probe microscope (NX10, Parks System, Korea) at ambient conditions. The tip was a conductive Si tip coated with Au (PPP-NCHAu AFM, Nanosensors). Electrical measurements were carried out using a semiconductor characterization system (4200-SCS, Keithley). To measure the synaptic functions, voltage pulses were applied using an ultra-fast I-V module for 4200-SCS (4225-PMU, Keithley).

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Figure 1. Workfunction of MoS2 modulated by Au and Al. (a) Schematic diagram of the specimen prepared by stacking metals (Au and Al), hBN, and MoS2 layers for SKPM measurements. (b) SKPM image of the specimen prepared by stacking metals (Au and Al), hBN, and MoS2 layers. The topography image measured simultaneously with SKPM is shown in Figure S2. The hBN layer is denoted with white dotted curves. (c) The x-directional line profiles of VCPD obtained for uncovered Au and Al with hBN and MoS2 layers (green line in b) and for the MoS2 layer on hBN layer and Au (or Al) (red line in b). (d) The ydirectional line profiles of VCPD obtained for the MoS2 layer on hBN layer and Au (brown line in b), for the MoS2 layer on hBN layer (blue line in b), and for the MoS2 layer on hBN layer and Al (pink line in b).

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Figure 2. Effects of metals on the MoS2 FET devices through the hBN layer. (a) Schematic diagram of the MoS2 FET device with hBN layer and Au (or Al). (b) Optical image of the fabricated device. (c) The ISD-VG transfer curves measured at VSD=0.1 V before and after depositing Au on the hBN layer. (d) The ISD-VG transfer curves measured at VSD=0.1 V before and after depositing Al on the hBN layer.

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Figure 3. Memory effects of various MoS2-based flash memory devices. (a) Schematic diagram of a MoS2-based flash memory device fabricated on SiO2/Si substrate (device I). (b) Schematic diagram of a MoS2-based flash memory device fabricated on metal/SiO2/Si substrate. Devices II, III, and IV are prepared on Au, Al, and Pd/SiO2/Si substrates, respectively. (c) An optical image of device II. (d-h) The ISD-VG transfer curves (black symbols) and dISD/dVG (red curves) for (d) device I, (e) FET, (f) device II, (g) device III, and (h) device IV. The ISD-VG transfer curves were obtained by sweeping VG from -40 to +40 V and back to -40 V, and ISD was normalized by ISD at VG=40 V for comparison among different devices. (i) Memory windows (∆V) versus the thickness of the upper hBN layer estimated for various MoS2-based flash memory devices. The filled and open symbols represent ∆V estimated from the ISD-VG transfer curves in the VG sweep range of -40 ~ 40 V and -60 ~ 60 V, respectively. 16


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Figure 4. The energy band diagrams of devices I, II, and III. (a) The energy band diagrams in a flat band state, equilibrium, VG > 0, and VG < 0 for device I. EC, EV, Eg, χ, ϕ, and Φ1 are the conduction band energy, valence band energy, energy bandgap, electron 17



affinity, workfunction, and tunneling barrier height from the MoS2(1) to MoS2(2) through BN(1). For VG > 0, electrons tunnel from MoS2(1) to MoS2(2) through BN(1) and are subsequently trapped in MoS2(2). For VG < 0, electrons tunnel from MoS2(2) to MoS2(1) through BN(1), while holes tunnel from MoS2(1) to MoS2(2). (b) The band diagrams in a flat band state, equilibrium, VG > 0, and VG < 0 for device II. Φ2 is the tunneling barrier height from MoS2(2) to Au through BN(2). For VG > 0, electrons tunnel from MoS2(1) to MoS2(2) through BN(1), as well as from MoS2(2) to Au through BN(2). For VG < 0, electrons tunnel from Au to MoS2(2) through BN(2), as well as from MoS2(2) to MoS2(1) through BN(1). (c) The band diagrams in a flat band state, equilibrium, VG > 0, and VG < 0 for device III. AlOx forms on the Al surface naturally, leading to an increase in Φ2 and prohibiting electron transfer between Al and MoS2.

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Figure 5. Simulation of synaptic functions. (a) Conductance change measured at ISD=0.1 V for device I while repeated potentiation (-28 V for 1 ms, spaced 1 s apart) and depression (23 V for 1 ms, spaced 1 s apart) pulses are applied to VG. The conductance change was normalized by the initial conductance (∆S/S0). (b) ∆S/S0 measured at ISD=0.1 V for device II while repeated potentiation (-12.5 V for 1 ms, spaced 1 s apart) and depression (24.2 V for 1 ms, spaced 1 s apart) pulses are applied to VG. (c) ∆S/S0 measured at ISD=0.1 V for device II while potentiation and depression gate voltages are applied repeatedly. (d) ∆S/S0 measured at ISD=0.1 V for device II after gate pulses (-29 V for 1 ms) with various delay times (∆t) are applied 10 times, demonstrating spike-rate dependent plasticity (SRDP). (e) ∆S/S0 measured at ISD=0.1 V for device II after presynaptic (Vpeak = 35 V) and postsynaptic pulses (Vpeak = -35 V) are applied with a time difference td, as shown in the left inset, demonstrating spike-timing dependent plasticity (STDP). The source and drain are analogues of the preneuron and postneuron terminals, respectively. The red curves are an exponential decay function fitted to the data. 19



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Additional information Supplementary information is available in the online version of the paper. Reprints and permissions information is available online at http://pubs.acs.org. Correspondence and requests for materials should be addressed to K.Y. *Corresponding author e-mail: K-H Yoo, [email protected] Author contributions K.Y., S.Y., and G.L. conceived and designed the study. S.Y. J.K. M.P. and C.L. fabricated devices and performed the electrical measurements. S.K. performed the SKPM measurements. K.Y. and S.Y. wrote the manuscript. All authors discussed the results and commented on the manuscript. Competing financial interests The authors declare that they have no competing interests. Acknowledgements This work has been financially supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and Future Planning (Grant Nos. 2016R1A2B3011980).

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SYNOPSIS TOC

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Artificial synaptic emulators based on MoS2 flash memory devices

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