Binary Resistive-Switching-Device-Based Electronic Synapse with

Article Cite This: ACS Appl. Electron. Mater. 2019, 1, 845−853

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Binary Resistive-Switching-Device-Based Electronic Synapse with Spike-Rate-Dependent Plasticity for Online Learning Peng Huang,* Zefan Li, Zhen Dong, Runze Han, Zheng Zhou, Dongbin Zhu, Lifeng Liu, Xiaoyan Liu, and Jinfeng Kang* Institute of Microelectronics, Peking University, No. 5 Yiheyuan Road, Haidian District, Beijing, P. R. China 100871

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S Supporting Information *

ABSTRACT: Neuromorphic computing is promising to become a future information processing technology with much less energy consumption, higher efficiency, and larger volume. A key element to build an electronic neuromorphic computing system is the synapse, which should be implemented with a simple device that can be easily integrated into large systems because of its vast amount. Here, inspired by a stochastic-forgetting learning concept, we experimentally demonstrate the spike-rate-dependent plasticity (SRDP) synaptic behavior with a one-transistor−one-resistive-switching-device structure and its application in unsupervised online learning. Furthermore, a convolutional neural network-SRDP two-layer network is proposed to recognize the full MNIST data set with 92% accuracy, which is a significant improvement compared with the 56% accuracy achieved by the same scale neural network using a back-propagation algorithm. This work may introduce new possibilities into the implementation of a high-performance artificial neural system for applications with none or very few human-labeled data. KEYWORDS: resistive switching device, electronic synapse, spike-rate-dependent plasticity, online learning, SNN

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INTRODUCTION In the era of artificial intelligence, many intellectual tasks such as pattern recognition, decision making, and natural language processing are assigned to computers. However, the traditional von Neumann paradigm becomes less efficient when dealing with these tasks because of significant hardware overhead and energy consumption on data movement between the computing unit and memory.1,2 Biological brains outperform conventional computers on these aspects probably because they process information in a fundamentally different way, which is parallel, flexible, distributed, and error-tolerant.3,4 Large systems implemented with a CMOS circuit have been reported but with large hardware cost.5−7 Recently, a “memristor”,8 including various kinds of devices such as resistive switching memory (RRAM),9−11 has been proposed as a promising candidate for an artificial synapse1,12−15 or both for a synapse and neuron to build a fully memristive neural network.16 Up to now, neural network utilizing the RRAM devices as the synapse can recognize a large pattern data set with desirable accuracy based on supervised learning with the back-propagation (BP) algorithm. Neural networks with the BP algorithm require a vast amount of data to train them with the feedback circuit, which leads to additional chip area, energy consumption, and latency.17,18 Inspired by a more basic mechanism of the signal propagation between biological synapses, the spiking neural network (SNN) is proposed,18−22 within which information is conveyed and processed in the form of spikes. Spike-time-dependent plasticity (STDP) and © 2019 American Chemical Society

spike-rate-dependent plasticity (SRDP) are two essential principles of the synapse weight update within SNN.23−26 The STDP synapse tunes the weight according to the time difference between spikes from the presynaptic neuron and postsynaptic neuron, whereas the SRDP synapse relies on the frequency of the input signal for the weight update.26−31 Recently, the implementation of the STDP/SRDP synaptic function has been demonstrated with RRAM devices,32−35 and a small SNN has been proposed to learn a small quantity of small-scale images.36−39 However, the capability of these SNNs is still limited and is not enough to support the practical application, such as the recognition of a full MNIST data set.40 Here, we propose an electronic synapse with SRDP implemented with a one-transistor−one binary RRAM-device (1T1R) structure and demonstrate an SNN capable of unsupervised online learning of hand-written digits in an MNIST data set. First, we will experimentally demonstrate the SRDP synapse function with the 1T1R structure and the corresponding neuron circuit with stochastic-forgetting learning concept.41,42 Second, the SNN constructed by the proposed SRDP synapse will be designed and optimized to achieve unsupervised online learning.43 Finally, we will propose a convolution neural network (CNN)-SRDP twolayer system to achieve up to 92% accuracy for the full MNIST Received: January 5, 2019 Accepted: May 21, 2019 Published: May 22, 2019 845

DOI: 10.1021/acsaelm.9b00011 ACS Appl. Electron. Mater. 2019, 1, 845−853

Article

ACS Applied Electronic Materials

Figure 1. Biological synapse and electronic synapse with SRDP. (a) The biological neural network, the presynaptic neuron, and postsynaptic neuron are connected by synapse. The synapse weight is used to represent the strength of the connection between the presynaptic neuron and postsynaptic neuron. (b) The observed relationship of synapse plasticity and signal frequency in biological experiment, named as spike-ratedependent plasticity (SRDP). For SRDP, the high-frequency signal between the presynaptic neuron and postsynaptic neuron will cause the synapse weight to be strengthened, whereas low-frequency signal will cause the synapse weight to be weakened, because the weights of all synapses will gradually be weakened due to “forgetting”. (c) The circuit diagram of the proposed electronic synapse, which is designed to mimic the SRDP function of the biological synapse. The SEL port is controlled by a reference random signal to emulate automatic forgetting behavior. BE is the bottom electrode of RRAM. D is the drain of the transistor. B is the body of the transistor. S is the source of the transistor. SEL is the selected port of MUX. (d) The dependence of the synapse weight W and the frequency of the preinput signal f in obtained experimentally in the proposed electronic synapse. The synaptic weight is the mean of 300 measurements.

between the presynaptic neuron and postsynaptic neuron will cause long-term potentiation (LTP), whereas the lowfrequency spikes will cause long-term depression (LTD).24 To emulate the biological SRDP characteristic, a neuron circuit including a 1T1R-based electronic synapse was proposed as schematically shown in Figure 1c. The presynaptic neuron circuit is a multiplexer (MUX), which selects the preinput signal or prenoise signal and forwards the selected signal to the synapse under the control of a reference random signal. The postsynaptic neuron consists of an integrator, a comparator, and a switching matrix (SM) module. Here, the synapse weight is represented by the series conductance of the RRAM device and the on-state transistor. The synapse can be updated via tuning the conductance of the RRAM device. The whole training process consists of three phases: accumulation, enhancement, and depression. During the accumulation phase, the MUX will select the preinput signal and forward it to the transistor gate of the synapse. Meanwhile, SM will select a constant signal VS and send it to the top electrode (TE) of the RRAM device. Thus, the preinput signal is transferred to the current through the synapse. The capacitor

data set. It is much higher than the 56% accuracy obtained by training the identical fully connected network with the typical BP algorithm. Our whole proposed methodology implements the SRDP synapse function and achieves considerable accuracy for unsupervised learning of a 10 000 hand-written digit data set with low circuit overhead of the 1T1R crossbar. Thus, it offers a new approach into future implementation of an SNNbased neuromorphic computing system for the computationally intensive cognitive tasks.

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RESULTS AND DISCUSSION SRDP Characteristic of the Electronic Synapse with Binary 1T1R Structure. Biologically, learning and memory are related to the synapse weight and synapse weight update between the presynaptic neuron and the postsynaptic neuron.23−26 Among many rules that try to explain the mechanism of the synapse weight update, SRDP is one of the typical explanations.22−24 Figure 1a,b schematically shows the SRDP behavior in the biological neural network and the corresponding experimental data. The high-frequency spikes 846


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Figure 2. Online learning progress of the SRDP-based neural network. (a) The circuit diagram of the fully connected synapse layer for the SRDPbased neural network. There is an internal random signal source to generate the reference random signal. (b) The schematic of the input frequency signal for digit “1”. The pattern pixel will send signal with frequency f p, and the background pixel will send signal with frequency f b. (c) The evolution of the membrane voltage, TE voltage, and integral current in the single postsynaptic neuron during the learning process, from which we can see the process of current integration on membrane voltage, SET, and RESET of the postsynaptic neuron clearly. (d) The gradual learning process for digit “1” as an example. The weights of physical RRAMs in the same bit line are reconfigured to the 28 × 28 pixel image. (e) The evolution of the mean weight of pattern pixels and background pixels. From Figure 2d,e, we can see the mean weight of pattern pixels and background pixels gradually approach HGS and LGS separately, and the learned image becomes more clear, proving the learning ability of the SRDP-based neural network.

SET spike and send it to the top electrode of the RRAM device. If the SET spike coincides with an preinput signal spike, the synapse weight will be enhanced. To implement the “forgetting” function of the biological synapse, a reference random signal is introduced as shown in Figure 1c. When the spike of a reference random signal is sent to the MUX and SM, the neuron circuit will enter the depression phase. The MUX will select the prenoise signal and forward it to the transistor gate of the synapse. Meanwhile, a RESET spike will be selected

of the integrator will integrate the current from the synapse. Thus, the membrane voltage (Vm), the potential of node A as shown in Figure 1c, would increase under the control of the preinput signal. Once Vm exceeds the threshold voltage Vth, the comparator module would generate a spike and send it to the transistor of the integrator to discharge the capacitor. Meanwhile, the generated spike will be sent to the enabled node of the SM module, which triggers the enhancement phase. During the enhancement phase, the SM will select a 847


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conductance state of the RRAM device are abbreviated as HGS and LGS, respectively. Our RRAM device can switch between 2.4 mS and 2.4 μS, which gives us about a 1000× conductance window. The detailed fabrication process and characterization of the RRAM device are in the Methods section “HfOx RS Device Fabrication” and Figure S1 of the Supporting Information. The transistor characteristic is in Figure S2 and Table S1 (Supporting Information). Figure 1d is the measured dependence of the synapse weight after training with different f in; here, the frequency is the spike number within a unit time. In the experiment, we choose 24 frequency points ranging from 3000 to 400 000 Hz. At every frequency point, different input signals with the same frequency are applied 300 times. Initially, the RRAM device has the probability P to be in the HGS according to our proposed training principle of the SRDP-based neural network. To guarantee the robustness of the system, we choose the 5000 and 200 000 Hz for the binary operation frequency (eetailed settings about the experiment are in the Methods section “SRDP Experimental Settings”). The measured dependence of synapse weight on the f in is similar to the biological SRDP synaptic behavior as shown in Figure 1b, which implies that the biological SRDP synaptic behavior can be implemented by the proposed neuron circuit. The dependence of synapse weight (W) in Figure 1d can be depicted as

and sent to the TE of RRAM device. If the RESET spike coincides with a prenoise spike, the synapse will experience depression. The depression process is stochastic due to the randomness of reference random signal and prenoise, so it is called stochastic-forgetting. The updated direction of the synapse weight can be described as follows l o o≥0 ε(VT − VSE) ·ε(VG − VF) = 1/4 ΔW (t ) = m o o o n≤0 ε(VT − VR ) ·ε(VG − VF) = 1/4

(1)

ε(x) is the unit step function, and ε(x < 0) = 0, ε(0) = 1/2, and ε(x > 0) = 1. VT is the voltage on the top electrode of RRAM. VG is the voltage on the transistor gate of the synapse. VSE (VR) is the amplitude of the SET (RESET) spike. The amplitude of the reference random signal, preinput signal, and prenoise signal are the same and is represented as VF. In summary, when a SET spike from the postsynaptic neuron (VT = VSE) coincides with a preinput signal spike (VG = VF), the synaptic weight would be enhanced. Although a RESET spike from the postsynaptic neuron (VT = VRE) coincides with a reference signal spike (VG = VF), the synapse experiences a stochastic depression. The synapse weight would be unchanged if the postsynaptic neuron spike does not coincide with the presynaptic neuron spike. The synaptic weight change ΔW after t time’s training is ΔW =

∫0

t

ΔW (t )dt =

∫0

t+

ΔW+(t )dt +

∫0

t−

ΔW −(t )dt

W= (2)

where ΔW+ and ΔW− are the positive and negative synaptic weight change, respectively. And t+ and t− are the integral times of ΔW+ and ΔW−, respectively. For a fixed frequency of the referenced noise signal and prenoise signal, the second integration can be treated as a constant C0 with a given initial synapse weight W0. The t+ is in positive correlation with the frequency of preinput signal (f in) and can be written as t+ = kfin2 ·t

∫0

(3)

kfin2 t

ΔW+(t )dt +C0

k·fin + fr fn tw3

G HGS +

fr fn tw3 k·fin + fr fn tw3

G LGS (5)

where f r and f n are the frequencies of the reference random signal and prenoise signal, respectively. GHGS and GLGS are the aberrations of conductance of HGS and LGS, respectively. tw is the width of the spike, which is defined as the interval from the start of the leading edge to the end of the trailing edge. The theoretical calculation agrees well with the measured data as shown in Figure 1d. Eq 5 implies that the mean weight of synapses increases with the f in after the training. Detailed information about the derivation of eqs 3−5 is presented in Note S1 of the Supporting Information. SRDP-Based Neural Network for Unsupervised Online Learning of 10 Hand-Written Digits. To demonstrate the feasibility of the proposed SRDP synapse for unsupervised online learning, a single layer, fully connected neural network with 28 × 28 presynaptic neurons, 10 postsynaptic neurons, and 7840 synapses is designed as shown in Figure 2. As the network structure is shown in Figure 2a, the transistor gates at each row are controlled by one presynaptic neuron. The feedback signal from each postsynaptic neuron is applied to the top electrodes of RRAM devices in the same column, either accumulating charge or tuning the synapse weight. There is an internal random signal source to generate the reference random signal for postsynaptic neurons, and it is applied to all the selected (SEL) ports of the presynaptic neurons meanwhile. It is worth noting that there exists competition between all postsynaptic neurons. As long as one postsynaptic neuron fires, all membrane voltages of all the postsynaptic neurons will be cleared to zero. The frequency signal from a whole input image is schematically shown in Figure 2b. The pixel within the digit region, which we define as “pattern pixel”, will send a high-frequency signal with frequency f p = 200 000 Hz. The “background pixel” outside the digit region will send a low-frequency signal with frequency f b = 5000 Hz. Each image from the 10 digits 0−9 will become the input image with the

where k is a constant, which is correlated with the pulse width of the spike and the capacity of the capacitor. Detailed derivation can be found in Note S1 of the Supporting Information. So, eq 2 can be rewritten as ΔW =

k·fin

(4)

The accumulated positive synapse weight increases with the f in as depicted in eq 4, and C0 is a negative constant. Therefore, the direction (potentiation/depression) of the change of synapse weight will depend on f in, which agrees with the definition of SRDP.26−31 If the frequency of the preinput signal is relatively high, the synapse would experience a potentiation process for a long time of training because of the fact that the probability of a “enhanced event” is larger than the probability of a “depression event”. However, the synapse would experience a depression process for a long time of training when the frequency of the preinput signal is relatively low. The analysis is consistent with eq 4, which helps us to better understand the work principle of our proposed electronic synapse. To demonstrate the feasibility of the proposed electronic SRDP synapse, an experiment is conducted with our fabricated RRAM device and a discrete transistor. The high- and low848


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Figure 3. Unsupervised online learning outcome and the fire-properly training principle. (a) A total of 10 hand-written digits in the MNIST data set to be learned by the SRDP neural network. (b) Gradual learning progress of the 10 input digits. (c) The membrane voltages of the postsynaptic neurons with 10 digits held on for 10 μs. The postsynaptic neurons have been reordered. (d) The influence of P and f p on the accuracy defined in the main text as a benchmark variable to evaluate the robustness of the system. (e) The influence of P and f p to the total training time. (f) The influence of P and f p to the total energy consumption on the RRAM synapse crossbar for training. The accuracy, total energy, and training time in the training process in Figure 3b are 99.5%, 70 μJ, and 20 ms, respectively.

same probability and hold for 200 μs. The inputs images are sequentially forwarded to the presynaptic neurons. Here random sampling [43] was used to generate the spike according to the input MNIST images. For each synapse in the crossbar, the initial conductance state has the probability P = 0.55 to be in the HGS. Later, we will simulate the proposed

neural network to show unsupervised learning of 10 handwritten digits. The detailed simulation method and parameters for unsupervised online learning of 10 digits are presented in Note S2 and Figure S3 (Supporting Information) To achieve unsupervised online learning of 10 hand-written digits, we proposed a principle, which we call the fire-properly 849


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Figure 4. CNN-SRDP two-layer neural network for MNIST data set recognition. (a) The circuit diagram of the single-layer convolutional neural network and its connection with the SRDP fully connected network. (b) The final recognition accuracy and the accuracy for each digit, respectively. (c) The influence of the conductance variation on the final accuracy. The accuracy is still above 90% even when the HGS variation reaches 30%. At each conductance level, 52 accuracy points are used to get the average value and the standard variation.

training principle, to find the proper training conditions: when an image appears in the presynaptic neuron, the postsynaptic neuron, which has learned this image, should have the highest probability to fire, namely, the postsynaptic neuron which has not learned one image or has learned any other image should not have the highest probability to fire. This training principle can be described mathematically as follows. During training, assume that postsynaptic neuron 1 should fire and postsynaptic neuron 2 is competing with postsynaptic neuron 1 at this epoch. M1 and M2 are two random variables representing the number of HGS pixels that receive the high-frequency signal for postsynaptic neuron 1 and postsynaptic neuron 2, respectively. Here we only consider HGS pixels that receive the high-frequency signal, because they are of major contribution to the integral current with the same input voltage amplitude. Assuming random variable M = M1 − M2, D is defined as D(P , fp , fn ) = E(M ) − σ(M )

stochastic forgetting. There are very few background pixels in HGS, because the low-frequency signal can still cause a tiny part of the background pixels to be SET. Figure 3 shows the simulated results of unsupervised learning of 10 digits. With the input images of 10 digits in Figure 3a, the gradual learning process of these 10 digits is shown in Figure 3b. The evolution of the mean weight corresponding to each postsynaptic neuron is shown separately in Figure S7 (Supporting Information). The membrane voltages of postsynaptic neurons are test by inputting 10 digits for 10 μs (Figure 3c). The postsynaptic neurons in Figure 3c have been reordered. The influence of these parameters on the accuracy, training time, and total energy consumption of the whole training process are calculated as shown in Figure 3d−f. f p is equal to f n, because the potentiation and depression rate should be relatively similar, or the training will fail. Here, the accuracy is a critical benchmark variable to evaluate the robustness of the system, obtained by training 100 groups of digits 0−9 and calculating the average accuracy. Because we train the system without using the labels, we do not know which postneuron will learn which digit before training. Only for the purpose of demonstration, we define that for each digit, the postneuron that fires most during the training process when inputting one digit learns this digit. So, the criterion for recognition is different for each simulation, namely, the order of the 10 digits to be learned to the 10 postneurons are different. As shown in Figure 3d, P cannot be too small, because the postsynaptic neurons cannot learn digits if they cannot fire. f p cannot be too large, because it will cause the first winner among the postsynaptic neurons to learn too quickly and has no time to RESET the background pixels. Finally, this postsynaptic neuron will always be the winner in the following training process, and more than one digit will be learned into this postsynaptic neuron. As shown in Figure 3e, if the f p and P are small, the integral current is also small. So, the postsynaptic neurons will be less likely to fire, and the training time tends to be large. In Figure 3f, the total energy is determined by both the training time and the power consumption. The total energy consumption is calculated by integrating the current through the RS device and only includes the energy consumption in the crossbar. Because the write current is much larger than read current, the energy consumption mainly comes from weight update. When f p and P are small, the training time is large, but the power consumption is small, because the postsynaptic

(6)

where E means the mathematical expectation, and σ means the standard deviation of a random variable. Postsynaptic neuron 1 should fire. So, the difference of the current integrated by postsynaptic neurons 1 and 2 is the larger, the better. The integrated currents of neurons 1 and 2 are proportional to M1 and M2, respectively. Therefore, the larger D(P, f p, f n) is, the better. Here we used D(P, f p, f n) > 0 to find proper parameters for training. Detailed discussion is presented in Figures S4 and S5 and Note S3 of the Supporting Information. The gradual learning process of a single postsynaptic neuron is shown in Figure 2c−e. More concretely, the evolution of the three internal variables, membrane voltage, TE voltage, and integral current in the learning process during the first 300 μs (complete evolution is in Figure S6 of the Supporting Information), is shown in Figure 2c, from which we can see integral current determines the increasing speed of the membrane voltage. The integral current is the total current that charges the capacitor C. When a SET pulse is sent, the membrane voltage will be cleared to zero. From Figure 2d,e, we can see that the mean weight of the synapses corresponding to the pattern pixels (background pixels) will get close to HGS (LGS), because they have much a larger probability to be SET (RESET) due to the different frequency of preinput signals for different pixels. After training, there are very few synapses corresponding to pattern pixels in LGS because of the 850


ACS Applied Electronic Materials neurons rarely fire. So, the total energy under different conditions are roughly in the same order of magnitude. Recognition of MNIST Data Set with CNN-SRDP TwoLayer Network. We put a single-layer binary CNN in front of the SRDP network to further improve its learning capacity as well as to give an example of the further usage of the SRDP network. The schematic of this two-layer network is shown in Figure 4a. First, the original input images are fed to the convolutional layer to get the unique feature maps. Then, the values in the feature maps are conveyed to the converters and mapped to different frequency signals to train the following SRDP network online. Here, the convolutional layer is a filter to extract the features of the input images.44,45 It is composed of different kernels to conduct convolution computation with the input images to get the feature maps. The number and size of the kernels directly influence the feature map size and final accuracy; here 10 kernels with size 9 × 9 are utilized based on the simulated optimization. Inspired by the concept of transfer learning in software,46 we think the convolutional kernel itself is a universal feature extractor regardless of which data are used for training. So, the kernels used here are trained with the CIFAR-1047 data set to avoid the usage of the labels in the MNIST data set. Then, the 10 kernels are quantified to three values, 1, 0, −1, and written to the crossbar with two RRAM devices representing one kernel value to obtain the negative value. The converter in Figure 4a is to conduct a pooling operation to squeeze the feature map size and an activation operation.45 A detailed simulation method of the convolution layer and the concrete circuit diagram of the converter are shown in Figure S8 and Note S4 (Supporting Information). The quantified 10 kernels are in Figure S9 (Supporting Information). The system is trained with 60 000 images without using the labels in the training set before recognizing a separate testing set with 10 000 images. The average recognition accuracy is 92%, and the accuracy of each digit is drawn in Figure 4b, separately. The lowest and highest accuracy of different digits are about 98 and 85%, respectively. For the purpose of benchmark, we also train the same scale (784−1000−10) optimized neural network with the widely used BP algorithm and obtained 56% accuracy considering the extracted device variation. This outcome further proves the advantage of our proposed SRDP neural network. Detailed settings about the benchmark simulation are in Figure S10 and Note S5 (Supporting Information). Figure 4c shows the impact of the conductance variation on the final accuracy. We can see that LGS variation has nearly no influence on the accuracy, because synapses in LGS contribute little to the integral current in the training and recognition process. The accuracy is still above 90% even when the variation of HGS reaches 30%. The CNNSRDP neural network can achieve 92% accuracy with 20% variation of HGS and 70% variation of LGS, which is the maximum variation extracted from our device characterization. The fully connected layer with SRDP is suitable for the next layer of CNN, because the natural gradual learning characteristic will allow one postsynaptic neuron to learn different features from different versions of training images from the same digit. So, when recognizing each version of the image from the same digit, this image will match at least part of its features to avoid the wrong classification.

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CONCLUSION

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METHODS

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ASSOCIATED CONTENT

In summary, a novel neural network with SRDP, based on a binary RRAM device, capable of unsupervised learning, is proposed. Furthermore, a CNN-SRDP two-layer neural network is proposed as an example to classify an MNIST data set without using labels with about 92% accuracy. Future studies, targeted at optimizing the peripheral circuit and fully implementing the system in a real circuit, should pave the way for a more energy and time efficient neural network. Continued optimization of system and device performance may even make it possible to overcome the “von Neumann bottleneck” and establish a neuromorphic computer with parallel computation, low power consumption, and small overhead, making it easy to be reconfigured to deal with a cognitive task.

HfOx RRAM-Device Fabrication. First, a 20 nm Ti adhesion layer and a 100 nm Pt bottom electrode were prepared on a 4 in. silicon substrate by electron beam evaporation. Then, AlOx was deposited in three layers by using ALD at 300 °C. Next is the deposition of three layers HfOx by using ALD at 300 °C. The processes were repeated for 10 times, so the total thickness of the AlOx layer and HfOx layer are 3 and 2 nm, respectively. After reactive sputtering was used to deposit a 40 nm TiN top electrode in high vacuum and pattern with lithography, dry etching was performed to form the square-shape devices. Finally, postmetal dielectrics of plasma enhanced chemical vapor deposition (PECVD) Si3N4/SiO2 and Al metallization (100 nm) were used to complete the device fabrication. SRDP Experimental Settings. The experiment setup is composed of an Agilent 81160 arbitrary pulse generator, an Agilent B1500 semiconductor analyzer, and an Agilent 9104A oscilloscope. The model number of the discrete transistor is SD214DE. The frequency signal is generated by an arbitrary pulse generator, applied to the transistor gate, and held for 2 ms for each experiment. The opening gate voltage is 2 V. The RESET voltage is −2 V, and the SET voltage is 1.6 V considering the on-state resistance of the transistor. The pulse width remains 1 μs throughout the experiment. The constant voltage Vs is chosen as −0.01 V so that we can get a positive membrane voltage considering the reverse integrator. The threshold voltage is 2 V. The frequency of the prenoise signal is fixed at 150 000 Hz. The reference random signal has the fixed frequency of 90 000 Hz. The prenoise signal and reference random signal are generated by the Monte Carlo method. The integral resistance R is 20 kΩ. The integral capacity C is 2.25 nF.

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsaelm.9b00011. Theoretical analysis of the frequency-dependence of synapse (Note S1), RRAM-device structure and characterization (Figure S1), Id−Vg curve of transistor (Figure S2, Table S1), simulation method and parameters for unsupervised learning (Figure S3, Note S2), details about the fire-properly training principle (Table S2, Note S3, Figures S4 and S5), evolution of the membrane voltage, integral current, and TE voltage (Figure S6), evolution of the mean weight for the 10 postsynaptic neurons (Figure S7), and binary RRAMdevice-based fully connected network with BP algorithm (Notes S4 and S5, Figures S8−10) (PDF) 851


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AUTHOR INFORMATION

Corresponding Authors

*E-mail: [email protected]. (P.H.) *E-mail: [email protected]. (J.K.) ORCID

Peng Huang: 0000-0003-3280-0099 Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS This work was supported in part by the NSFC (61421005, 61604005, and 61334007). REFERENCES

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