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A Symmetric Tunnel Field-Effect Transistor Based on MoS2/ Black Phosphorus/MoS2 Nanolayered Heterostructures Xixi Jiang, Xinyao Shi, Min Zhang, Yarong Wang, Zhenghao Gu, Lin Chen, Hao Zhu, Kai Zhang, Qing-Qing Sun, and David Wei Zhang ACS Appl. Nano Mater., Just Accepted Manuscript • DOI: 10.1021/acsanm.9b01193 • Publication Date (Web): 25 Jul 2019 Downloaded from pubs.acs.org on July 27, 2019

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A Symmetric Tunnel Field-Effect Transistor Based on MoS2/Black Phosphorus/MoS2 Nanolayered Heterostructures Xixi Jiang1†, Xinyao Shi2†, Min Zhang1, Yarong Wang1, Zhenghao Gu1, Lin Chen1, Hao Zhu1*, Kai Zhang2*, Qingqing Sun1*, David Wei Zhang1 1

State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University,

Shanghai, 200433, China 2

i-Lab, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences, Suzhou,

215123, China

KEYWORDS: tunnel field-effect transistor; MoS2; black phosphorus; heterojunction; subthreshold slope

ABSTRACT: The fast-developing information technology has imposed urgent need for effective solutions to overcome the increasing power density in further scaled electronic devices and systems. Tunnel field-effect transistor (TFET) built with two-dimensional (2D) semiconductors has been widely studied due to its steep-slope switching capability with ultra-thin channel. In this work, a symmetric TFET has been fabricated using the MoS2/black phosphorus/MoS2 heterostructure as the channel material. The TFET device exhibits bidirectional current flow


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which is distinguished from the conventional asymmetric TFET geometry. Upon the application of top gate structure, the devices show sharp turn-on behavior which is originated from the transport properties based on the band-to-band tunneling (BTBT) mechanism. By engineering the top gate materials, a subthermionic subthreshold slope (SS) below 60 mV/dec at room temperature has been achieved, offering a new pathway to lower the power supply and power density in future integrated circuits based on novel 2D materials.

INTRODUCTION There have been increasing needs for the fast-speed and low-power nanoelectronic devices along with the continuous complementary metal-oxide-semiconductor (CMOS) scaling. The device capability to address the issues including heat dissipation and power consumption is critical to maintain the pace predicted by the Moore’s Law.1 Although various field-effect transistor (FET) device geometry and materials have been proposed, studied and even mass-produced including FinFET structure, alternative materials like GeSi and III-V compounds, and fully depleted silicon-on-insulator (FDSOI) configuration, not all the strategies to improve the operation speed and lower the operation voltage have been fully explored.2 Tunnel field-effect transistor (TFET) has been suggested as a promising candidate in the effort to achieve faster switching with suppressed power consumption.3,4 The conduction carriers in a TFET are transported through the band-to-band tunneling (BTBT) process rather than the thermal injection in conventional MOSFETs enabling steeper subthreshold slope (SS) below the 60 mV/dec limit at room temperature.5,6 Therefore, the integration of TFET technique in leading-edge MOSFETs is very attractive since it combines the advantages afforded by the novel quantum mechanical tunneling


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mechanism with the vast infrastructure of advanced semiconductor technology. It is expected that TFETs based on two-dimensional (2D) ultra-thin films or one-dimensional (1D) nanowires can achieve a power consumption ~100 times lower than that of conventional MOSFETs.7 In traditional Si-based planar transistors, the current leakage can occur in a depth of ~5 nm below the surface extending into the bulk. On the other hand, further shrinking the Si channel film thickness will lead to deteriorated semiconductor properties in Si. So far, 2D materials such as graphene8,9, transition metal dichalcogenides (TMDCs)10,11 and black phosphorus (BP)12,13 have attracted great attention due to their intriguing material properties even with one atomic layer thickness.14 Besides, their easily modulated electronic properties, high current densities and clean surfaces are also advantageous to be integrated in transistors for better performance.15,16 Integrating 2D materials as the active channel in TFET is very promising because the heterojunctions can be formed by simply stacking the 2D semiconductors through van der Waals interactions. In addition, the ultra-thin channel can also significantly improve the electrostatic gate control enhancing the conduction in the channel for better driving capability which is actually the bottleneck for the practical application of TFET technology. Till now, there have been reports on both theoretical and experimental studies on the 2D material-based TFET devices. For example, Britnell has reported the resonant tunneling of Dirac fermions through the barrier of a boron nitride thin layer sandwiched between graphene electrodes.17 However, the On/Off current ratio of the TFET device was limited due to the absence of bandgap in graphene. Sarkar et al. have demonstrated a TFET using p-type Ge (highly doped) as the source and n-type MoS2 as the channel to achieve an average SS of 31.1 mV/dec at room temperature.18 Yan et al. have demonstrated 2D-2D tunneling in a BP/SnSe2 heterostructure without electrical gating that showed BTBT-induced negative differential resistance (NDR) at room temperature.19


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Nevertheless, the reported TFET devices built on 2D semiconductors are mostly focusing on gated asymmetric p-n or p-i-n diodes in which the current flows in only one direction. Such intrinsic disadvantage will lead to additional and complicated circuit design occupying extra chip floor space. In this work, we developed a TFET device with symmetric MoS2/BP/MoS2 n-p-n heterostructure. Bidirectional current flow can be realized with a BTBT process between the MoS2 region and the BP region. As compared with the reference MoS2 FET device, the symmetric TFET device exhibited significantly improved switching characteristics with minimum SS value of 58.4 mV/dec at room temperature by utilizing poly (ethylene oxide) (PEO) and lithium perchlorate (LiClO4) as the top gate dielectric. Such symmetric TFET integrating 2D materials has paved promising ways towards ultra-low-power device applications as well as system-level logic and memory circuit implementation.

RESULTS AND DISCUSSION The fabrication process (see Experimental Methods for details) for the symmetric TFET is shown in Figure 1a. The schematic structure of the symmetric TFET is shown in Figure 1b, with the MoS2 and BP regions formed by mechanical exfoliation from high-quality crystal bulk materials. The X-ray diffraction (XRD) pattern obtained from the synthesized bulk BP crystals indicates high crystallinity and purity (Figure S1). The TFET channel consists of two thin MoS2 flakes (2-3 nm) and one thick BP flake (60-70 nm) and dual gate geometry has been applied for better electrostatic gate control. Such combination of the p-type semiconducting BP flake and the MoS2 flakes showing natural n-type characteristic forms a small tunneling barrier width enabling


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efficient carrier tunneling.20,21 BP was selected as the p-type semiconductor in the n-p-n heterojunction because it has a lower electron affinity (EA) and smaller bandgap as compared to other 2D materials. MoS2 was selected as the n-type semiconductor in the channel considering its higher EA as compared to the other widely-explored TMDCs.18 The EA, bandgap and work function of bulk BP crystal is 4.10, 0.3 and 5.0 eV, respectively (Figure 1c), according to the results of ultraviolet photoelectron spectroscopy (UPS) measurement shown in Figure 1d and Fourier transform infrared (FTIR) absorption spectroscopy measurement shown in Figure 1e. The EA, bandgap and work function of MoS2 thin film is obtained by the UPS (Figure 1f) and photoluminescence (PL) spectra measurement (Figure 1g), and were found to be 4.30, 1.82 and 4.5 eV, respectively. The band edge position was calculated according to our previous work.22 The work function of BP and MoS2 were extracted from the UPS spectra by subtracting the binding energies of the secondary electron cut-offs from the excitation energy. The energy difference between EVB and EF was extracted from the low binding energy tails (EVB and EF are the valance band maximum and Fermi energy, respectively). The EA values were calculated by EA= EVB+ Eg, where Eg is the optical band gaps. Thus, MoS2/BP/MoS2 forms a symmetric heterojunction with low tunneling barrier heights. This provides solid basis for effective and efficient carrier tunneling through the barriers with low operation voltages. It is also worth to mention that dual gate structure used in our TFET device is favorable in manipulating and improving the device performance. This is because the electrical characteristics such as the type of electric conduction and switching characteristics of the transistor can be evaluated through the back gate while the top gate can be used to achieve a higher electron concentration in MoS2 which is critical to obtain a small SS in the symmetric TFET. Figure 1h and 1i schematically illustrate the band diagrams of the n-p-p heterojunction demonstrating the


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operation mechanism of the symmetric TFET in both Off and the On state. The source/drain electrodes are in direct contact to the MoS2 flakes. By applying positive (with respect to the source) voltage to the drain (the MoS2 on the right), the electrons are driven from the left MoS2 to the right MoS2. Such transport is modulated by the gate voltage to switch the device between On and Off states. Generally, gate modulation mainly works on the left and the right MoS 2 to shift their Fermi level. For example, in the Off state, the Fermi level of MoS2 is shifted downward to the mid-gap, as shown in Figure 1h. When the Fermi level of BP falls in the band gap of MoS2, only electrons above the conduction band of the left MoS2 are thermally injected into the BP and then transported to the right MoS2 without tunneling, leading to ultra-low current due to the limited number of available electrons with high energies. With increasing gate voltage, the Fermi level of MoS2 is shifted towards the conduction band edge and is close to the Fermi level of BP generating much thinner barrier in the heterojunction, as shown in Figure 1i. Then, the electrons in the conduction band of the left MoS2 tunnel to the valence band of BP and the right MoS2 by a small positive drain voltage, switching the device to On-state. By exchanging the source and drain connection, same tunneling behavior has be observed as well (shown in Figure 1j and 1k) since the two MoS2 flake thickness are quite close to each other which means no significant difference in the band structure. The symmetric TFET operation is based on the BTBT mechanism enabling steep-slope switching with subthermionic SS below 60 mV/dec. Figure 2a shows an optical image of the symmetric TFET fabricated by stacking two MoS2 flakes and a BP flake with a dry-transfer technique. The left MoS2, BP and the right MoS2 flakes are well aligned as indicated by the regions marked with green, red and blue dashed lines, respectively. Raman spectra of the MoS2, BP flakes and the heterojunction are shown in Figure 2b. The Raman peaks at ~383 and ~408 cm−1 are ascribed to the E2g1 and A1g phonon modes of


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MoS2, respectively. The peaks observed at ~361, ~439 and ~466 cm−1 correspond to the Ag1, B2g, and Ag2 phonon modes of BP, respectively. The Raman modes detected from the overlapping regions of the stacked MoS2/BP and BP/ MoS2 layers suggest that two strain-free heterojunctions with van der Waals interactions have been formed.23 Figure 2c shows the atomic force microscopy (AFM) image of the MoS2/BP/MoS2 heterojunction. The thickness of the structure is shown in Figure 2d which was measured along the direction indicated in Figure 2c. The thickness of the left MoS2, BP and the right MoS2 flakes were found to be 2.9, 66 and 2.4 nm, respectively. Next, we characterized the electrical performance of the symmetric TFET device. In this work, all the electrical measurements were performed at room temperature in ambient atmosphere. We first fabricated individual back-gate MoS2 FET (Figure 3a and 3b) and back-gate BP FET (Figure S2) devices in order to examine the physical property of the exfoliated MoS2 and BP flakes. The MoS2 back-gate FET showed a clear n-FET behavior. As shown in Figure 3a, the linear dependence of drain current (Id) on drain voltage (Vd) at low voltage level indicated ohmic Ti contact to MoS2 at the source and drain. The transfer characteristics of the MoS2 back-gate FET is shown in Figure 3b with clear Off state and On/Off current ratio of more than 106. The large SS value of 1.26 V/dec is largely due to the relatively thick (90 nm) SiO 2 back-gate dielectric leading to poor gate control and slow turn-on behavior. On the other hand, the Id versus Vg (gate voltage) transfer characteristics of the BP FET device indicates negligible gate dependence (Figure S2b), which is in accordance with the fact that the Fermi level of the thick BP lies far below the valence band maximum (Vbm) as illustrated in Figure 1g. Therefore, the BP used in this work can be deemed as a highly-doped p-type semiconductor.


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By integrating the n-type MoS2 and p-type BP flakes to fabricate a back-gate n-p-n symmetric TFET device, faster switching performance can be expected. As shown in Figure 3c, the linear Id-Vd curves also indicated ohmic contact without significant charge injection barrier at source/drain which can enhance drive capability of the device with higher On-state current. From the transfer characteristics of the TFET shown in Figure 3d, smaller SS (0.74 V/dec) and Off-state current (~10-14A) compared to the MoS2 FET have been obtained which are the two significant remarks of a typical TFET. It should be noted that there is a sudden drop in Id when Vbg is -15 V which is because of the sudden drop in gate leakage current (Ig) at around -15 V Vbg, as shown in Figure S3. As described above, the charge carriers in the TFET are transferred between different energy bands by interband tunneling instead of thermal injection. Nevertheless, the SS of the back-gate TFET is still much higher than the 60 mV/dec Boltzmann limit at room temperature highlighting the necessity of device engineering by shrinking the gate dielectric thickness to enhance the gate control. However, the relatively thick gate dielectric in the back-gate geometry is required for the mechanical exfoliation to provide sufficient optical contrast between the flakes and the substrate. Therefore, top-gate geometry involving the deposition of high-quality and ultra-thin solid-state high-k dielectric film on the surface of 2D semiconductors has been extensively studied in recent years.24 Due to the absence of dangling bonds on the surface of the layered 2D materials, the deposition of ultra-thin dielectric by using techniques such as atomic layer deposition (ALD) is quite difficult. Island-like film morphology or even physical damage to the surface 2D materials can be introduced during the deposition. Thus, we have utilized the PEO and LiClO4 solid polymer electrolyte layer as the gate dielectric in this work to form a top gate geometry (see Experimental Methods for details). Such polymer electrolyte layer can result in a large gate


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capacitance due to the formation of an electrical double layer.25,26 The schematic and optical microscope images of the top-gate TFET are shown in Figure 4a and 4b, respectively We defined a parallel top gate for the device which was deposited simultaneously with S/D electrodes on the SiO2/Si substrate. The Id-Vtg transfer characteristic of the top-gate device is shown in Figure 4c, a significantly smaller SS of 58.4 mV/dec has been obtained over a current range from ~10-10~10-8 A. A bidirectional current flow at the same level has also been observed (Figure S4) by switching the source and drain electrodes. Compared to the top-gate MoS2 FET fabricated using similar method showing SS of 76.3 mV/dec (Figure S5), the symmetric TFET based on the MoS2/BP/MoS2 heterojunction clearly exhibited a steeper switching behavior. The Id still shows a linear dependence on Vd at a low voltage level similar to the above result obtained from the back-gate MoS2 FET and TFET indicating ohmic contact S/D (Figure 4c, inset). The output characteristics (Id vs. Vd) of the device are shown in Figure 4d with clear linear and saturation region indicating improved gate control over the channel with suppressed short-channel effects. The sharp increase of Id in the linear region also suggest small S/D contact resistance. It is worth to mention here that the top gate leakage is high which might be due to the unstable electrical property of the polymer dielectric (Figure S6). This results in the higher Off-state current in the top-gate TFET as compared with the back-gate devices with SiO2 as dielectric. On the other hand, the polymer dielectric with poor insulating performance can also degrade the SS performance. This means that the intrinsic switching speed of the TFET based on the symmetric MoS2/BP/MoS2 is much faster than the exhibited 58.4 mV/dec shown here which was only dampened by the gate dielectric quality. Further engineering on the structure of the top-gate stack to suppress the leakage current as well as minimizing the effective dielectric thickness can


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be anticipated to achieve lower Off-state current and even smaller SS over a larger current range in the symmetric TFET. Nevertheless, the electrical performance achieved in our symmetric TFET with MoS2/BP/MoS2 heterojunction is still impressive as compared with other reported TFET devices involving junctions of low-dimensional materials (Table S1). CONCLUSIONS In summary, we have developed a symmetric TFET using a MoS2/BP/MoS2 heterostructure. The energy band alignment of the heterojunction has been analyzed which can enable the interband tunneling for the charge carriers under proper electric field effect. As compared with the conventional FET devices, the TFET has exhibited steeper switching behavior and lower Off-state current. A subthermionic SS of 58.4 mV/dec at room temperature has been obtained by building the top-gate structure with polymer electrolyte dielectric. Different from the traditional asymmetric TFET devices, our symmetric TFET based on 2D semiconductors allows for bidirectional current flow while maintaining good electrical performance. Although further device and material engineering is required to improve the leakage, our device concept and structure has paved an attractive pathway for the fast-speed and low-power nanoelectronic device and system-level applications. EXPERIMENTAL METHODS Materials: BP were synthesized by an improved mineralizer-assisted chemical vapor transport (CVT) method using tin tetraiodide (10 mg, Aladdin, 99.99%), tin (20 mg, Aladdin, 99.99%) and red phosphorus (500 mg, Alfa Aesar, 99.999%) as source materials.27 These initial materials were sequentially transferred into a quartz tube and sealed by a Partulab device (MRVS-1002) under 10-3 Pa. The sealed tube was then placed at the heating zone in a quartz tube furnace. The


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representative growth procedure was set as following: First, the furnace was slowly heated from room temperature to 750 °C and maintained for 2 hours. Then, the furnace was cooled down to 500 °C and kept for at least 4 hours to promote the crystal growth. Finally, the furnace was cooled down to room temperature with a rate of 1 °C/min. After the growth procedure, large-sized BP crystals with metallic luster could be found at the cold end of the quartz tube. The polymer electrolyte (PE) is formed by mixing poly(ethylene oxide) (PEO) and lithium perchlorate (LiClO4) in 8:1 ratio in deionized water. Device Fabrication: Firstly, the MoS2 and BP flakes were mechanically exfoliated from the bulk crystals (the bulk MoS2 was commercially available from SPI Supplies). onto the heavily doped silicon wafer covered with 285 nm SiO2. The BP flakes with 60-70 nm thickness and MoS2 flakes with 2-3 nm thickness and proper lateral size were selected for device fabrication. Then, a dry-transfer technique was employed to fabricate the MoS2/BP/MoS2 structure onto the heavily doped silicon wafer covered with 90 nm SiO2. Subsequently, the contact electrodes including the source, drain and side gate were patterned by standard electron beam lithography. A layer of 10/70 nm Ti/Pt was then deposited by sputtering followed by lift-off process forming the metal contacts. In the last step, the device was coated with a layer of polymer electrolyte dielectric by drop-casting PEO:LiClO4 and baked at 90 ℃ for 10 min to drive off the remaining solvent. Characterization: The electrical measurements were carried out using an Agilent B1500A semiconductor analyzer in the ambient atmosphere. The UPS measurements were performed with an AXIS-ULTRA DLD-600W instrument using a He-gas discharge lamp (He 1α at 21.22 eV). The FTIR measurement was performed with Fourier Infrared Spectrometer FTIR-1500. The steady-state photoluminescence and Raman spectroscopy characterizations were carried out with


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LabRAM HR800 (Horiba Jobin Yvon) with the excitation wavelength of 532 nm. The AFM images were processed by WSxM 5.0 Develop 8.1.

ASSOCIATED CONTENT Supporting Information The Supporting Information is available free of charge on the ACS Publications website. The detailed comparison between the symmetric TFET in this work and other reported TFET devices, XRD spectrum of the synthesized BP crystal, structure and performance of the fabricated BP back-gate FET device, the back-gate leakage current, the transfer curve by switching the source and drain, top-gate MoS2 FET device, and top-gate leakage current characteristic. AUTHOR INFORMATION Corresponding Author *E-mail: [email protected] (H.Z.) *E-mail: [email protected] (K.Z.) *E-mail: [email protected] (Q.S.)

Funding Sources H.Z. acknowledges the funding support by the Shanghai Municipal Science and Technology Commission (18JC1410300), Q.S. is thankful for the support from the National Natural Science Foundation of China (61522404), L.C. acknowledges the support from the National Natural Science Foundation of China (61704030) and 02 State Key Project (2017ZX02315005).


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Diode. ACS Nano 2014, 8, 8292-8299. (22) Jiang, X.; Xiong, Y.; Zhang, Z.; Rong, Y.; Mei, A.; Tian, C.; Zhang, J.; Zhang, Y.; Jin, Y.; Han, H.; Liu, Q., Efficient Hole-Conductor-Free Printable Mesoscopic Perovskite Solar Cells Based on SnO2 Compact Layer. Electrochim. Acta 2018, 263, 134-139. (23) Lee, G.; Pearton, S. J.; Ren, F.; Kim, J., Two-Dimensionally Layered p-Black Phosphorus/n-MoS2/p-Black Phosphorus Heterojunctions. ACS Appl. Mater. Interfaces 2018, 10, 10347-10352. (24) Xu, J.; Chen, L.; Dai, Y.; Cao, Q.; Sun, Q.; Ding, S.-J.; Zhu, H.; Zhang, D. W., A Two-Dimensional Semiconductor Transistor with Boosted Gate Control and Sensing Ability. Sci. Adv. 2017, 3, e1602246. (25) Lin, M.-W.; Liu, L.; Lan, Q.; Tan, X.; Dhindsa, K. S.; Zeng, P.; Naik, V. M.; Cheng, M. M.-C.; Zhou, Z., Mobility Enhancement and Highly Efficient Gating of Monolayer MoS2 Transistors with Polymer Electrolyte. J. Phys. D: Appl. Phys. 2012, 45, 345102. (26) Carrad, D. J.; Burke, A. M.; Lyttleton, R. W.; Joyce, H. J.; Tan, H. H.; Jagadish, C.; Storm, K.; Linke, H.; Samuelson, L.; Micolich, A. P., Electron-Beam Patterning of Polymer Electrolyte Films to Make Multiple Nanoscale Gates for Nanowire Transistors. Nano Lett. 2014, 14, 94-100. (27) Xu, Y.; Yuan, J.; Zhang, K.; Hou, Y.; Sun, Q.; Yao, Y.; Li, S.; Bao, Q.; Zhang, H.; Zhang, Y., Field-Induced n-Doping of Black Phosphorus for CMOS Compatible 2D Logic Electronics with High Electron Mobility. Adv. Funct. Mater. 2017, 27, 1702211.


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Figure 1. (a) Schematic diagram of the fabrication process for the symmetric TFET. (b) Schematic structure of the symmetric TFET. (c) Energy band alignment of MoS2/BP/MoS2. (d) UPS and (e) FTIR spectra of bulk BP. (f) UPS and (g) PL spectra of MoS2 thin film. Band diagrams explaining the carrier transport in the device under (h) Off-state and (i) On state. Band diagrams explaining the carrier transport with exchanged source and drain connection under (j) Off-state and (k) On state.


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Figure 2. (a) Optical image of a symmetric TFET on the SiO2/P+-Si substrate. (b) Raman spectra of the left MoS2, BP, right MoS2 and the two overlapped stack regions. (c) AFM image of the MoS2/BP/MoS2 flakes. (d) AFM height profile of the MoS2/BP/MoS2 flakes along the dashed line in (c).


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Figure 3. (a) Id-Vd curves of the reference back-gate MoS2 FET by sweeping Vd from -40 to 40 mV under different Vbg. (b) Id-Vbg transfer curves in log scale of the reference back-gate MoS2 FET with Vd ranging from 100 to 600 mV. (c) Id-Vd curves swept from -40 to 40 mV under different Vbg of the back-gate TFET. (d) Id-Vbg transfer curves in log scale of the back-gate TFET with Vd ranging from 100 to 600 mV.


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Figure 4. (a) Schematic of the top-gate TFET. (b) Optical microscope image of the top-gate TFET. The circled region represents the solid polymer electrolyte. (c) Id-Vtg transfer curves in log scale with Vd =100 mV. Insert: Id-Vd curves swept from -0.4 to 0.4 V under different Vtg. (d) Id-Vd curves with Vtg ranging from 0.4 to1.2 V.


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