Branched Segments in Polymer Gate Dielectric as Intrinsic Charge

Article pubs.acs.org/JPCC

Branched Segments in Polymer Gate Dielectric as Intrinsic Charge Trap Sites in Organic Transistors Junghwi Lee,† Hyun Ho Choi,§ Namwoo Park,† Honggi Min,† Singu Han,† Heejeong Jeong,† Inseok Song,† Se Hyun Kim,‡ and Hwa Sung Lee*,† †

Department of Chemical & Biological Engineering, Hanbat National University, Daejeon 305-719, Korea Department of Nano, Medical and Polymer Materials, Yeungnam University, Gyeongsan 712-749, Korea § Department of Physics and Astronomy, Rutgers University, Piscataway, New Jersey 08854, United States ‡

S Supporting Information *

ABSTRACT: Charge traps in polymer gate dielectrics determine the electrical stability of organic field-effect transistors (OFETs), and polar alkoxy groups are wellknown extrinsic charge traps. However, the actual location of intrinsic charge traps in nonpolar polymer gate dielectrics has been poorly understood yet. Here, we demonstrate that the skeletal structure of polymer chain plays an important role in determining the electrical stability. To verify it, we prepared linear and branched polystyrene (l-PS and b-PS) and blended them, in which branched segments provide much larger free volume than the other segments. The current-insulating performance and field-effect mobility increased with decease of b-PS portion. In particular, the bias-stress stability was remarkably varied according to the change of b-PS portion even though all measurements excluded reactive components such as oxygen and water; the increase of b-PS resulted in time-dependent decay of mobility and threshold voltage under bias stress. This indicates that the branched segments in b-PS provide intrinsic and metastable charge trap sites. Our result suggests that the skeletal structure of polymeric chains in gate dielectric is one of the important factors affecting intrinsic long-term operational stability of OFET devices.

1. INTRODUCTION

charge traps in nonpolar polymer gate dielectrics has been poorly understood yet. Recent studies have demonstrated that a part of free volumes in polymer film has enough space to allow the immigration of oxygen or water molecules, which can increase the polarity of gate dielectric and/or can work as extrinsic trap sites.14,15,19,32−37 Under a bias stress, i.e., when constant gate bias is continuously applied for a long time, the applied gate bias could facilitate diffusion of polar molecules like water into the polymer, thereby dramatically reducing the electrical biasstress stability and OFET device performance. These studies revealed that the free volume does not provide charge trap sites if the OFET device performances were measured under vacuum or under dried inert gas conditions. However, the contributions of free volume in polymer to the formation of intrinsic charge traps cannot be ruled out based on polymer physics arguments or the measured charge trapping behaviors reported previously.11,16,38−42 The free volume is closely related to the physical properties of a polymer, including the glass transition temperature and viscoelasticity. A large free

Organic field-effect transistors (OFETs) have received much attention as switching elements for use in flexible electronics, and the carrier mobilities of them are comparable to those of amorphous silicon FETs nowadays. 1−7 The successive commercialization of them for flexible electronics relies on the development of flexible gate dielectrics and substrates, and the polymer films are one of the most suitable candidates.8−10 However, the use of polymer layers as stable gate dielectric needs to solve several problems: poor current insulation,11−13 operational instability,14,15 and degradation by chemicals.8,16,17 Among them, the most pressing issue is the presence of charge traps in polymer gate dielectrics, which degrades device performance such as field-effect mobility, on/off current ratio, threshold voltage, or hysteresis.14,18−23 To investigate the charge traps in polymer gate dielectrics, a number of factors related to polymer properties have been systematically controlled such as surface energy,24−26 dipole moment,26−28 chemical functionality,18,26,29 and molecular weight.14,30,31 As a result, polar alkoxy moieties in polymeric chain are revealed as extrinsic charge trap sites by inducing slow polarization or attracting water vapors. However, the actual location of intrinsic © 2015 American Chemical Society

Received: February 13, 2015 Published: March 18, 2015 7670

DOI: 10.1021/acs.jpcc.5b01522 J. Phys. Chem. C 2015, 119, 7670−7677

Article

The Journal of Physical Chemistry C

Figure 1. Schematic illustration of the top-contact bottom-gate pentacene FETs and the chemical structures of l-PS and b-PS used in this study.

0.2 Å/s and a substrate temperature of 30 °C under a base pressure of approximately 10−7 Torr. The devices were completed by evaporating gold through a shadow mask to define the source and drain contacts on the pentacene film, with channel lengths and widths of 200 and 1000 mm, respectively. Characterization. The thickness of each PS film on a Si wafer was measured using ellipsometer (M-2000 V, J.A. Woollam Co., Inc.) and alpha-step profilometer (Dektak 150, Veeco). The root-mean-square (rms) roughness was determined using AFM (Digital Instruments Multimode) measurements collected over 2 × 2 μm2 scan areas. Two-dimensional grazing incidence X-ray diffraction (2D GIXD) studies were performed to investigate the crystalline structure of the pentacene films. All X-ray measurements were carried out at the Pohang Accelerator Laboratory (PAL), Korea. The pentacene film morphology was examined using an AFM operated in the tapping mode using Si tips (42 N/m and 320 kHz). The current−voltage characteristics and bias-stress responses of the prepared devices were measured by operating the OFETs under an applied negative gate bias. The source electrode was grounded, and the drain electrode was negatively biased. The changes in the electrical properties under light illumination were measured by illuminating the device with a white beam (26 mW/mm2) during the recovery process. The electrical properties of the devices were measured at room temperature (∼10−4 Torr) using an HP4156A instrument under vacuum conditions to exclude the effects of common reactive components in air, such as oxygen or water.

volume tends to increase the thermal dynamic motion of a polymer chain and decrease density of polymer layer. In general, the current-insulating strength of a polymer gate dielectric can be increased by increasing density of polymer layer; the leakage current increases as the density of polymer decreases. 38,39,42 This implies that the charge carriers preferentially choose void defect or free volume as their transport pathway.40−42 For these reasons, the free volume in polymer gate dielectrics is expected to intrinsically affect charge trapping phenomena in OFETs. In this paper, we demonstrated that the skeletal structure of polymeric chain could significantly affect device performance and most importantly bias-stress stability and that branched segments in nonpolar polymers worked as intrinsic charge trap sites. The density of branched segments was systematically controlled by blending two styrene-based polymers with different chain structure: linear (l-PS) and branched (b-PS). It increased with b-PS/l-PS blend ratio,21,39,43−45 and the spincoated blend films did not exhibited significant phase separation with preserving flat surfaces. We found that the branched segments worked as charge trap sites, reducing fieldeffect mobility and bias-stress stability in the absence of common reactive components in air, such as oxygen or water molecules.

2. EXPERIMENTAL SECTION Materials and Device Fabrication. The OFET devices were fabricated on a substrate consisting of a highly doped ntype Si wafer topped with a thermally grown 100 nm thick oxide layer. The wafer also served as the gate electrode. Prior to treating the SiO2 surface, the wafer was cleaned by exposure to UV/ozone (253.7 nm) for 30 min. The substrate was chemically treated by spin-coating hexamethyldisilazane (HMDS, Aldrich), followed by baking at 120 °C for 1 h, to terminate hydroxyl groups on SiO2 surface. l-PS (Mw = 7.4 kDa, Mw/Mn = 1.09) and b-PS (Mw = 7.6 kDa, Mw/Mn = 1.30), purchased from Polymer Source Inc., were spin-coated onto the SiO2 substrate from chlorobenzene solutions and dried for 48 h in a vacuum oven at 60 °C to remove residual solvent. Because the PS molecular weight has been revealed as a critical parameter determining device performances,14,30,31 we chose lPS and b-PS with a similar molecular weight. All PS gate dielectrics with a variety of blend ratios of l-PS and b-PS were fabricated using the same process. 50 nm thick pentacene (Aldrich Chemical Co., no purification) films were deposited using an organic molecular beam deposition system at a rate of

3. RESULTS AND DISCUSSION We fabricated b-PS/l-PS blend films with various weight ratios: b-PS/l-PS = 0/100 (B0L100), 30/70 (B30L70), 50/50 (B50L50), 70/30 (B70L30), and 100/0 (B100L0). All PS dielectrics were fabricated with a similar thickness of 550 ± 30 nm to exclude the dielectric thickness effect on OFET performances. The rms roughness of polymer layers was found to be 0.22 ± 0.01 nm, implying no significant phase separation of the blend films (Figure S2). It is due to the similar chemical moieties between l-PS and b-PS and the rapid deposition process that did not provide enough time for the phase separation. The OFET and PS structures employed in this study are shown in Figure 1. The capacitances and dielectric constants of gate dielectric layer are summarized in detail in Table 1. 7671


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portion: from ∼10−4 A cm−2 for B0L100 to ∼10−3 A cm−2 for B100L0, under an applied electric field of 1.5 MV cm−1. The sudden current increase was observed between B30L70 and B50L50, and B70L30 and B100L0 films yielded high current density. This tendency implies that the branched segments in bPS work as preferential pathway for charge transport, so reduce the current-insulating performance. Furthermore, there is a possibility for charge carriers to transfer from the accumulated channel as well as the gate electrode to the b-PS/l-PS gate dielectric through the branched segments, only if a single layer of b-PS/l-PS is used as a gate dielectric.46−50 To avoid this problem, therefore, 100 nm thick SiO2 layer was used in a double-layer gate dielectric. To investigate these insulating films as gate dielectric in OFETs, top-contact bottom-gate OFETs were fabricated. Pentacene was selected as an organic semiconductor because it provides an excellent and well-characterized electrical performance, particularly in the context of OFET applications. We used the polymer gate dielectric (thickness: 550 nm) with various b-PS/l-PS ratio coated on 100 nm thick SiO2 layer in the OFET fabrication in order to prevent the leakage current flow from gate to source/drain. The output and transfer characteristics of the devices using PS gate dielectric with various b-PS/l-PS ratio are presented in Figure 3. The devices functioned as well-behaved p-type transistors with characteristics that included a linear regime at small drain voltage (VD) and a saturation regime at VD exceeding the gate voltage (VG).51 The gate leakage currents (IG) were observed under the drain current (ID) of 10−9 A in all cases, indicating that the 100 nm thick SiO2 layer efficiently prevented the charge injection from gate to source/drain. In the output characteristics, the maximum saturation currents decreased as b-PS/l-PS ratio increased. A similar tendency was also observed in field-effect mobility and threshold voltage; as b-PS/l-PS ratio increased

Table 1. Summaries of the Gate Dielectric Capacitances and the Pentacene FET Performances sample

capacitance (nF cm−2)

dielectric constant

B0L100 B30L70 B50L50 B70L30 B100L0

4.22 4.38 4.41 4.58 4.74

2.30 2.37 2.39 2.47 2.54

field-effect mobility (cm2 V−1 s−1) 0.68 0.69 0.55 0.49 0.47

± ± ± ± ±

0.10 0.11 0.08 0.09 0.06

threshold voltage (V) −31.8 −33.8 −36.9 −40.0 −39.6

± ± ± ± ±

1.1 0.8 0.5 1.1 2.8

The current-insulating property of PS gate dielectric was first analyzed as a function of b-PS/l-PS ratio. We electrically measured metal−insulator−metal capacitor using PS films as insulators. The current density−electric field characteristics exhibited that B0L100 film had the strongest insulating property (Figure 2). The current density increased with b-PS

Figure 2. Current density versus electric field characteristics of the gold MIM structures prepared with thin PS dielectric films. The inset shows the MIM structure.

Figure 3. Output (up) and transfer (down) characteristics of pentacene FETs prepared with gate dielectrics formed from 100 nm thick SiO2 and PS layers. Gray lines show gate-leakage currents in transfer curves. Transfer characteristics of each FET were obtained at a fixed VD of −60 V. 7672


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morphologies of the pentacene films deposited onto the PS dielectrics were similar. It was presumably attributed to the similar surface energy and roughness of the b-PS/l-PS gate dielectric regardless of b-PS ratio (Table S1). It was due to the extremely low density of oxygen atoms in a b-PS chain; C:O = 980:1 in B100L0. Figure 5b shows the 2D GIXD results of 10 nm thick pentacene films deposited on the B0L100 and B100L0 samples. The very weak (002) reflection peak marked with white arrows in the B100L0 case was observed, in contrast to the B0L100 case. This indicates that the pentacene film on the B100L0 had slightly higher crystalline order than that on the B0L100. Typically, polycrystalline films with a grain morphology appear to increase the carrier transport efficiency due to the presence of well-ordered crystalline structures and/ or large grain sizes,55,56 inducing the increase of the field-effect mobility. The enhanced crystalline structure of the pentacene on the B100L0, however, is not dominant, and thus it could not significantly affect the field-effect mobility. Furthermore, this higher crystalline structure of the pentacene on the b-PS could not explain the change of bias-stress stability as a function of bPS/l-PS ratio.57,58 Therefore, the aforementioned variance of transfer characteristics as a function of b-PS/l-PS ratio results from changes in the PS gate dielectric properties, not from changes in pentacene film properties. The b-PS, particularly branched segment in b-PS, contains charge trap sites, which prevent charge transport and channel accumulation. This finding, that is, charge traps at branched segments in bPS, was more clearly observed when gate bias stress was applied. We measured the drain current as a function of time under the constant gate and drain bias (VG = −60 V and VD = −5 V, Figure 6a).59 To exclude the effects of oxygen or water present in air, the measurement was performed under a vacuum (∼10−4 Torr). All devices exhibited a decrease in ID as a function of time, indicating that the mobile carriers in the channel region were immobilized by gate bias. We found that the content of b-PS in a gate dielectric strongly determined the electrical stability of the device; the decay of ID(t)/ID(0) intensified as the b-PS content increased. The value of ID after

from 0/100 (B0L100) to 100/0 (B100L0), the average mobility decreased from 0.68 to 0.47 cm2 V−1 s−1 (Figure 4).

Figure 4. Variations in the field-effect mobility (closed symbols) and threshold voltage (open symbols) of pentacene FETs as a function of the b-PS content.

This result indicates that the increase of b-PS portion results in the inferior charge transport. It can be explained qualitatively in terms of the broadening of the density of states due to interface dipolar disorder of CO moieties in the gate dielectric.52,53 Furthermore, the threshold voltage was negatively shifted from −34.8 to −39.6 V, indicating the inferior channel accumulation. Based on the multiple-trapping-and-release (MTR) model that is one of the most suitable charge transport model in organic electronics, it is considered that both shallow and deep traps were generated by increase of b-PS portion.54 One can think that this different device performance is closely related to the molecular ordering/crystalline structure of pentacene layer. However, we found that this variance of FET performances was not originated from the microstructural change of pentacene layer. We conducted AFM and 2D GIXD analysis to investigate the morphology and crystallinity of pentacene layer. Figure 5a shows AFM images of 5 and 10 nm thick pentacene films deposited on B0L100 and B100L0 at the initial film growth stages. As shown in the results, the initial

Figure 5. (a) AFM images at the initial growth stages of 5 and 10 nm thick pentacene films deposited on l-PS (B0L100) and b-PS (B100L0) dielectrics. (b) 2D GIXD patterns of 10 nm thick pentacene films deposited on l-PS (B0L100) and b-PS (B100L0) dielectrics. 7673


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(Figure 7a) or under illumination (Figure 7b) over 30 min. Under bias stress, the consistent tendency among B0L100,

Figure 6. (a) Time-dependent ID decay under a constant bias stress (VG = −60 V and VD = −5 V) under vacuum conditions. (b) Fieldeffect mobility and (c) Vth variations with increasing number of measurements.

application of 2 h bias stress decreased as the b-PS content increased: 0.63 for B0L100, 0.61 for B30L70, 0.48 for B50L50, 0.38 for B70L30, and 0.27 for B100L0. This difference indicates that the branched segments in b-PS chain provide charge traps related to the bias stress effects. Note that the ID decays during the early stages of the bias stress occurred quite abruptly, and their values depended on the b-PS content. The rapid decay that occurred immediately after the device had been turned on suggested that the charge trap sites at the semiconductor/gate dielectric interface predominantly and rapidly interacted with the mobile carriers,20,60,61 disturbed charge transport in the channel region, and hindered the electrical stability of the FET devices. To reveal whether this ID decay is originated from the degradation of carrier mobility and/or negative shift of threshold voltage, we plotted FET mobilities and threshold voltages as a function of the number of transfer measurements collected (Figure 6b,c). As the number of measurement increased, both FET mobility and threshold voltage were changed regardless of b-PS portion; FET mobility continuously decreased, and threshold voltages shifted toward negative values. The amount of mobility degradation and threshold voltage shift was noticeably dependent on b-PS portion in the devices; both FET mobility and threshold voltage were more rapidly changed when the b-PS content increased. Typically, unlike our observation, the bias-stress effect in OFET devices corresponds to the shift of threshold voltages, indicating charge trapping in a deep state. We speculate that the average energy state of charge traps at branched segments in b-PS lies on the borderline between shallow and deep traps or that charge traps are homogeneously distributed from interface to bulk.57,62−65 Note that the electrical stabilities of FET devices under a bias of VG or under repetitive measurements are noticeably dependent on b-PS portion, even in the absence of water or oxygen molecules. Most previous reports have asserted that the presence of water or oxygen molecules captured in the chain ends or in the functional groups of the polymer gate dielectric give rise to device instabilities.14,15,19,32−37 In contrast to these extrinsic charge traps, those at branched segments capture mobile carriers intrinsically. To further understand the charge traps at branched segments in b-PS chain, we conducted electrical measurements under bias stress and recovery processes. Changes in the threshold voltage shift (ΔVth) over time were measured in a device containing B0L100, B50L50, or B100L0 gate dielectric. Bias stress (VG = −60 V and VD = 0 V) was applied in dark for 30 min, and the recovery process (VG = VD = 0 V) was performed in dark

Figure 7. Time-dependent ΔVth for pentacene FETs based on B0L100, B50L50, or B100L0 gate dielectrics under vacuum condition (∼10−4 Torr). A bias stress (VG = −60 V, VD = 0 V) was applied under dark conditions for 30 min, and then a recovery process (VG = VD = 0 V) was performed in (a) dark and under (b) illumination. (c) Schematic diagram of the charge trapping at the branched segments in polymer gate dielectric.

B50L50, and B100L0 based devices was obtained as shown in Figure 6; ΔVth was higher in the B100L0 device than in the B0L100 or B50L50 devices. Under the recovery process, we found two different charge detrapping mechanisms present in all cases, regardless of the b-PS content. First, rapid recovery of Vth occurred within a few minutes right after the devices were exposed to light. This phenomena was not observed when the devices were not exposed to the light, and ΔVth in this stage is independent of b-PS portion. Thus, the charge detrapping in this regime is regarded as evidence for the photoexcitation of trapped charges, especially in organic semiconductors.66−68 Second, slow recovery of Vth occurred subsequently during the later stage of photoillumination in all gate dielectric cases. Under dark conditions, only slow recovery was observed. This slow charge detrapping in the later stages always occurred regardless of photoillumination, at a rate that was also independent of b-PS portion. We speculate that slow charge detrapping in the later stages is related to the presence of other trap sites within the PS gate dielectric and that these trap sites do not associated with b-PS. One interesting point is that the ΔVth differences among B0L100, B50L50, and B100L0 devices after application of a bias stress for 30 min are preserved even 7674



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after a 30 min recovery period under dark or illumination conditions. It indicates that the charge traps at branched segments in b-PS chain have quite deep energy states or place far from pentacene layer, so it is difficult for trapped charges to be detrapped. We surmise that there are two possibilities for the nature of charge traps at branched segments. First, the polar CO groups were possible to trap charge carriers intrinsically. Orgiu et al. reported that the OH group in poly(vinyl alcohol) works as an intrinsic charge trap, resulting in the hysteresis.46 Because CO group is also polar like OH group, it is hard to exclude the possibility of CO group as charge trap sites. However, note that these polar moieties entrap charge carriers more efficiently under the bias stress with the presence of water. Choi et al. reported that the difference of the bias-stress instabilities between the OFETs with H-end-capped PS and COOH-endcapped PS dielectrics remarkably increased when bias stress is applied in humid environment.14 Therefore, we expect that the presence of the CO group could affect the charge trapping behavior in minor because all electrical measuremnts were performed under vacuum (10−4 Torr). Next, free volume around branched segments acts as a charge trap site (Figure 7c). Under bias stress, 1.3−1.8 MV cm−1 of electric field is applied to the PS. This electric field, resulting from the coulomb interaction between charge carriers in channel and gate, might induce the mobile carriers in the channel to diffuse into PS gate dielectric. In this step, charge carriers preferentially choose the branched segments as their migration pathways because free volume is larger around branched segments than around the other segments according to the free volume theory by Artbauer et al.40−42 It is expected that the branched segments located in the channel interface as well as bulk contributed to formation of charge traps; the trapped charges in the channel interface hinder the lateral charge transport by scattering (degradation of mobility), and those in the bulk interrupt gate electric field to reach the channel (negative shift of threshold voltage).

AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected] (H.S.L.). Author Contributions

J.L. and H.H.C. contributed equally. Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS This work was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (NRF2014R1A1A4A01009458).

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REFERENCES

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4. CONCLUSIONS We demonstrate that the polymer branched segments provide intrinsic charge trap sites related to electrical stability. As evidence, we found that the chain skeletal structures present in the polymer gate dielectrics critically affect the FET performance and electrical stability. The styrene-based polymer was used as gate dielectric, and the density of branched segments was systematically controlled by varying the portion of branched polymer. As a result, the current-insulating property and bias-stress stability of pentacene FETs were significantly degraded as the density of branched segments increased. It was attributed to the polar moieties at the branched segments and/ or the free volume around the branched segments, which played a critical role in forming charge trap sites, despite the absence of water or oxygen. The results and conclusions obtained in this study are vital to the design of polymer gate dielectrics for OFETs with enhanced bias-stress stability.

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ASSOCIATED CONTENT

* Supporting Information S

Figures S1 and S2; Table S1. This material is available free of charge via the Internet at http://pubs.acs.org. 7675


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Branched Segments in Polymer Gate Dielectric as Intrinsic Charge

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