Carbon Nanotube Complementary Gigahertz Integrated Circuits and

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Carbon Nanotube Complementary Gigahertz Integrated Circuits and Their Applications on Wireless Sensor Interface Systems Lijun Liu,†,∥ Li Ding,†,∥ Donglai Zhong,† Jie Han,† Shuo Wang,‡ Qinghai Meng,§ Chenguang Qiu,† Xingye Zhang,‡ Lian-Mao Peng,† and Zhiyong Zhang*,† Downloaded via WESTERN SYDNEY UNIV on February 4, 2019 at 02:51:11 (UTC). See https://pubs.acs.org/sharingguidelines for options on how to legitimately share published articles.

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Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China ‡ Key Laboratory of Green Printing, Institute of Chemistry, Chinese Academy of Sciences (ICCAS), Beijing 100190, China § CAS Key Laboratory of Nanosystem and Hierarchical Fabrication, CAS Center for Excellence in Nanoscience, National Center for Nanoscience and Technology, Beijing 100190, China S Supporting Information *

ABSTRACT: Along with ultralow-energy delay products and symmetric complementary polarities, carbon nanotube field-effect transistors (CNT FETs) are expected to be promising building blocks for energy-efficient computing technology. However, the work frequencies of the existing CNTbased complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are far below the requirement (850 MHz) in state-of-art wireless communication applications. In this work, we fabricated deep submicron CMOS FETs with considerably improved performance of n-type CNT FETs and hence significantly promoted the work frequency of CNT CMOS ICs to 1.98 GHz. Based on these high-speed and sensitive voltagecontrolled oscillators, we then presented a wireless sensor interface circuit with working frequency up to 1.5 GHz spectrum. As a preliminary demonstration, an energy-efficient wireless temperature sensing interface system was realized combining a 150 mAh flexible Li-ion battery and a flexible antenna (center frequency of 915 MHz). In general, the CMOS-logic high-speed CNT ICs showed outstanding energy efficiency and thus may potentially advance the application of CNT-based electronics. KEYWORDS: carbon nanotube film, complementary metal-oxide semiconductor, field-effect transistors, voltage-controlled oscillators, sensor interface

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Furthermore, excellent and symmetric CNT CMOS FETs have been achieved due to the symmetric band structure between conduction and valence bands around the Fermi level in CNTs via a doping-free process, which involves fewer procedures than in Si CMOS technology.9 CNT-based CMOS integrated circuits (ICs) have been proved to dissipate much less power and have lower fabrication costs than mainstream Si-based CMOS-logic circuits1−3,6 and are expected to be attractive building blocks for chips in smart sensors and IoT devices. Recently, CNT CMOS electronics have undergone great progress,3,4,10−22 but still faces major challenges to be useful mainly owing to the limited speed or working frequency. By far, the highest frequency of all reported CNT CMOS ICs

ue to an ultrasmall intrinsic capacitance and quasiballistic transport,1−3 carbon nanotubes (CNTs) have been predicted and demonstrated to be promising semiconducting materials for realizing advanced transistors with high performance and low power dissipation.2−8 Very recently, CNT field-effect transistors (FETs) with a 5 nm gate length (Lg) were demonstrated, exhibiting performance and energy dissipation superior to those of state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) FETs and even reaching the quantum limit of a binary switch.3 In particular, CNT FETs presented an energy-delay product that was 1 order of magnitude lower than that of Si CMOS FETs with similar gate lengths and thus offer great potential as building blocks for energy-efficient computing technology,3 which is becoming increasingly important for the emerging smart sensors, Internet-of-Things (IoT), and cloud technologies.7 © XXXX American Chemical Society

Received: December 16, 2018 Accepted: January 29, 2019 Published: January 29, 2019 A

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Figure 1. Characterizations of the CNT CMOS FETs. (a) SEM image of the solution derived CNT film. Inset: Raman spectrum characteristic. (b) Schematic device structure of the top-gated CNT CMOS FETs. (c) False-colored SEM image of a pair of as-fabricated CMOS FETs. For p-FET, Lch/Lg = 350 nm/220 nm and W = 10 μm, and for n-FET, Lch/Lg = 350 nm/220 nm and W = 20 μm. The scale bar denotes 10 μm. Upper: Band diagrams of a Pd-contact p-type FET and a Sc-contact n-type FET in the on-state. (d) Transfer curves and (e) output characteristics of both p-FET (left) with Vgs varying from −3 to 0 V and n-FET (right) with Vgs ranging from 3 to 0 V (step of 0.3 V for both devices). (f and g) Comparisons of Ion/W (f) and gm/W (g) between some of the reported CNT FETs (with current on/off ratio >10) and our CMOS FETs for different values of Lg and Vds.5,10,11,14,15,28−30

In this study, we fabricate the CNT CMOS FETs with considerably improved performance by scaling the dimensions and optimizing the structure and fabrication process based on high-quality CNT film and then promote the CNT CMOS ICs to a record approximately 2 GHz regime. We then present a voltage-to-frequency converter-based quasi-digital sensor interface IC that shows superior low energy dissipation and works in GSM frequency spectrum. Finally, as an example, we demonstrate a preliminary wireless temperature sensing interface system based on our CNT CMOS voltage-controlled oscillators (VCO) on-chip integration with a flexible Li-ion battery and a flexible antenna with center frequency of 915 MHz, which demonstrates the potential applications in far-field wireless communication, such as narrow band (NB) IoT systems.

is still not high enough for far-field wireless communication, which reaches at least GSM spectrum (i.e., 850 MHz or 1.8 GHz).23 Although significant progress has been achieved in terms of the speed of CNT FET-based ICs,10,14,24 the highest working frequency of CNT CMOS ICs (five-stage ring oscillators) is only 282 MHz,10 which is still far outside the GSM spectrum. Five-stage ring oscillators with oscillating frequency of 5.54 GHz have been realized on CNT films, but pure p-FETs rather than CMOS architecture used cannot satisfy the requirement of low power dissipation.14,21 In order to gain maximum performance benefit from CNT FETs and minimize the standby power, systems built on CNT FETs must be realized using complementary logic. On the other hand, the characteristic size (L) of antennas strongly depends on the frequency (f) of the carrier wave in communication systems with a relation of L ∝ 1/f, with a lower carrier wave frequency requiring larger antennas, which are not suitable for integration into a practical system. For example, large antennas with a size of several meters are required to emit a carrier wave with a frequency of 10 MHz. To use antennas with sizes of several centimeters, which are suitable for fabrication on chips, the carrier wave frequency must be at the GHz level. Considering that existing CNT CMOS ICs actual working speed is much lower than 1 GHz,10,11,13 which limits their application in far-field wireless communications, one of the primary tasks is to improve the performance of CNT CMOS FETs and then realize high-performance and low-powerdissipation ICs to process GHz signals.

RESULTS AND DISCUSSION The performance of CNT CMOS transistors is promoted mainly by scaling down the gate length to deep submicrometer region on the basis of using high-quality and high-density CNT film with semiconducting purity of as high as 99.99% (see Figure S1), which is necessary to maintain a high on/off current ratio in these scaled CNT FETs. Specifically, an annealing process at 600 °C is required to clean the CNT film, thus effectively enhance the performance of both n-FETs and p-FETs. The CNT material used in this work is solutionderived CNT network film via a process described in methods. B

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Figure 2. CNT CMOS inverter and CS amplifier. (a) Circuit diagram of a CMOS inverter. (b) Voltage-transfer characteristic (VTC) curve of a fabricated inverter under working voltage Vdd varying from 3.5 to 0.3 V. (c) VTC curves (red) and their mirrors (blue) at Vdd = 3 and 1.5 V. The shadowed “eye” area represents the noise margin of the inverter. (d) Circuit diagram of a CMOS CS amplifier. (e) VTC curves of the CS amplifier under fixed Vdd = 3 V, while different control voltage Vcont varying from 0.8 to 4 V and (f) current-transfer characteristic curve of the same CS amplifier under fixed Vdd = 3 V, while control voltage Vcont varying from 0.8 to 4 V.

submicrometer n-FETs before/after annealing process is statistically shown in Figure S4, and the average on-state current is improved by 282% after the annealing process. As a result, the annealing process not only improves the performance for both of p- and n-type FETs but also reduces the performance gap between n- and p-type FETs. In particular, an n-FET with Lch/ Lg of 360/220 nm exhibits a maximum current density Idsat of 117 μA/μm and peak transconductance density gm of 85 μS/μm (under Vds = 2 V; see Figure S5); either the Idsat or peak gm value is the highest value among all CNT-based n-FETs.10,11,13 Note that the Sc-contacted topgate n-FETs based on CNT film show a good short-term stability, which is evidenced by that CMOS FETs and ICs in this work or previous works were all measured in ambient air.11,22 However, to achieve long-term stability, an effective passivation for n-FETs to isolate O2/H2O is necessary in the future.27 Meanwhile, a p-FET with the same Lg exhibits an Idsat of 263 μA/μm and gm of 203 μS/μm. Therefore, the channel width of the n-FET (Wn) is designed to be twice that of the pFET (Wp) in our CMOS ICs to achieve a complementary performance match between n- and p-FETs, as shown in Figure 1c−e. Besides, subthreshold swing (SS) is also shown in Figure 1d. Compared to other published works with high onstate CNT FETs,5,10,14,15,27 our CMOS FETs present much better SS (SS of 150 mV/dec for p-FET and 200 for n-FET under low Vds). Figure 1f,g compares the values of Idsat and gm (at Vds = 1 V) between our CNT CMOS FETs (see more detailed output curves with scaled Lg in Figure S6) and other published CNT FETs, revealing two key points. First, the performance of CNT CMOS FETs is significantly promoted by scaling down the gate length to submicron. Second, the ptype FETs are among those high-performance CNT pFETs,5,10,11,14,15,28,29 while our n-FETs present much better

Scanning electron microscope (SEM) images of this highdensity CNT film (>50 CNTs/μm) are shown in Figure 1a and Figure S1a,b. A Raman spectrum (inset of Figure 1a) of this CNT film shows a G-band/D-band peak ratio as high as 45 (even comparable with or better than the CVD grown CNTs),25 which verified that the sorted CNT films are of high quality and with low defects. Top-gated complementary FETs (see schematic and SEM images in Figure 1b,c) are fabricated based on a well-developed doping-free process, that is, Sc or Pd is used as the source/ drain (S/D) contact to realize barrier free n- or p-type FETs on the same CNT film (see the energy band diagram in Figure 1c and fabrication process details in Materials and Methods and Figure S2a−g).9−11,19,22 FETs are designed to present a relative small gate/channel ratio (Lg/Lch= 220 nm/360 nm) to reduce the parasitic capacitance between gate and S/D contacts. However, the ungated CNT regions should not lead to obvious current lowering since they are effectively doped by S/D contacts (Pd or Sc) with a long transfer doping length.26 A pair of typical complementary FETs with Lg = 220 nm (see the SEM image in Figure S2h) exhibits transfer and output characteristics, as shown in Figure 1d,e and Figure S3. Although CMOS FETs built on CNT network films present symmetric performance for Lg larger than 1 μm, the n-FETs would provide much worse on-state performance than the pFETs when Lg is scaled down to the submicrometer level, mainly due to the polymer residuals on CNTs, which affect Sccontacts more severely than Pd-contacts.11 Here, a crucial 600 °C annealing process was carried out to partly remove the polymer residuals coating on the CNTs before CMOS device fabrication. This annealing process was previously reported to be effective for enhancing (100%) the on-state of short channel p-FETs based on CNT network film.14 Here, the on-state of C

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Figure 3. Characteristics of CNT CMOS based voltage-controlled oscillator (VCO). (a) The circuit diagram of a five-stage CMOS VCO. (b) False-colored SEM image of a five-stage VCO with additional one-stage CS amplifier. The scale bar denotes 10 μm. The gate length is 220 nm, and the channel width of all six n-FETs (right) is twice that of all six p-FETs (left). (c) Output voltage signals of the VCO under Vdd = Vcont = 4 V and shows the highest oscillation frequency of 1.98 GHz. (d) Output frequency spectrum of the VCO circuit under Vdd = Vcont = 3.5 V. (e) Comparison of stage delays among published CNT CMOS oscillators and this work.10,13,31,32 (f) Vcont-dependent oscillation frequency and output signal power of another VCO circuit (VCO 2). The output signal power is almost independent of Vcont and fixed at −40 dBm, and the mean sensitivity of the Vcont-dependent frequency is 0.68 GHz/V.

different from a five-stage inverter-based ring oscillator (RO),10,13,14,31 the five-stage CS amplifier-based VCO circuit is designed to maximize the voltage-to-frequency sensitivity, that is, all gates of pull-down transistors (n-FETs) are connected to a control voltage Vcont (i.e., the output of the sensor), and a closed-loop chain is formed on pull-up transistors (p-FETs). A VCO circuit is fabricated based on CNT CMOS FETs with the same gate length (220 nm), as shown in Figure 1d,e. The first required function of the VCO circuit is to generate a GHz carrier wave for the wireless transmission of data. The oscillation characteristics of the VCO circuits are thus measured. A typical fabricated VCO (VCO 1) generates a near-sine wave with an oscillation frequency (fo) of 1.98 GHz and a peak-to-peak voltage amplitude of about 0.1 V at Vdd = Vcont = 4 V (see the Figure 3c). When Vdd is lowered to 3.5 V, the VCO presents a fo of 1.77 GHz and a output power of −37 dBm as shown in Figure 3d. In addition, we fabricated 30 five-stage VCOs based on CMOS FETs with Lg = 220 nm in one chip, and 26 VCOs worked successfully, indicating a total yield of 86%. The failed VCOs are likely due to the rare CMOS inverters with low voltage gain (1.26) of 59/60 as shown in Figure S7a. We now consider another type of special “inverter”, that is, a fiveterminal CMOS single-stage common-source amplifier (CS amplifier, see the circuit diagram in Figure 2d). The performance of CS amplifier (voltage gain or working current (Idd)) can be tuned by the gate voltage of n-FET (Vcont), as shown in Figure 2e (voltage-transfer characteristic) and Figure 2f (current-transfer characteristic). These two figures represent that the voltage gain and working current Idd can be effectively tuned by control voltage Vcont varying from 0.8 to 4 V while with fixed Vdd = 3 V. Note the Idd as the function of control voltage is crucial for the section discussed below. CNT CMOS FETs with the best comprehensive performance will provide the best building blocks for constructing high-speed CMOS ICs. The key functions of interface ICs in a smart sensor or an IoT device are to provide carrier wave and signal modulation, both of which can be performed by a VCO module (see the circuit diagram in Figure 3a). Similar but D

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Figure 4. CNT CMOS VCOs as sensing interface ICs and energy consumption benchmarking. (a) The circuit diagram of a temperature sensor interface module. (b) Detailed output waves under different temperature detected by the commercial temperature sensor. (c) Temperature-dependent oscillation frequency output of VCO with a sensitivity as high as 12.2 MHz/°C or 0.081 °C/MHz (dark blue line is the linear fit with r2 ∼ 0.998) and the stable output peak-to-peak voltage amplitude larger than 0.1 V. (d) Comparison of the energy per cycle of this work with published results. Red stars represent this work under Vdd = 3 V, blue stars represent oscillators based on conventional silicon technology, and green stars represent the calculated results from the EDP and intrinsic gate delay of the best 10 nm gate length CMOS CNT devices.3,35−39

the fo−T relation presents excellent linearity (r2 ∼ 0.998), with a high slope of 12.2 MHz/°C (temperature-to-frequency sensitivity). Furthermore, the VCO circuit exhibits stable output voltage at any temperature in the valid measurement range (see Figure 3c, right axis). Therefore, we can obtain the temperature information by measuring the frequency output from the VCO circuit after calibration. Compared to previously reported sensing interface circuits based on CNT-array ROs (with several kHz operation frequency and low interface sensitivity),33 our VCO exhibits 6 orders of magnitude higher operating frequencies, a much wider tuning range and a higher sensor-to-frequency sensitivity, all of which guarantee that the physical quantity measured by the sensors can be transmitted with better precision and far-field communication using a smaller antenna. In addition, the unit combining VCOs and temperature sensors has high stability and repeatability (see the details in Materials and Methods and Figure S8a,b), making the applications of sensing interfaces in smart sensors or IoT devices possible. Power consumption is one of the most considered metrics for ICs in smart sensors or IoT devices, which are expected to work for a long time powered by a battery.34 Obviously, the dynamic energy dissipation increases with the operating speed in ICs, and the energy efficiency, that is, the normalized energy consumption over the circuit working frequency, is usually used as a metric to benchmark the power dissipation between different circuits.35 We compare the energy efficiency of our

CNT CMOS circuits10 (see the comparison of delay per stage among CNT CMOS oscillators in Figure 3e). Another key parameter for VCO circuits, the voltage-to-frequency sensitivity, is measured by tuning Vcont with Vdd fixed, as shown in Figure 3f. When Vcont is tuned from 2 to 3.5 V, the VCO (VCO 2) presents an fo value varying from 400 MHz to 1.45 GHz (Figure 3f), covering the range of the standard commercial NB-IoT frequency spectrum.23 This VCO exhibits a high voltage-to-frequency sensitivity of approximately 0.68 GHz/V as well as a large voltage tunable range. A commercial analogue voltage output temperature sensor is connected to Vcont of a fabricated VCO module to test its functions as sensing interface circuit, as shown in Figure 4a. The temperature sensor can provide an effective temperature sensing range of 25−150 °C using an output circuit with a 1.7−5 V voltage range. The sensor converts the environmental temperature to an analogue voltage signal, which is input as the Vcont of the VCO and used to tune the oscillating frequency fo. As a result, any temperature within the temperature sensor’s measurement range is converted to a special fo, and the interface sensing function is thus realized. Specifically, in this case, the temperature variation from 25 to 150 °C on the sensor leads to a wide variation in fo (from 0.4 to 1.5 GHz), as shown in Figure 4b,c. Limited by the dynamic range of frequency modulation of the VCO circuit, the linear range of fo−T is narrowed to 75−140 °C, which leads to fo varying from 0.6 to 1.5 GHz. In the valid measurement range (75−140 °C), E

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Figure 5. Fabrication and characteristics of flexible Li-ion battery and antenna. (a) Photo of the high flexibility of the battery as-prepared. (b) The charge−discharge curves and (c) electrochemical impedance spectroscopy (with a frequency loop from 100 kHz to 100 mHz) of a typical flexible battery before and after bending. (d) Photo of the flexible antenna created by inkjet printing nanosilver conductive ink on a PET film. (e) Reflection coefficient (S11) measurement without attaching the Li-ion battery and under different bending conditions (flat, 45° bending and 90° bending). (f) Reflection coefficient (S11) measurement when attaching the Li-ion battery and under different bending conditions.

and Figure S10a−c).41,42 The charge−discharge curve of asprepared flexible battery is shown in Figure 5b, which clearly shows that the discharge plateau is 2.4 V and that a reversible specific capacity of 150 mA h g−1 (based on the weight of LTO) is delivered. No obvious difference in capacity, ohmic internal resistance, or charge-transfer process is observed for the as-prepared flexible battery before or after bending as shown in Figure 5c. On the other hand, the flexible antenna was fabricated by inkjet printing the nanosilver conductive ink onto the PET film (as shown in Figure 5d; see further details in Materials and Methods and Figure S11, including the temperature dependence on conductive stability, the antenna design, and the communication distance), which shows good flexibility, robustness, and low dielectric losses.43,44 The antenna was designed based on the reliable ALN-9662 from the Alien Corporation for UHF RFID and has a center frequency of 915 MHz and a size of 25 mm × 81 mm. Bending measurements indicate that the antenna exhibits a very low susceptibility to performance degradation (Figure 5e). Furthermore, no obvious change is observed in the reflection coefficient (S11) measurements of the antenna under different bending conditions after attaching the Li-ion battery (Figure 5f), indicating that bending of the attached battery has an acceptable effect on the signal emission of the antenna. We finally demonstrate a wireless temperature sensing interface system based on our high speed CNT CMOS IC. A universal and grand scale wireless sensing interface system is shown in Figure 6a schematically. Our CNT IC is embedded

VCO circuits with that of the reported Si CMOS oscillator ICs, as shown in Figure 4d and Figure S9 and Table S1. CNT-based CMOS VCOs present better dynamic energy efficiency than most Si CMOS oscillators with similar gate lengths (or number of technology nodes).3,35−39 Notably, our VCOs are far from optimized in terms of the number of transistors and the circuit design. If using optimized CNT CMOS FETs with scaled Lg of 10 nm to construct the VCOs, the ultimate sub-10 fJ/cycle would be achieved,3 indicating the great potential and advantages of CNT CMOS ICs regarding dynamic energy consumption. It should be noted that the static power consumption would be the main insufficiency in this work since the transistors present high off current owing to the small band gap (0.5 eV) of CNTs, which is also an important issue for all other small band gap semiconductor-based electronics. Some well-designed device structure such as a feedback-gate structure can effectively suppress the off-current to lower the static power dissipation.40 With a suitable device structure and the optimization of circuit design, ICs with low static power consumption accompanied by high speed can both be achieved. To demonstrate an energy efficient wireless sensing interface system, the two other components, that is, the antenna and battery, are needed to be integrated with CNT chip. The Liion battery was assembled on a flexible PET substrate by laminating an anode, separator, cathode, and 2 PET films together and packaged using laminated Al-plastic film, as shown in Figure 5a (see the details in Materials and Methods F

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Figure 6. Real-time wireless sensor interface system. (a) Schematic of a universal wireless sensor interface system based on CNT IC. (b) Calibration (f−T relationship) of the CNT-based VCO (VCO 3). (c) Detailed calibration output waves from CNT interface circuit under specific temperatures. (d) Real-time data (i.e., temperature of car engine shell), as indicated by the wireless receiving signal spectra. Oscillation frequencies ( f1, f 2, and f 3) represent different temperatures (T1, T2, and T3) which verified by a commercial infrared thermometer.

in the flexible substrate (PET) of antenna and powered by the Li-ion battery on its backside as shown in Figure 6a (inset). If a small sensor is connected, sensing data are collected and transmitted by the CNT interface system to the cloud platform via surrounding repeaters/routers, and then a complete wireless interface system is realized. In this system, any terminal, including mobile phones and PCs, can be used to monitor or browse the information graphically in any place with internet access on a grand scale. As a typical example, a commercial temperature sensor is used in this system. The environment temperature is sensed and converted to an electric signal with a specific frequency and then transmitted to nearby routers. A real time demonstration of a completed process, including temperature sensing, signal processing, and transmission via our CNT interface system, is shown in Figure 5b−d. First of all, the output frequency−temperature relation (f−T) of the system (see Figure 5b) was calibrated; the detailed output waves from the IoT device under specific environment temperatures (here we use this temperature

sensor to detect engine shell temperature of a car) are shown in Figure 5c. After f−T calibration, real-time data (i.e., temperature) can be determined from the wireless received signal spectra, as shown in Figure 5d, in which oscillation frequencies (f1, f 2, and f 3) represent different temperatures (T1, T2, and T3) which are verified by a commercial infrared thermometer. Note that the demonstration here is just a special case of applications of the sensing interface system based on CNT IC. In fact, the CNT CMOS IC-based interface system can be adapted into a universal IoT device in the GSM frequency spectrum in many application scenarios when combined with different types of sensors to provide the additional advantages of low-power dissipation, low cost, and flexibility.

CONCLUSIONS In conclusion, we have fabricated high-performance CNT CMOS FETs with deep submicron gate length through a welldeveloped doping-free process and the use of high-quality G

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ACS Nano semiconducting CNT film, and then n-type CNT FETs presented the record on-state performance including current density of 117 μA/μm and peak transconductance of 85 μS/ μm. The fabricated voltage-controlled oscillator (VCO) circuits, consisting of five-stage CS amplifiers, generated a near-sine wave with an oscillation frequency of up to 1.98 GHz and exhibited a high voltage-to-frequency sensitivity of approximately 0.68 GHz/V. The corresponding propagation delay per stage of the CNT CMOS VCOs reached to 50 ps (using the FETs with a gate length of 220 nm), which is much lower than all previous reported CMOS logic ICs based on CNTs or other low-dimensional nanomaterial. In addition, semidigital sensing interface circuits combining CNT VCOs and a commercial temperature sensor were demonstrated with ultrahigh temperature-to-frequency sensitivity, outstanding energy efficiency, and a wide tunable frequency range (from 0.4 to 1.5 GHz), which covers the required GSM or NB-IoT frequency spectrum. Combing a 150 mAh Li-ion battery and a flexible antenna with center frequency of 915 MHz, we finally demonstrate a real time wireless temperature sensing interface system as a typical application example. In general, this work shows potential of high speed and energy efficient CMOS CNT-based electronics to be useful in a wide range of applications especially the smart sensors, IoTs, and cloud computing technologies.

FET was patterned via EBL, and 10 nm thickness HfO2 (80 cycles) film was grown via atomic layer deposition (ALD) at 90 °C HfO2 followed by a lift-off process. Fourth, contacts and gate insulator of nFETs were fabricated using a process similar to that of p-FETs except for using Sc/Al film (80/5 nm) instituting of Pd as contacts. Note there are two separated ALD processes for p-FETs and n-FETs, respectively, which are quite necessary. During the CMOS process, the Pd-contact and CNT channel in p-FET without passivation layer (such as HfO2) are likely to be contaminated by Sc in the lift-off process for the fabrication of n-FET, which will severely lower the yield of CMOS FETs. Finally, top-gate electrodes and upper wires consisting of Pd/Au films (10/90 nm) were formed by EBL, EBE, and a standard lift-off process. It should be noted that jumpers were formed by using overexposed PMMA 200k to electrically isolate upper connection wires (the final Pd/Au layer) from lower connection wires before the fabrication of the final Pd/Au layer (more details of the jumper can be seen in the The Use of Overexposed PMMA Jumpers section). The Use of Overexposed PMMA Jumpers. In this work, we used overexposed PMMA jumpers for the interconnection in our RO circuits owing to the simple process and low parasitical capacitance at junction (the dielectric constant of overexposed PMMA is much lower than that of ALD HfO2). The overexposed PMMA is widely used jumpers in previous works, and its mechanism has been explored.45 Process details: After the lower connection wires were formed, they were spin-coated with PMMA-200k (4000 rpm) and baked under 170 °C for 3 min, followed by electron beam lithrography. In this case, the aperture size of EBL is 120 μm and with 0.02 μm step size. The dose is set on 10000 μC/cm2. After the overdosed EBL, chip was placed in acetone to remove unexposed PMMA region. Using this approach, a jumper with size of μm × μm can be easily formed. Mechanism: PMMA is a typical positive resist in EBL. Moderatedose electron irradiation onto PMMA causes degradation of the resist and the formation of fragments of lower molecular weight that can be removed in a solvent such as methyl isobutylketone (MIBK) in propanol, which does not affect the unexposed resist. However, at higher electron irradiation doses, the PMMA molecules cross-link with each other to form a network of much larger molecules. This kind of cross-linked PMMA is a very tough substance, resistant to most solvents and etchants, such as acetone (the solvents we used in the lift-off process). Unexposed regions of PMMA are of course soluble in the usual solvents. In this way, heavily exposed PMMA can serve as a negative resist to become a jumper to isolate different circuit layers. One of the key reasons to use overexposed PMMA as jumpers is this process is simple and practical as well as compatible with normal EBL based on positive PMMA and standard lift-off process. The Characterization of Devices and Circuits. The as fabricated CNT-based CMOS FETs and ICs were measured using a probe station (Cascade Summit 1100), a semiconductor analyzer (Keithley 4200), an oscilloscope (Agilent DSO90404A), and a spectrum analyzer (Agilent N9020A). Especially for measuring VCO circuits, the Keithley 4200 was used to offer supply voltage (Vdd) and controlled voltage (Vcont), and the Agilent DSO90404A and the Agilent N9020A were used to measure the output waveforms and the output spectrum, respectively. Stability Characterization of GHz CMOS ICs for Sensing Interface. Stability is an important requirement for the applications of CNT CMOS based VCOs. We measured the CNT VCO ICs at high temperature as shown in Figure S8a, in which cyclic measurements were carried out from room temperature (RT) to a fixed high temperature and then back within 150 s. In each circulation, working current of the VCO varied with temperature (time) and returned to an initial value (at RT). Even after four circulations (100 °C, 115 °C, 130 °C, 140 °C) with a whole duration of 10 min, working current of the VCO can also return to the initial value, which indicates that the CNT circuits present excellent thermal stability. During the cyclic raising and falling temperature measure-

MATERIALS AND METHODS Preparation of CNT Film. Arc-discharged CNTs were purchased from Carbon Solutions Inc., and the dispersants (poly[9-(1octylonoyl)-9H-carbazole-2, 7-diyl (PCz)]) were synthesized by Suzuki polycondensation. First, CNTs and PCz were added into toluene to form solution, and then the solution was dispersed with a top-tip dispergator (Sonics VC700) at 300 W for 30 min. Second, the dispersed solution was centrifuged for 0.5 h at 50000 g to remove most of metallic CNTs and insoluble materials. The upper 90% of the supernatant was collected and centrifuged for a second centrifugation for 2 h at 50000 g. Finally, upper 90% of the supernatant was collected as semiconducting single-walled CNTs (s-SWCNTs) for the fabrication of thin film with dip-coating method. The s-SWCNT solution was diluted several times with the toluene for the preparation of CNT film. SiO2/Si substrates with small size (smaller than 5 cm × 5 cm) were immersed in the diluted solution for 3 days and then picked up and purged by high-purity nitrogen. The substrate with CNT film was first immersed in toluene for 10 min and then purged with high-purity nitrogen. We blew away the air in the tube furnace (Thermo Scientific Linderg/Blue M MoldathERM 1100 °C) using 1000 sccm argon and put the substrate covered by the CNT film in the tube furnace to be annealed for 3 h. The detailed annealing temperature is set on 600 °C, and the argon and hydrogen flow rates are 300 and 50 sccm, respectively. After the annealing process, we immediately put the substrate with CNT film repeatedly rinsed in isopropanol (IPA). The detailed characteristics of CNT films are shown in Figure S1 and Figure 1a. Fabrications and Measurements of CNT CMOS FETs and ICs. The fabrication process of CMOS FETs based on CNT film is shown in Figure S2. In general, the most important nanofabrication process is electron beam lithography (EBL) for patterning; before each EBL process, spin-coating poly(methyl methacrylate, PMMA) as positive resist. (In most cases, 4000 rpm followed by a 3 min 170 °C bake) First, Ti/Au films (10 nm/40 nm) were patterned by EBL and deposited as lower connection wires and standard alignment marks. Second, CNT-film active regions were patterned by an EBL process followed by an inductively couple plasma (ICP) etching. Third, pFET contacts were formed by an EBL process, and the deposition of 80 nm Pd films through electron beam evaporation (EBE) followed with a standard lift-off process. Then, the gate dielectric layer for pH

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ACS Nano ment, the relation between frequency (f) and temperature (T) keeps stable and repeatable in the system as shown in Figure S8b.

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ASSOCIATED CONTENT S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsnano.8b09488. Figures S1−S11, Table S1, and references (refs 1−11). Additional discussion on CNT material characterization, detailed fabrication process, more devices performance characterization, yield of inverters and oscillators, stability test, detailed design and fabrication process of Li-ion battery and flexible antenna (PDF)

AUTHOR INFORMATION Corresponding Author

*E-mail: [email protected]. ORCID

Qinghai Meng: 0000-0002-5100-1375 Zhiyong Zhang: 0000-0003-1622-3447 Author Contributions ∥

These authors contributed equally to this work. Z.Z. proposed and supervised the project. Z.Z. and L.D. designed the experiment. L.L., J.H., and D.Z prepared the carbon nanotube film, and L.L. performed all the device/circuit fabrication and performance characterization. S.W. and X.Z. fabricated the flexible antenna, and Q.M. fabricated the flexible Li-ion battery. L.L. and L.D. performed the system demonstration. L.L., L.D., Z.Z., and L.M.P. analyzed the data and cowrote the manuscript. All the authors discussed the results and commented on the manuscript. Notes

The authors declare no competing financial interest.

ACKNOWLEDGMENTS This work was supported by the National Key Research & Development Program (grant no. 2016YFA0201901), the National Science Foundation of China (grant nos. 61621061, 61427901, and 61671020), and the Beijing Municipal Science and Technology Commission (grant no. D171100006617002 1-2). REFERENCES (1) Chau, R.; Datta, S.; Doczy, M.; Doyle, B.; Jin, B.; Kavalieros, J.; Majumdar, A.; Metz, M.; Radosavljevic, M. Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications. IEEE Trans. Nanotechnol. 2005, 4, 153−158. (2) Tulevski, G. S.; Franklin, A. D.; Frank, D.; Lobez, J. M.; Cao, Q.; Park, H.; Afzali, A.; Han, S.-J.; Hannon, J. B.; Haensch, W. Toward High-Performance Digital Logic Technology with Carbon Nanotubes. ACS Nano 2014, 8, 8730−8745. (3) Qiu, C.; Zhang, Z.; Xiao, M.; Yang, Y.; Zhong, D.; Peng, L.-M. Scaling Carbon Nanotube Complementary Transistors to 5 nm Gate Lengths. Science 2017, 355, 271−276. (4) Franklin, A. D. Electronics: The Road to Carbon Nanotube Transistors. Nature 2013, 498, 443−444. (5) Cao, Q.; Tersoff, J.; Farmer, D. B.; Zhu, Y.; Han, S.-J. Carbon Nanotube Transistors Scaled to a 40-nanometer Footprint. Science 2017, 356, 1369−1372. (6) Qiu, C.; Liu, F.; Xu, L.; Deng, B.; Xiao, M.; Si, J.; Lin, L.; Zhang, Z.; Wang, J.; Guo, H.; et al. Dirac-Source Field-Effect Transistors as Energy-Efficient, High-Performance Electronic Switches. Science 2018, 361, 387−392. I

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