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Chemical Instrumentation Edited by GALEN W. EWING, Setan Hall Univenity, So. Orange, N. J. 07079
These articles are i n h d e d to serve ihe readers O ~ T H I JOURNAL S
by calling allention to new developments i n the themy, design, or availability of chemical laboratmy instrumenlation, or by presenting useful insights and ezplanaliom of topics that are of praclical impmtance to those who use, or leach The editor the use of, modern instrumentalia and i ~ t r u m e n t a techniques. l inviles correspondence from prospective contributors.
LXXI.
An Introduction to Microelectronics
Edward M. Winkler and Maarten van Swaay, Kansas State Universitv. Deoartment of Chemistry, Manhattan. Kansas 66506
SEMICONDUCTOR DEVICE TECHNOLOGY (8,10,44-48) The key element of all semiconductor devices is the p-n junction (49-54). A number of processes can he used to fahricate such junctions, hut only two, planar passivation and epitaxy, are applicable to integrated circuit (IC) production. The term integrated circuit implies either the interconnection of previausly fabricated components to form an extremely campact circuit (hybrid integrated circuit), or the simultaneous fabrication of all components of a functional unit by a common process involving a single substrate (monolithic integrated circuit). The starting material for the planar psssivation or epitaxial process is a wafer of an elemental semiconductor such as silicon or germanium. The electronic properties of any material depend on its composition and structure; therefore, the wafer must be electronic grade (1 part impurity in 10'" and of uniform crystallographic orientation. Wafer materials of 98-99% purity are further purified by zone refining. Electronic grade silicon is also obtained by fractional distillation of silicon tetrachloride or trichlorosilane and subsequent decomposition in the presence of hydrogen. The resulting polycrystalline material must be converted to a single crystal (55). In one method (Czochralski), the conversion is accomplished by slowly 10tating and pulling a pure seed crystal from the liquid surface of a molten batch of the polycrystalline starting material. Stringent control of conditions is necessary to minimize imperfections in the crystal structure. Crystals of n- or p-type are produced by addition of an appropriate impu-
rity (dopant) to the molten batch. The 0.3 to 3-in. diameter rod is sliced into wafers with a thickness of about 0.015 in. Lapping and polishing reduce the final thickness to 0.005 to 0.007 in.
Planar passivation Planar passivation includes oxidation, diffusion, and passivation; silicon wafers are normally used. The thermally activated reaction between silicon and an oaidant, such as oxygen, "wet" oxygen, or steam, is used to form a layer of SiOz on the surface of the wafer. Oxide layers may also he formed by anodization, vacuum evaporation, and sputtering. The oxide layer functions as a mask for diffusion and protects the surface of the substrate, particularly p-n junctions, from contaminants (passivation). SisN, has been used in place of SiOz to stabilize the threshold voltage of MOSFETs, especially at higher temperatures (56). ,Instability is caused primarily by migration of sodium ions under constant bias conditions; SiaN4 is less permeable to alkali ions than SiOz. The mask fabrication sequence involving photoresist has been illustrated previously (Fig. 4). P-n junctions are formed by subjecting silicon areas exposed through the oxide mask to the desired dopant (impurity, diffusant). The choice of the dopant is dictated by the required nature of charge carrier (p- or n-type), hy the relative diffusion rates in silicon and in the oxide mask, by the effect of subsequent diffusions, and by the limit of solid solubility in silicon. Boron (p) and phosphorus (n) are most widely used because they have the best overall properties. In comparison, arsenic and antimony have low diffusion rates in silicon; they are,
therefore, more appropriately used to minimize diffusion during subsequent heat cycling. In same cases, a special property of the dopant is necessary to obtain a desired electrical characteristic. Gold, for example, is useful in high-speed switching junctions because it acts as a recombination center for minority carriers. The dopant may be introduced into the vapor stream passing over the silicon substrate (constant-source diffusion), or it may be deposited directly onto the surface of the substrate (limited-source diffusion). In both cases the dopant is "driven in" by diffusion a t a temperature of about 1100'C. Psssivation of the silicon surface occurs when an oxidizing atmosphere is introduced during the final stage of diffusion. An example of planar passivation is shown in Fig. 13. In reality the dopant also diffuses, to some extent, under the oxide mask.
Epitaxy Diffusion produces a nonlinear decrease in impurity concentration with depth. When a constant concentration profile is desired, epitaxy is used. Basically, the process involves monocrystalline growth on a monocrystalline surface (substrate, seed). The growth and the substrate may he chemically the same (iscepitaxyl or different (heteroepitaxy), and need not possess the same crystallographic orientation. Indirect silicon growth involves decomposition of a vaporized silicon compound a t the substrate surface, e.g. SiCI,
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Figure 13. Fabrication sequence for a discrete, double diffused, npn planar transistor
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Volume 50, Number 7, July 1973
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results in a thin, high resistance n-type epi-layer assuring high BVCEO,hacked by a low-resistance collector contact region which keeps V C ~ I . . tlow. I
Monolithic integrated circuits
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Figure 14. Fabrication sequence for a discrete. epitaxial-diffused transistor
Dopants are added to the vapor stream and controlled by the SiCL/dopant concentration ratio. Direct growth techniques, such as vacuum evaporation, sublimation, and sputtering, do not involve intermediatereactions. Epitaxy provides a solution for a prohlem associated with discrete, double diffused planar transistors (Fig. 13) which require a high collector-base breakdown voltage, BVcsa, and a low collector-emitter saturation voltage, V ~ EThe~collec~ ~ tor resistance of the planar structure is sufficient to fulfill the first requirement, i.e. high BVczo, but at the expense of a high V C ~ l s adue l i to high series resistance of the collector. A combination of epitaxial and planar processes, as shown in Fig. 14,
Figure 15. Various fabrication sequences for diode isolated monolithic npn transistors
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The production of a monolithic integrated circuit requires some modification in transistor fabrication as previously illustrated, to accommodate all metallic cantacts on one surface. In addition to transistors, these eircriits may contain diodes, resistors, and capacitors. These closely spaced components must he isolated from one another because the silicon substrate offers a low resistance path hetween them. Common methods of isolation involve reverse-biased p-n junctions (diode isolation), and oxide, beam-lead, or silicon-ansapphire (SOS) isolation (dielectric isolation). Several methods for obtaining diode isalatian are shown in the fabrication sequences for a monolithic npn transistor in Fig. 15. The n-type 'islands' (isolated or isolation regions) are isolated by applieation of a negative potential that is greater than at any other part of the circuit, i.e. reverse bias of the n-isolation/p-substrate junction. One or more components may be imbedded in a single isolation region depending on the common connection and isolation requirements. The n+ region a t the collector-contact junction (shown only in Fig. 1 5 4 insures a good ohmic, rather than rectifying, contact. Note that the sequences in Fig. 15 differ only in the methods used to fabricate the collector and isolating regions. The dependence of electrical characteristics upon the fabrication process will be illustrated later by a brief comparison of the resulting transistors. That comparison will also il~ ~ .that the world of monolithic eirlustrate cuitry is one of compromise in which desired characteristics are approached through optimization. Compromise is essential owing to the interrelationship of the parameters involved, as may be shown by the following example. Please recall that the doping level in the collector is directly related to the collector junction capacitance and inversely related to BVcso, collector series resistance R,,, the width of the depletion layer, and A transistor in the 'on' state (saturation) does not turn 'off immediately when reverse bias is applied to the emitter-base diode, because stored charge in the form of minority carriers accumulates in the base and collector regions while the base-emitter and base-collector diodes are forward conducting. These carriers must be neutralized (through recombination) before the transistor will return to the 'off state. The time requited for recombination (storage time) depends on the concentration of the stored carriers and the availability of recombination centers. Gold, as a recombination center, can be used as a collector dopant to decrease the life time of minority carriers (faster turn-of0. However, the rate of the inverse process, regeneration of minority carriers, will also increase, resulting in more leakage current. To reduce the leakage current, the region in which regeneration occurs, i.e., the depletion layer, is reduced in size by an in-
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