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Confinement-Guided Shaping of Semiconductor Nanowires and

Sharon Lefler , Roi Vizel , Ella Yeor , Eran Granot , Omri Heifler , Moria Kwiat , Vadim Krivitsky , Miguel Weil , Yuval E. Yaish , and Fernando Patol...
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Letter pubs.acs.org/NanoLett

Confinement-Guided Shaping of Semiconductor Nanowires and Nanoribbons: “Writing with Nanowires” Alexander Pevzner, Yoni Engel, Roey Elnathan, Alexander Tsukernik, Zahava Barkay, and Fernando Patolsky* School of Chemistry, The Raymond and Beverly Sackler Faculty of Exact Sciences, Tel-Aviv University, Tel Aviv 69978, Israel S Supporting Information *

ABSTRACT: To fully exploit their full potential, new semiconductor nanowire building blocks with ab initio controlled shapes are desired. However, and despite the great synthetic advances achieved, the ability to control nanowire’s geometry has been significantly limited. Here, we demonstrate a simple confinement-guided nanowire growth method that enables to predesign not only the chemical and physical attributes of the synthesized nanowires but also allows a perfect and unlimited control over their geometry. Our method allows the synthesis of semiconductor nanowires in a wide variety of two-dimensional shapes such as any kinked (different turning angles), sinusoidal, linear, and spiral shapes, so that practically any desired geometry can be defined. The shape-controlled nanowires can be grown on almost any substrate such as silicon wafer, quartz and glass slides, and even on plastic substrates (e.g., Kapton HN). KEYWORDS: Nanowires, nanoribbons, silicon, semiconductor, nanomaterial, shape control, assembly, germanium

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surface. These approaches yield nanowires with limited shape control that must be harvested from the donor substrates if further fabrication of devices is required. Recently, wavy carbon nanotubes serpentines structures were also synthesized by a crystalline surface-directed “nanotube epitaxy” method.29 Notably, no reported synthetic method allows the on-place wafer production of ab initio shape-controlled semiconductor nanowires. Here, we demonstrate a simple and robust confinementguided nanowire growth method that enables one to predesign not only the chemical and physical attributes of the synthesized nanowires, but also allows a perfect and unlimited control over their geometry and location. Via the vapor−liquid−solid (VLS) mechanism, we could grow semiconductor nanowires of different compositions in a wide variety of two-dimensional shapes, such as any kinked (different turning angles), sinusoidal, linear, and spiral shapes, so that practically any desired geometry can be defined. Fine control over the density and number of nanowires was also achieved, and we could synthesize nanowires down to a pitch lower than 50 nm. Plastic substrates are gaining popularity recently for applications such as plastic electronics and bio-medical flexible or implantable sensors. We therefore demonstrate that in addition to substrates like silicon wafers, or quartz and glass slides, these shape-controlled nanowires can be grown also on plastic

n recent years, one-dimensional (1D) nanomaterials such as carbon nanotubes and semiconductor nanowires/nanotubes have been intensively explored as potential building blocks for multiple electronic, optoelectronic, and biosensing applications.1−16 Extensive efforts have been devoted to the synthesis of semiconductor nanowires with controlled chemical and physical properties such as dimension,2,3,17,18 chemical composition,19−22 doping,19−21,23 and crystal structure.24−26 However, and despite the great synthetic advances achieved, the ability to control nanowire’s geometry has been significantly limited. To fully exploit their full potential, new semiconductor nanowires building blocks with ab initio controlled shapes are desired. Shaped-controlled semiconductor nanowires are expected to have novel electrical and optical properties and may be used for the fabrication of novel devices with fewer welding joints and improved electrical connections. A certain limited degree of complexity in silicon nanowire geometry was recently demonstrated using a “nanotectonic” approach.27 This method provides iterative control over nanowire nucleation and growth, affording kinked silicon nanowires in which straight sections of controllable length are separated by 120° triangular joints. Nanowires geometries obtained by this method are limited to kinked triangular nanowire structures. In another report,28 a metal-assisted chemical etching approach was employed, allowing the synthesis of zigzagged silicon nanowires with 150, 125, or 90° turning angles by controlling the crystallographic orientation of the Si mother wafer, reaction temperature, and etchant concentration. The overall quality of the as-synthesized nanowires is rather low and the shape of the nanowires obtained varies along the wafer © 2011 American Chemical Society

Received: May 7, 2011 Revised: December 1, 2011 Published: December 5, 2011 7

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Figure 1. Schematic illustration of the shape-guided growth method.

Figure 2. SEM images of synthesized nanowires with a wide variety of 2D shapes. (a−d) SEM images of multiply kinked two-dimensional Si nanowires with different turning angles from 120 to 80°. The yellow arrow (panel c) highlights the position of the nanocluster catalyst. The scale bars are 250 nm. (e−g) SEM images of sinusoidal shape two-dimensional silicon nanowires with different periods. The yellow arrow (panel e) highlights the position of the nanocluster catalyst. The scale bars are 250 nm. (h) SEM image of a two-dimensional spiral shape Si nanowire. The yellow arrow highlights the position of the nanocluster catalyst. The scale bar is 250 nm. (i) SEM image of a 1D shape-controlled SiNW, by modulation of nanotunnel shape along the growth direction. The scale bar is 250 nm (zoom-in image, scale bar is 250 nm). (j) SEM image of a square-wave shaped silicon nanowire. Scale bar is 250 nm. (k) SEM image of a sample showing multiple sinusoidal-shaped silicon nanowires. Scale bar is 2.5 μm.

dry etching in a reactive ion etcher (RIE) (Figure 1c). The depth of the shape-controlled trench can be modulated between 10 to 500 nm. Second, a 1.5 nm thick titanium adhesion layer was e-beam evaporated, followed by e-beam evaporation of a gold layer of controlled thickness, which functioned both as the sacrificial material defining the enclosed channels (see Supporting Information Figure S1) and as the catalyst for the following VLS-growth of silicon, germanium and additional semiconductor nanowires (Figure 1d). Subsequently, the resist film was lifted-off to reveal the gold lines

substrates (e.g., Kapton HN). Obviously, this can be extended to any type of thermally stable substrates. A schematic description of the method developed in our laboratory is given in Figure 1. First, open trenches of a desired shape, size, number, density, orientation, and location were patterned by electron-beam direct writing on a resist film on a Si wafer with a 600 nm thermal SiO2 layer (Figure 1a,b). The ebeam lithography can be readily replaced by the use of nanoimprint lithography (NIL) masks of the desired properties. The formation of trenches in a SiO2 layer was done by chemical 8

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on the substrate (Figure 1e). Third, the openings of the tunnels were defined by photolithography (Figure 1f). Afterward, a silicon dioxide capping layer was deposited over the substrate by ICP-PECVD (Figure 1g). Finally, after the remaining resist was lifted-off (Figure 1h), the gold buried under the silicon dioxide capping layer was controllably removed by wet etching with standard gold etchant to form the shape-controlled nanotunnels (Figure 1i). In order to retain a relatively short (e.g., several tens of nanometers) length gold sections at the end of the nanotunnels, which will sequentially serve as VLS catalysts for the nanowires growth, the etching process was stopped by immersion of the substrate in deionized water. The length of the resulting gold segment is of crucial importance for the growth of high quality nanowire elements. Gold segments of length longer than 200 nm will lead to splitting of the metal catalyst during the nanowire growth and to nanowires of lower quality. In the next step, Si or Ge nanowire growth was carried out in a hotwall or cold-wall CVD reactor via the VLS process (Figure 1j). Finally, the removal of silicon dioxide capping layer was done by chemical dry etching using RIE (Figure 1k). Scanning electron microscope (SEM) images of synthesized nanowires with a wide variety of 2D shapes, Figure 2, reveals the full capacity of our shape-guiding growth method. These shapes include kinked Si and Ge nanowire structures with different turning angles of between 80−120°, Figure 2a−d, sinusoidal nanowires (Figure 2e−g) with different periods and even more complex shapes like spirals (Figure 2h). Also, the morphology of the nanowire can be modulated along its axial direction, Figure 2i. The clearly visible gold catalyst can be observed at the tip of the growing nanowires (Figure 2c,e,h), indicating that the growth proceeds via the VLS catalytic process27,30−32 throughout the entire synthesis. If allowed, nanowires will escape out from the nanotunnel confinement leading to the growth of unguided nanowires of larger diameters (Supporting Information Figure S2). This further confirms that the growth is indeed based on the VLS mechanism. Notably, these results show that the gold catalyst droplet adopts the shape and dimensions of the nanotunnel under confinement, finally leading to nanowires reflecting the shape of the original nanotunnels. Interestingly, continuous nanowires of high morphological quality are obtained even at the sharpest turning angles, Figure 2j. Thus, this proposed approach allows for a perfect control of the 2D and 1D morphologies of the resulting nanowire elements. These results indeed provide a clear demonstration that this method is universal and can be utilized to achieve semiconductor nanowire structures of any desired 2D geometry. The shape-controlled nanowires growth method allows growing nanowires almost on any substrate such as silicon wafers, quartz, and glass slides, and even on plastic substrates (e.g., Kapton HN). Figure 3 shows SEM images, taken under low vacuum conditions (or obtained using a low vacuum SEM mode) of sinusoidal Si nanowire and linear Ge nanowire grown on quartz and Kapton substrates, respectively. The process described in Figure 1 allows for the direct growth of germanium and silicon nanowires on Kapton substrates at temperatures as high as 450 °C, without any visual deterioration of the Kapton surfaces. The silicon oxide layer deposited on top of the kapton substrates seems to protect the plastic surface from thermal degradation during the nanowire growth. Thus, this method can be applied for the controlled in-place growth of semiconductor nanowires directly on temperature sensitive

Figure 3. (a) SEM image of sinusoidal shape two-dimensional Si nanowire grown upon quartz substrate. The scale bar is 1 μm. (b) SEM image of straight Ge nanowire grown upon plastic (Kapton HN) substrate. The scale bar is 1 μm. The images obtained using a lowvacuum SEM mode.

and flexible substrates, of great potential for future electronic, optoelectronic, and sensing devices. Additionally, electron backscattered diffraction (EBSD) method was utilized for obtaining the nanowire crystallographic properties at high resolution33 in similarity to previous studies.34−36 A detailed study of our as-prepared nanowire structures shows, Figure 4, that all the on-wafer grown

Figure 4. Electron backscattering diffraction (EBSD) analysis. The left panel shows secondary electron images (70° tilt) of Si nanowires with different shapes (a−c) and Ge multiply kinked nanowire (d). The center and right panels show raw and indexed EBSD Kikuchi patterns obtained from the nanowires in the SEM images, respectively. The scale bar is 250 nm. 9

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not limited to these shapes, and practically any desired geometry could be achieved. The nanowires can be grown on a wide variety of substrates such as silicon wafers, quartz, glass slides, and even on plastic substrates. The dimensions of the nanowires can be determined according to the channel width and the thickness of the evaporated gold layer, and tight control over the density, position, and number of nanowires synthesized is readily achieved. The electron back-scattering diffraction and TEM analysis shows that wires grown by the “shape-guiding growth” method show highly crystalline structures. Future research will focus on the study of shapefunction and shape-crystallinity relationships, and applications of our 2D and 3D shape- controlled nanowires. Also, we are currently applying this approach for the growth of nanowire systems of higher complexity, such as controlled crossbar arrays, branched nanowire structures, nanotubular optical onsurface elements, and 3D nanowire-based probes for scanning microscopy applications. Experimental Section. The Si wafers with 600 nm thermal SiO2 were cleaned by soaking in acetone, isopropyl alcohol (IPA) (each for a period of 5 min), rinsed with deionized water, soaked in H2SO4(97%)/H2O2(30%) ratio 3:1 for 5 min, thoroughly rinsed with deionized water, and dried using a dry N2 stream. Cleaned wafers were coated with ZEP520A resist (purchased from Zeon Chemicals) by spinning at 5000 rpm for 60 s, followed by baking at 180 °C on a hot plate for 3 min. The trenches with a variety of dimensions, shapes, and desired location were written by e-beam lithography. The photopatterned wafer was developed by immersing in ZED-N50 developer (purchased from Zeon Chemicals) for 30 s, followed by rinsing with methyl isobutyl ketone (MIBK) for 10 s, and drying using a dry N2 stream (Figure 1a). The formation of the trenches in SiO2 layer was done by chemical dry etching in RIE at the following conditions: CHF3 flow rate 50 sccm, O2 flow rate 2 sccm, He flow rate 15 sccm, total pressure 15 mTorr, and RF plasma 40 W (Figure 1b). Filling the trenches with gold (50 nm), which functioned both as the sacrificial material defining the enclosed channels and as the catalyst for VLS silicon nanowire growth, was made by e-beam evaporation at a base pressure of the 10−7 Torr at 1 nm/s evaporation rate. Titanium 1.5 nm thickness e-beam evaporated layer was served as adhesion layer for gold. Finally, the remaining resist was lifted-off in N,N-dimethylacetamide (purchased from Sigma-Aldrich), rinsed with deionized water and IPA for 5−10 s, and dried using a dry N2 stream (Figure 1c). The openings of the tunnels were defined by photolithography, using LOR-3A copolymer and S-1805 resist (purchased from MicroChem Corp.), which was deposited on the substrate by spinning at 4000 rpm for 40 s, followed by baking at 185 °C/110 °C on a hot plate for 5 min/1.5 min, respectively. The photopatterned wafer was developed by immersing in MF 319 developer (purchased from: Shipley) for 1 min, followed by rinsing with water for 10 s and drying using a dry N2 stream (Figure 1d). Subsequently, the silicon dioxide capping layer was deposited over the substrate by ICP-PECVD at the following conditions: SiH4 flow rate 200 sccm, O2 flow rate 50 sccm, total pressure 80 mTorr, temperature 150 °C, and ICP plasma 300W with bias plasma 50 W. The remaining resist was lifted-off in PG remover (purchased from MicroChem Corp.) at 70 °C, rinsed with deionized water and IPA for 5−10 s, and dried using a dry N2 stream (Figure 1e). Finally, the gold

nanowires have crystalline structures. Clearly, nanowires confined to the nanotunnels can adopt any shape, even sharp at turning angles, without leading to termination of nanowires growth. EBSD results show that nanowires are highly crystalline along their whole length. Removal of nanowires from their parent growth substrates, by FIB-based lamella formation, and the subsequent TEM analysis showed that the nanowires are single-crystalline, Supporting Information Figure 3S. Nevertheless, defects at different extents can occur depending on growth conditions, for example, precursors partial pressures and temperature, which may lead to the pyrolitic deposition of solid material on the tunnels walls, thus affecting the crystal quality of the resulting confined nanowires. Also, small traces of metals, gold or titanium, remaining on the walls of the growth tunnels after their chemical etching, were shown to dramatically affect the crystal quality of grown nanowires. These remaining traces of metal clusters serve as catalysts for the formation of larger silicon clusters which cause the partial or complete clogging of the nanotunnels and the formation of nanowires of low morphological quality, Supporting Information Figure 4S. Furthermore, high-growth temperatures, >500 °C, lead to increased rates of pyrolitic decomposition of gas precursors on the walls of the empty nanotunnels, thus affecting the quality of the resulting wires. We plan in the future to develop FIB-based approaches for the formation of lamellas that will allow us to perform TEM analysis of whole along-their-length nanowire sections and characterize the effect of the growing nanotunnels shape and the turning angle dependency on nanowire morphology attributes. Furthermore, electrical measurements performed on a zigzagged nanowire structure, Figure 5 curves a and b, show

Figure 5. Electrical measurements, Vsd versus Isd, performed on a zigzagged nanowire. Electrical measurement of the straight section of a zigzagged nanowire (black curve) and of the kinked section of the same nanowire structure (red curve). Insets: top-view and side-view SEM images of the electrical device.

that the presence of the kink/turning point does not negatively affect the electrical performance of the nanowire. This shows that the nanowire is continuous and of high morphological quality along its whole length, even at the kinking/turning points. In, summary, we have successfully demonstrated the ability to grow on-surface Si, Ge, and SiGe nanowires, via the vapor− liquid−solid (VLS) mechanism, with a wide variety of twodimensional shapes such as kinked (different turning angles), sinusoidal, linear, and spiral shapes. However, the method is 10

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invested in the optimization of conditions for their preparation. Nonoptimized conditions may lead to completely amorphous nanowire sections or to highly contaminated cross sections, Supporting Information Figure S5 (platinum and carbon contaminations used for the lamella preparation).

buried under the silicon dioxide capping layer was controllably removed by wet etching with standard gold etchant (purchased from Sigma-Aldrich) to form the nanotunnels. In order to retain a relatively short (e.g., several hundreds of nanometers) length of gold slugs in the end of the nanotunnel, which serves as VLS catalysts for the nanowires growth, the etching process was stopped by immersion of the substrate in deionized (DI) water (Figure 1f). Si and Ge nanowire growth was carried out in CVD reactor via VLS process (Figure 1g). Si nanowire growth was at 420− 460 °C and 25 Torr, using a SiH4 (flow rate 5 sccm), diluted with Ar (flow rate 10 sccm). Ge nanowire growth was at 280 °C and 400 Torr, using a 10% GeH4 (flow rate 40 sccm), diluted with H2 (flow rate 200 sccm). Finally, the removal of silicon dioxide capping layer was done by chemical dry etching in RIE at the following conditions: CHF3 flow rate 100 sccm, O2 flow rate 3 sccm, He flow rate 15 sccm, total pressure 50 mTorr, and RF plasma 200 W (Figure 1h). For Kapton HN surfaces, initially Kapton film was cleaned with oxygen plasma at the following conditions: 100 W and 50 sccm O2 for 180 s. To improve the roughness of Kapton film, the film was coated with polyimide (Pyralin PI 2808, purchased from HD MicroSystems). The time sequence for spin coating the polyimide was a 5 s spin at 500 rpm, followed by 30 s at 2000 rpm. The film was then fully polymerized by baking at 100 °C for 60 min, 200 °C for 30 min, and 300 °C for 60 min. Nanowires growth on Kapton films was performed as described above for Si/SiO2 substrates except for the RIE etching step for tranches formation which was not performed. The crystallographic microscopic properties of the wires were analyzed by the electron backscattered diffraction (EBSD) system in FEI Quanta 200 field emission gun (FEG) environmental scanning electron microscope (ESEM). The EBSD system was HKL-Oxford Channel5 with Nordlys II detector. The method provided in situ morphological and crystallographic analysis of the Si and Ge nanowires without removing them from the original substrate. The EBSD Kikuchi patterns were collected from selected points on the secondary electron (SE) wire image for nanoscale crystallographic information. The EBSD analysis was performed at the conventional specimen configuration of 70° tilt position relative to the main e-beam, and in addition at 15 mm working distance and 20 keV main e-beam energy. TEM analysis was performed after removal of the surfaceconfined nanowires from their parent substrates by a FEGHRTEM (Philips Tecnai F20). FIB-based nanowire crosssection lamellas were formed using the following TEM lamella preparation: Step 1: The region of interest is first covered with a ∼650 nm Pt protection layer using a 2 keV e-beam. Step 2: Additional several micrometer Pt protection layer was then deposited using a 30 keV ion beam. Step 3: U-cut was done using 30 keV ion beam. Step 4: The probe was connected to lamella by welding with Pt deposition, then the connections were cut off and the lamella lifted out from trench. (All this was done using 30 keV ion beam). Step 5: The lamella was welded on TEM grid using Pt deposition and the probe was cut off. Step 6: Initially, the thinning of the lamella was done using 30 keV ion beam to the thickness of ∼200 nm, followed by the final thinning that was done using 2 keV ion beam to the thickness of ∼50 nm. The crystalline quality of the resulting nanowire cross sections is strongly dependent on the protocol used for the formation of TEM-lamellas, thus, special attention must be

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ASSOCIATED CONTENT

S Supporting Information *

Figures 1S demonstrates the diameter control of nanowires grown. Figure 2S shows that nanowires grow through the VLS mechanism. Figure 3S shows HRTEM analysis of high quality nanowires. Figure 4S shows SEM images of multiple lowquality nanowires grown at nonoptimal conditions. Figure 5S shows TEM images of FIB-lamella and of low quality Ptcontaminated nanowire cross sections. This material is available free of charge via the Internet at http://pubs.acs.org.

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AUTHOR INFORMATION Corresponding Author *E-mail: [email protected]. ACKNOWLEDGMENTS This work was in part financially supported by the Legacy Fund, Israel Science Foundation (ISF), and the German-Israel Foundation (GIF).

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