Control of Black Phosphorus by Ambient Thermal Treatment

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Functional Nanostructured Materials (including low-D carbon)

Realizing Long-Term Stability and Thickness-Control of Black Phosphorus by Ambient Thermal Treatment Min-Hye Jeong, Dohyun Kwak, Hyun-Soo Ra, A-Young Lee, and Jong-Soo Lee ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.8b04627 • Publication Date (Web): 17 May 2018 Downloaded from http://pubs.acs.org on May 17, 2018

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ACS Applied Materials & Interfaces

Realizing Long-Term Stability and ThicknessControl of Black Phosphorus by Ambient Thermal Treatment Min-Hye Jeong,†# Do-Hyun Kwak,†# Hyun-Soo Ra,† A-Young Lee,† and Jong-Soo Lee†* †

Department of Energy Science & Engineering, DGIST, Daegu 42988, Republic of Korea

ABSTRACT Few-layer black phosphorus has shown great potential for next-generation electronics with tunable band gap and high carrier mobility. For the electronic applications, the thickness modulation of a BP flake is an essential due to its thickness-dependent electronic properties. However, controlling the precise thickness of few-layer BP is a challenge for the highperformance device applications. In this study, we demonstrate that thermal treatment under ambient condition precisely controls the thickness of BP flake. The thermal etching method utilizes the chemical reactivity of BP surface with oxygen and water molecules by the repeating formation and evaporation of phosphoric acid during thermal annealing. Field effect transistor (FET) of the thickness-modulated BP sheet by thermal etching method shows a high hole mobility of ~576 cm2V−1s−1 and a high on-off ratio of ~105. The stability of the BP devices remained for one month under ambient condition without an additional protecting

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layer, resulting from the preservation of active BP layers below native surface phosphorus oxide. KEYWORDS: Back phosphorus, field-effect transistor, thermal etching, thickness control, air stability

INTRODUCTION Black phosphorus (BP), as one of two-dimensional (2D) materials with a weak van der Waals interlayer interaction, has attracted in electronic and optoelectronic device applications due to its fundamental properties as a representative material of the p-type semiconductor.1-2 Few layer BP exhibited a tunable direct band gap from ~0.3 eV to ~1.5 eV by scaling down layers from bulk to monolayer, high carrier mobility of ~1000 cm2V-1s-1 at room temperature, and current modulation of on/off ratio up to 105. of BP,

1, 3-4

In spite of these tremendous properties

precise control of the BP thickness and prevention of the vulnerability of exfoliated

BP flakes under ambient moisture condition are critical issues for high-performance electronic and optoelectronic device applications. Mechanical exfoliation known as a conventional 2D exfoliation method is very inaccurate and inefficient method to acquire the desirable BP thickness. By approaching top-down methods, recently, various etching methods in 2D materials have been reported, such as plasma-based processes and UV etching methods.5-13 Even though these methods have verified quite precise thickness modulation of 2D materials, high energy of the plasma or UV source is likely to cause ineludible defects on surface of 2D materials.8, 11 Another etching method is a thermal annealing, which was already utilized to layer by layer thinning in few layer MoS2.14-15 Similarly, the thermal thinning method in few-layer BP flake was also reported, but its thickness modulation was carried out under vacuum condition above the


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sublimation temperature of 400 oC.16 Moreover, although the growth of molybdenum and tungsten chalcogenide has been reported using chemical vapor deposition (CVD), the growth of large-area BP sheets has not been reported due to the process complexity.17 So far, largearea growth and desired thickness control of BP sheets have been a challenge to overcome for device applications. To improve the stability of BP devices, various passivation layers such as Al2O3,18 hexagonal boron nitride (h-BN),19 graphene oxide20 have been proposed to protect the exfoliated BP sheet from the moisture and surface modifications in order to avoid the adsorption of oxygen and water molecules on its surface. Moreover, recent reports have revealed that the surface modification by using heteroatom or molecule,21-22 metal ions23 and fluorine atoms,24 1, 2-ethanedithiol (EDT) of few-layer BP25 can improve its carrier mobility and responsivity as well as device stability. However, the processes are rather complicated, there are still many challenges to resolve the oxygen-induced degradation on the surface of BP flakes. Fuhrer et al. reported that the degradation of BP sheets originated from the formation of phosphine oxide only on the topmost layer of BP under air exposure, leaving the deeper layer intact.26 Very recently, Wang et al. demonstrated theoretically that a fully oxidized topmost layer of bulk BP can resist destruction from water molecules while the BP underneath can be preserved without degradation.27 This provides a revolutionary way to use a native oxide layer as a passivation layer without other protective layers. In this study, we report on the long-term stability of high-performance BP devices by a native oxide layer as well as optimization of BP devices by the designed thickness control through the cyclic thermal thinning at reasonable temperature under ambient atmosphere. The thickness of thermally etched BP flakes was confirmed by using Atomic Force Microscope (AFM), and it was controlled by specific etching rate, which is determined by annealing temperatures and etching time. Although the surface of as-exfoliated BP flakes is degraded by forming phosphoric acid under ambient air condition,18-19, 26, 28-31 thermally etched BP flakes ACS Paragon Plus Environment


showed no severe surface degradation due to the evaporation of phosphoric acid above its boiling temperature. In addition, we demonstrate that water molecules play a crucial role in the thermal etching behavior by forming phosphoric acid. To investigate charge transport of thermally etched BP sheets, we fabricated BP field-effect transistors (FETs) and measured the electrical properties of thickness-controlled BP devices. Carrier mobility and on-off ratio of the BP FETs were controlled by the thickness of the BP sheet designed by the thermal etching method. The thermally etched BP FETs showed highperformance transport behaviors without a severe degradation and long-term stability for one month, resulting from the conservation of phosphorus layered structure under phosphorus oxide layers.

RESULTS AND DISCUSSION We used a facile thermal etching method, as a top-down method, to control precisely the thickness of BP flakes. The thermal etching process was performed under ambient atmosphere by controlling the reactivity of BP with oxygen species. Figure 1a shows a schematic diagram of the entire etching process. First, few-layer BP sheets were exfoliated mechanically from the bulk BP flake, and then transferred onto Si/SiO2 substrates with 300 nm dielectric layer. The substrates were positioned in the center of a box furnace under ambient atmosphere, and the reaction temperature and time controlled to secure thermal etching conditions. To find the optimal thermal etching condition, we changed annealing temperatures (100, 150, 200, and 250 oC) and reaction time (0, 30, 60, 90, and 120 min), respectively. The variation of BP thickness was confirmed by AFM analysis. Figure 1b and c shows AFM images of BP flakes before and after thermal etching process at 250 oC for 1


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hour. The thickness of BP flakes as confirmed at the line profile in Figure 1d decreased from original 35 nm to 25 nm, and the etching rate in the edge region accelerated to 20 nm. This can be originated from the different surface oxygen concentrations at the edges of the thinner and thicker BP with thickness-dependent band gaps and conduction band edges and the unstable dangling bond along the [001] direction of BP flake at high temperature.16 AFM images for the samples at different annealing temperatures (150, 200, and 250 oC) are illustrated in Figure S1. The surface morphologies of BP sheets annealed above 150 oC were very clean without any bubble forms. We have also characterized pristine and thermally etched BP sheets by Raman spectroscopy. The Raman intensity of three peaks corresponding to in-plane B2g and Ag2 modes and out-of-plane Ag1 mode of the BP sheet decreased markedly by stacking-induced anisotropic structure change due to the reduction of BP thickness with increasing etching time (0, 2 and 3 h) as seen in Figure 1e.11, 28, 32-33 It was reported that the Raman active modes can be shifted by thickness,34 strain,35 temperature,36 and doping.37 However, the thermally etched BP shows no significant Raman peak shift was observed compared with the pristine BP, suggesting negligible structure change of BP after thermal etching. The thermal etching rate is closely related with the annealing temperature of which increase results in a rapid reaction. The etching rates estimated from the slope of the linear fit in Figure 1f were 0.8, 2.7 and 10 nm per 1 hour at 150, 200 and 250 oC, respectively. Thus, the desired thickness of BP sheet can be prepared by controlling the thermal etching time at the specific annealing temperature. The thermal etching mechanism of BP sheet can be explained by understanding the degradation process of BP sheet. Under ambient air condition, the degradation of BP surface initializes from adsorption of superoxide anions dissociated by a light source, making the BP surface highly hydrophilic. Then, water molecules accelerate the breakdown of BP structures by forming phosphoric acid (4H3PO4, volatile compounds), which is a final product of bubble shape under the BP



degradation process.27, 32 By performing a heat treatment higher than the boiling point of the phosphoric acid (158 o

C),38 the phosphoric acid on the BP surface is likely to be evaporated by showing a

reduction of its thickness. However, the bubbles on the BP surface still remained during the annealing at 100 oC for several days as shown in Figure S2. On the other hand, the surface of the BP flakes annealed above 150 oC, which is the similar boiling point of phosphoric acid, indicates a clear surface without any bubbles as shown in Figure S1. The results suggest that the thermal etching behavior of BP flake is attributed from the evaporation of phosphoric acid, leading to a dissolution of PxOy layers formed on the top surface of BP sheets. As the PxOy thickness decreases, the oxygen atoms again penetrate on the BP surface and react with the phosphorus atoms by forming a native oxide. Then, the thermal etching behavior continues by repeating formation and evaporation of phosphoric acid at the high temperature. The phosphoric acid is formed by following this chemical reaction, P4O10 + 6H2O → 4H3PO4 (phosphoric acid). Here, it is impossible to form the phosphoric acid on BP surface without water exposure. To investigate the thermal etching behavior without water, the BP flakes with 39 and 50 nm thickness annealed under O2 as well as N2 environment at 250 oC for one hour, respectively. Interestingly, AFM images in Figures S3a and b represent that thickness reduction of the BP flakes is only less than 1 nm. It signifies that the thickness variation is insignificant during the thermal annealing process under only O2 and N2 environment. Thus, O2 and N2 molecules have no correlation with the thermal etching behavior of BP flake. Consequently, our experimental results suggest that water molecules play a crucial role in BP surface degradation as well as thermal etching behavior of BP flake by forming phosphoric acid. Electronic properties of van der Waals 2D materials can be tuned by modulating thickness


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because the band gap depends on layer thickness by quantum confinement effect.4, 39-41 Fewlayer BP FETs also show the variation of carrier mobility and on-off ratio with respect to the layer thicknesses.41-42 We fabricated BP FETs of which the target thickness is 10, 15 and 20 nm by controlling etching time at 250 oC. Figure 2a shows a schematic of the BP FET after the thermal etching. First, few-layer BP flake was prepared to the target thickness via thermal etching method. Then, the Ti/Au (5/35 nm) electrodes were patterned and deposited by using electron beam lithography and evaporation process, respectively. Figures 2b and c show an optical image of as-fabricated BP FET and AFM result for its thickness of ~10 nm. Figures 2d and e show the output curves for the thermally etched BP FETs with different channel thickness as a function of VDS (drain-source voltage) at back gate bias of -90 and 90 VG (gate voltage), respectively. By reducing the BP thickness, the drain current decreases in consistent with the results of other 2D material based FETs.8, 41 Although the phosphorus oxide on BP surface is formed during thermal treatment, the thermally etched BP FETs exhibit nearly ohmic contact behavior due to the very thin native oxide. Figure 2f shows transfer curve for the BP FETs with different thicknesses as a function of gate bias at 0.2 VDS. The BP FETs under ambient air exposure have exhibited a severe degradation of electrical properties by showing p-type doping behavior and decrease of current density.19,

29

Interestingly, the

thermally etched BP FETs show clear ambipolar behavior, which was attributed to the formation of native phosphorus oxide and reduction of the phosphoric acid remained on BP surface. The on-current (at -90 VG) and off-current (at the neutral point) of the BP FETs with different thicknesses in Figure 2g were extracted from the transfer curve. When BP thickness goes down, a decrease of on-current is insignificant as compared to that of off-current because it is not related to the bandgap, but overall carrier density of the material. On the other hand, off-current is highly dependent on the band gap by following the equation, ACS Paragon Plus Environment


‫ܫ‬௢௙௙ ∝ exp

ିாಸ ௠௞ಳ ்

, where EG is the bandgap, kB is the Boltzmann constant, and T is the

temperature.43-44 By reducing the thickness, off-current significantly decreases due to increase of band gap. Eventually, the on-off ratio of the BP FET with thickness of 10 nm was five orders higher than that of the BP FET of 35 nm thickness. The thickness-dependent on-off ratio is well known in 2D van der Waals family.2 Figure 2h shows the variation of hole and electron carrier mobility in the thermally etched BP FETs as a function of their thickness. The carrier mobility in the linear regime in Figure S4 was calculated from the transconductance (gm) by plotting drain current (IDS) versus gate voltage (VG) at a constant drain-source voltage (VDS). The slope of this plot is equal to gm: µlin = Lgm / (WCiVDS), where L is the channel length, W is the width of the active area, gm is transconductance and Ci is the capacitance of 300 nm SiO2 dielectric layer, respectively. In the thermally etched BP FETs ranging from 10 nm to 25 nm thickness, the hole (electron) carrier mobility increased from 11 (1) to 576 (162) cm2V−1s−1 with increasing the layer thickness. The mobility of 346 (21) cm2V−1s−1 in the BP FET with 35 nm thickness slightly decreased as compared to that in the 25 nm thickness. The nonmonotonic trend of carrier mobility can be explained as a resistive network model comprised of Thomas-Fermi charge screening and interlayer resistive coupling.45-47 In sum, we fabricated the BP FETs having the high hole mobility of 576 cm2V−1s−1 or high on-off ratio up to 105 by modulating their thickness via the thermal etching method. We also investigate the electrical stability of the thermally etched BP FETs under ambient air condition. Figures 3a and 3b show the transfer curves for the pristine BP and the thermally etched BP FETs with different exposure time under ambient air condition. In Figure 3c, the hole mobility of the pristine BP FET (black dots) was abruptly decreased within 12 days due


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to the collapse of active area by phosphoric acid. However, the electron (blue dots) and hole (red dots) mobility of the thermally etched BP FET with the native oxide layer was completely retained as long as 30 days without degradation of device characteristics. The initial hole (electron) mobility of 233 (94) cm2V-1s-1 slightly decreased to 200 (82) cm2V-1s-1 after 30 days, respectively. In addition, the pristine BP FETs showed a strong p-type behavior after 3 days by showing neutral point shift to ~90 VG as shown in Figure 3d. In contrast, the thermally etched BP FET showed a slight decrease of hole and electron mobility and kept ambipolar behavior after even ambient exposure for one month. The enhanced electrical stability of the BP FET is attributed to the formation of native surface oxide under annealing process. Recently, it was reported that the stable oxide on the bulk BP flakes could prevent the degradation under ambient condition for a long time.26 According to the ABMD (Ab initio molecular dynamics) simulation, the air stability of BP surface can be determined by surface oxide species. In case of fully oxidized BP, the formation of P-O-P bonds induces the hydrophilic surfaces, which impedes the adsorption of water molecules and inhibits the surface collapse to improve the air stability. On the other hand, in the partially oxidized BP in which the P-O-P bond is not completely formed, it is difficult to prevent the BP structure from collapsing because the BP surface becomes highly hydrophilic and the P-P bonds are destroyed by H2O adsorption.27 This is consistent with our experimental observation. In Figure S6, XPS spectrum for the thermally etched BP indicates the shift of phosphorus oxide peak of 0.5 eV along the high binding energy as compared to that of BP without thermal annealing under ambient condition. The higher binding energy for phosphorus oxide indicates highly bonded oxygen with phosphorus.26 By forming many P-O-P bonds on the BP surface during thermal annealing, thus, the thermally treated BP FET maintains high stability under ambient air exposure.



Figure 4 shows the cross-section high-resolution TEM (HRTEM) image and EDX elemental mapping images of BP FET with different thicknesses prepared at different annealing temperatures of 150, 200, and 250 oC, respectively. The samples for the TEM images were prepared by covering hexagonal boron nitride (h-BN) on the thermally etched BP FETs to clearly distinguish the amorphous structure of phosphorous oxide between layered structures of BP and h-BN.

Figures 4a-c indicate the cross-section positions to obtain TEM images

and to analyze chemical elements in the thermally etched BP at 150, 200, and 250 oC. As shown in the TEM images of Figures 4d-f, it was demonstrated that the amorphous phosphorus oxide formed on the BP sheet with uniform thickness irrespective of the thickness of BP. At the same time, the TEM images show the layered structure of BP under the phosphorus oxide layer. The thermally etched BP sheets show a high crystallinity exhibiting lattice fringes without any defects. The thickness of the measured phosphorus oxide was about 3 nm, and the thickness of the native oxide remained constant regardless of the annealing temperature. This result indicates that the oxygen-induced degradation or thermal etching behavior under ambient air condition only occurs on the BP surface. Similarly, the elemental analysis in Figures 4h-l show formation of the native surface oxide.

CONCLUSIONS We demonstrated a facile thermal etching method to control BP thickness by taking advantage of chemical reactivity of its surface above annealing temperature of 150 oC under ambient atmosphere. The thinning of BP flakes without surface degradation was confirmed by optical microscopy and AFM. The thermal etching mechanism is similar to BP degradation process, in which phosphoric acid under the ambient condition is formed on the surface of BP sheet and evaporated at high temperature. We also measured the electronic


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properties of the thermally etched BP FETs and achieved a high hole mobility of 576 cm2V−1s−1 or high on-off ratio up to 105 by modulating its thickness through the thermal etching method. In addition, the thermally etched BP FET showed long-term stability under ambient condition for one month. Its electrical property results from the conservation of layered structure under surface oxide. Our study suggests that the ambient thermal thinning method is promising in further fabrication of high quality few layer BP devices on a large scale. Experimental Section Thermally etched BP Sample preparation: BP flakes were exfoliated from bulk flakes using Nitto tape, and the exfoliated BP was stamped onto a 300 nm thick SiO2 layer on a degenerated p-type Si Substrate. To modulate the thickness of BP flakes, the samples were annealed under an ambient condition at 150 to 250 oC for 0.5 to 2 h. The annealing was carried out into the thermal processing system (Daihan Scientific FP-05). After the samples were heated at the specified annealing temperature for each 30 min. The furnace maintains the same temperature during the entire annealing process. Sample characterization: AFM (Park XE7) characterization was carried out in non-contact mode. AFM images of BP flakes were obtained before and after thermal treatment. XPS (Thermo Scientific ESCALAB 250 Xi) measurements were performed in ultrahigh vacuum with a spot size of 900 µm. All XPS spectra were calibrated concerning the binding energy of phosphorus at 130 eV. Raman spectrometer (NICOLET ALMECA XR, Thermo Scientific) equipped with a 532 nm laser was used to characterize BP. High-resolution TEM (HRTEM) images of thermally etched BP FET were obtained using a Hitachi HF-3300 microscope operating at 300 kV. The EDX (Bruker Super-X 4SDD EDX system) spectra were collected with a screen current value of > 2.3 nA to get the signal in a few time without specimen



damage. Fabrication of BP Device: Thermally etched BP flakes were obtained by the aforementioned thermal etching method. Then, electron-beam lithography (Raith 150TWO) was used to define the metal contacts on the thermally treated BP flakes. For the fabrication of back-gated BP transistors, source and drain electrode regions were patterned by using Ebeam lithography and E-beam resistor (PMMA, 950K) was used as a hard mask. Metal deposition (Ti/Au, 5 nm/ 25 nm) was carried out by e-beam vacuum evaporator under 10-6 torr (SRN-200), and device measurement system was carried out by Keithley 2636A in an N2 atmosphere glove box at room temperature. ASSOCIATED CONTENT Supporting Information. A listing of the contents of each file supplied as Supporting Information should be included.; Thermally etched BP Sample preparation, Sample characterization, Fabrication of BP Device; Figures S1. Surface characteristics of few layer BP under ambient atmosphere at different annealing temperatures.; Figures S2. AFM images of few layer BP under ambient condition for few days.; Figures S3. AFM images of few layer BP flake under only O2 and N2 atmosphere.; Figures S4. FET characteristics of etched BP devices by thermal treatment.; Figures S5. XPS spectrum for phosphorus oxide of degraded BP without thermal annealing under ambient condition and thermally etched BP AUTHOR INFORMATION Corresponding Author * [email protected] Author Contributions


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†

These authors contributed equally.

ACKNOWLEDGMENT This work was supported by Basic Science Research Program (2017030044) through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and Future Planning. We also thank H. S. Jang, S. K. Jeon, and J. B. Bang (CCRF DGIST) for discussions of Electron beam and Photo-lithography system. Nano-device fabrication was carried out in CCRF of DGIST.



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FIGURES

Figure 1. Ambient thermal treatment of BP flakes. (a) Schematic illustrations explaining BP thinning mechanism by thermal treatment. (b, c) AFM images before and after thermal treatment at 250 oC for 1 hour. (d) The black and red lines of thickness profile are associated with pristine BP and thermally etched BP, respectively. (e) Raman spectra of pristine BP and thermally treated BP. Inset: optical images of pristine and thermally treated BP. (f) Thermally etched BP thickness with different temperatures of 150, 200 and 250 oC as a function of etching time.



Figure 2. FET characteristics of thermally etched BP devices. (a) Schematic illustration of thermally treated BP FET under ambient atmosphere. (b) Optical image and (c) thickness profile ~10 nm of the etched BP device after thermal treatment at 250 oC for 2 hour. (d, e) IDS - VDS characteristics of thermally etched BP FETs at VG = -90 V and 90 V, respectively. (f) Logarithmic-scale IDS - VG characteristics of the thermally etched BP devices of 35 nm, 25 nm, 15 nm, and 10 nm at VDS = 0.2 V. (g) The variation of on-off current modulation and (h) carrier mobility as a function of thermally etched BP thickness, which were extracted from the electrical characteristics of the devices.


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Figure 3. Electrical stability of pristine BP FET and thermally etched BP FET. (a) Transfer curve of pristine BP FET with different time under ambient exposure. (b) Transfer curve of thermally etched BP FET with different time under ambient exposure. (c) Carrier mobilities of pristine BP FET and thermally etched BP FET as a function of exposure time under ambient condition. (d) Neutral point of pristine BP FET and thermally etched BP FET as a function of exposure time under ambient condition.



Figure 4. Cross section TEM images of thermally etched BP FET with different annealing temperatures of 150, 200, and 250 oC. (a-c) Optical images of thermally etched BP FETs by h-BN passivation at annealing temperatures of 150, 200, and 250 oC, respectively. (d-f) TEM images of cross section into thermally etched BP FETs at annealing temperatures of 150, 200, and 250 oC. (g-i) oxygen and (j-l) phosphorus element mapping images and their intensity profiles of thermally etched BP FETs at annealing temperatures of 150, 200, and 250 oC.


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Table of contents Graphic


Control of Black Phosphorus by Ambient Thermal Treatment

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