Research Article www.acsami.org
In Situ XPS Chemical Analysis of MnSiO3 Copper Diffusion Barrier Layer Formation and Simultaneous Fabrication of Metal Oxide Semiconductor Electrical Test MOS Structures Conor Byrne,*,† Barry Brennan,‡ Anthony P. McCoy,† Justin Bogan,† Anita Brady,† and Greg Hughes† †
School of Physical Sciences, Dublin City University, Dublin 9, Ireland National Physical Laboratory, Hampton Road, Teddington TW11 0LW, United Kingdom
‡
ABSTRACT: Copper/SiO2/Si metal-oxide-semiconductor (MOS) devices both with and without a MnSiO3 barrier layer at the Cu/SiO2 interface have been fabricated in an ultrahigh vacuum X-ray photoelectron spectroscopy (XPS) system, which allows interface chemical characterization of the barrier formation process to be directly correlated with electrical testing of barrier layer effectiveness. Capacitance voltage (CV) analysis, before and after tube furnace anneals of the fabricated MOS structures showed that the presence of the MnSiO3 barrier layer significantly improved electric stability of the device structures. Evidence of improved adhesion of the deposited copper layer to the MnSiO3 surface compared to the clean SiO2 surface was apparent both from tape tests and while probing the samples during electrical testing. Secondary ion mass spectroscopy (SIMS) depth profiling measurements of the MOS test structures reveal distinct differences of copper diffusion into the SiO2 dielectric layers following the thermal anneal depending on the presence of the MnSiO3 barrier layer. KEYWORDS: copper diffusion, manganese silicate, XPS, secondary ion mass spectroscopy, barrier layers, interconnects, capacitance, MOS
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metal/ILD interface.8 When the alloying element reaches the ILD interface, it chemically reacts in a self-limiting fashion with the dielectric surface resulting in the formation of a stable metal oxide or metal silicate barrier layer which acts to prevent Cu diffusion.9,10 In order for a barrier candidate material to be considered, it must fulfill certain criteria such as (a) prevent Cu diffusion into the surrounding ILD, (b) promote adhesion between the Cu line and the ILD (as Cu is known to have poor adhesion to silicon oxide based ILDs), and (c) be thin enough to allow Cu to fill most of the interconnect line, thereby decreasing resistance of the line. Manganese (Mn) has been suggested as a possible candidate to alloy with Cu in the conducting line for use as a self-forming barrier.11,12 Mn has been shown in previous studies to interact with SiO2 to form a stable MnSiO3 barrier layer, which could potentially satisfy all the criteria necessary for integration in future iterations of interconnects. Characterization techniques such as XPS and transmission electron microscopy (TEM) have been used to provide information on the chemical and structural composition of the barrier region, respectively.13,14 In addition, metal oxide semiconductor (MOS) structures are commonly used as test vehicles in order to establish the effectiveness of a barrier
INTRODUCTION Moore’s law has continued to push device geometries for integrated circuits (IC) toward smaller and smaller feature sizes as seen with the downward scaling of devices, which has proved challenging in relation to materials, materials growth and device characterization.1 The introduction of copper, replacing aluminum, as the metal of choice for on chip interconnect lines for IC production in the late 90s, led to significant device improvements in terms of lower resistivity, reduced RC time delay, decreased power consumption and increased resistance to electromigration failure.2,3 With the advantages of the change to Cu also came a number of disadvantages, most notably the potential for Cu diffusion into any surrounding silicon based inter layer dielectric (ILD) material, which can lead to device degradation and ultimately device failure.4,5 In order to prevent this from happening, a dual layer consisting of Ta/TaN is typically employed as a barrier layer for containment of Cu within the conducting metal line. As device geometries continue to shrink, so too must the barrier layer thickness in an effort to increase the volume available for Cu in the smaller conducting lines. Self-forming barriers have been proposed as a replacement for the relatively bulky Ta/TaN barrier layer currently used.6,7 To create a self-forming barrier, a selected metal is alloyed with Cu in the interconnect line. Post metallization annealing then results in expulsion of the alloying element toward all surfaces of the conducting line, including the © 2016 American Chemical Society
Received: August 28, 2015 Accepted: January 6, 2016 Published: January 6, 2016 2470
DOI: 10.1021/acsami.5b08044 ACS Appl. Mater. Interfaces 2016, 8, 2470−2477
Research Article
ACS Applied Materials & Interfaces material system at preventing copper diffusion.15,16 These different characterization techniques are normally carried out on separate samples making it difficult to precisely correlate interface chemistry with electrical performance. To address this issue, in this study dielectric-barrier layer samples are prepared which allow simultaneous interface chemistry measurements and MOS structure fabrication within the ultrahigh-vacuum (UHV) environment, enabling direct comparison between the interfacial chemistry during the barrier layer formation and the electrical performance of fabricated barrier layers.
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temperature before spectra were acquired. The XPS core level spectra were peak fitted using Voigt profiles composed of Gaussian and Lorentzian line shapes while using a Shirley−Sherwood type background. All spectra from an individual core level were fit concurrently to ensure consistency between the various experimental stages. Peak fitting analysis was carried out using AAnalyzer peak fitting software. Once the XPS studies of the interfacial barrier layer formation were complete, a thick Cu capping over layer (>100 nm) was deposited on the whole sample from a tungsten filament evaporator, at a pressure better than 1 × 10−8 mbar, from a Cu metal source of 99.99% purity prior to removal from the UHV system. Capacitance voltage sweeps of the fabricated MOS structures were carried out using a Boonton model 72 b 1 MHz CV meter interfaced to a Keithley 4200 semiconductor parameter analyzer. Voltage sweeps ranged from +10 to −10 V with a step of 0.1 V and hysteresis was tracked by applying a reverse −10 V to +10 V CV sweep immediately following the initial CV sweep. A hold time of 300 s at +10 V (applied to the fabricated Cu gate contact) was used prior to all CV sweeps in order to bias any mobile ions within the dielectric layer toward the Si/SiO2 interface to maximize any flatband voltage shifts within the CV profile. Both N2 flow (flow rate 5 l/min) and atmosphere ambient anneals of the MOS structures were carried out in a tube furnace in a class 1000 clean room. Samples were held at the desired temperature (300 and 400 °C) for 60 min during anneal stages. Ten devices across each sample set were tested, however, for clarity the results for only one device from each set is presented as there was very good reproducibility across the samples. Sub-100-nm cross-sectional lamella structures of the fabricated samples were prepared for transmission electron microscopy (TEM) analysis using a FEI Helios Nanolab system. TEM imaging of the sample structures was carried out on a JEOL 2100 TEM system using an acceleration voltage of 200 kV. SIMS was carried out in an ultrahigh vacuum time-of-flight secondary ion mass spectrometry (TOF-SIMS IV) instrument (ION-TOF GmbH, Muenster, Germany) operating in noninterlaced mode, using a 25 keV Bi3+ ion analysis beam at a sputter current of 0.1 pA, and a 10 keV Cs ion sputter beam with a sputter current of 40 nA. Surface charging was compensated using a 20 eV electron flood gun. An area of 400 μm × 400 μm was sputtered with the Cs ion beam during depth profiling, with analysis carried out by randomly rastering the Bi3+ ion beam in a 150 μm × 150 μm region in the center of the sputter crater.
EXPERIMENTAL DETAILS
Silicon dioxide films were thermally grown to a thickness of 100 nm on an n-type silicon wafer, with individual samples subsequently cleaved from the wafer with dimensions of 2 cm × 1 cm. To facilitate the fabrication of MOS devices, in parallel to preparing an area for XPS analysis on the same sample, a 1 cm × 1 cm laser diced Si shadow mask, with both circular and square gate areas of 500 μm × 500 μm, 750 μm × 750 μm, and 1 mm × 1 mm, was used to cover half of the sample, as shown schematically in Figure 1. This enables parallel
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Figure 1. Schematic illustration of Si shadow mask used to fabricate MOS devices on 100 nm SiO2/Si sample with (a) top down view, (b) side on view, and (c) side on view showing final metal/oxide/ semiconductor fabricated sample.
RESULTS AND DISCUSSION Figure 2 displays XPS survey spectra throughout the course of barrier formation and subsequent Cu capping of the sample. As can be seen in the survey spectra of the degassed sample, the only spectral features detected are silicon and oxygen related, reflecting the lack of any detectable ambient contamination on the SiO2 surface following degassing at 500 °C for 1 h in UHV. A layer of metallic Mn (∼1.2 nm as determined via XPS substrate suppression peak analysis) was deposited in situ onto the clean SiO2 surface at room temperature and the sample was subsequently annealed at 500 °C for 1 h to promote barrier layer formation. Finally, spectra were taken from the thick Cu capping layer which was deposited onto the sample in order to create electrical contacts for the fabricated MOS structures. The absence of both an O 1s and C 1s signals in the survey spectrum following the deposition of the thick Cu capping layer indicates that the film was fully metallic and contamination free within the detection limits of XPS. Figure 3 displays the narrow scan Si 2p core level spectra following degas, Mn deposition and annealing of the sample. This initial degassed surface shows a single peak at ∼103.8 eV, consistent with the BE position of SiO2 from the thermal grown oxide layer. As can be seen following the Mn deposition and 500 °C anneal, the growth of a lower binding peak, relative to
interface chemistry studies by XPS to be carried out on the uncovered section of the sample in addition to fabrication of MOS structures via the covered portion of the sample following metal deposition and anneal stages. The samples were loaded into a UHV chamber (base pressure of 5 × 10−10 mbar) and degassed to a temperature of 500 °C prior to any metal depositions to remove any contaminants from the surface as a results of ambient exposure. Metallic Mn was then deposited in situ in a highly controlled fashion using an Oxford Applied Research EGC04 mini electron beam evaporator, at a pressure of 5 × 10−9 mbar, using Mn chips, procured from Goodfellow Cambridge Ltd. with a purity of 99.98%, which were initially etched in 37% HCl supplied by SigmaAldrich to remove the surface oxide. XPS analysis of the chemical interactions between the deposited Mn and the dielectric surface was undertaken as a function of thermal annealing cycles leading to MnSiO3 formation. The XPS was carried out using a conventional Al Kα (hυ = 1486.6 eV) X-ray source in conjunction with a VG Microtech electron energy analyzer operating at a pass energy of 20 eV and at a pressure of 1 × 10−9 mbar, yielding an overall resolution of 1.2 eV. High temperature annealing studies were carried out in situ at a pressure better than 5 × 10−9 mbar with the sample held at its target temperature (500 °C) for 60 min and allowed to cool to room 2471
DOI: 10.1021/acsami.5b08044 ACS Appl. Mater. Interfaces 2016, 8, 2470−2477
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Figure 2. XPS survey spectra throughout the experimental steps of substrate degas, Mn deposition, 500 °C in situ anneal, and subsequent Cu capping deposition.
Figure 4. XPS O 1s spectra from the SiO2 substrate and at various stages during the formation of the MnSiO3 barrier layer, with a Mn silicate related peak detected at 531.2 eV BE after annealing.
Figure 3. XPS Si 2p spectra from the SiO2 substrate following degas, after 1.2 nm Mn deposition, and subsequent 500 °C anneal. The formation of a MnSiO3 related photoemission peak at 102.7 eV BE is observed only after annealing, with 60° off angle measurement indicating it is surface localized.
Figure 5. XPS Mn 2p spectra following Mn deposition and 500 °C anneal showing the limited formation of a manganese silicate related peak at 641.2 eV upon annealing, with metallic Mn still remaining.
interfacial barrier layer region, however, these were also detected in parallel XPS studies. The absence of an O 1s signal consistent with the presence of substantive Mn oxides in the current study apparent from the spectra in Figure 4 strongly indicates that the primary chemical species formed at the Mn/ SiO2 interface is MnSiO3. These spectra display the high level of control afforded by adopting a UHV approach to the fabrication of MOS structures as the precise chemical composition of the interfacial region can be determined and compared to previous studies prior to Cu deposition. The limited extent of manganese silicate formation is consistent with previous findings by Casey et al.10 which shows that additional oxygen is required to promote more complete conversion of metal Mn into MnSiO3. A second sample was also prepared, following the same procedures, but without the deposited Mn interlayer using the same 100 nm thermal silicon dioxide substrate. Identical XPS results for this sample (excluding barrier formation steps) were obtained (not shown) indicating that the degassed SiO2 substrate was free
the Si 2p substrate peak is evident at a binding energy of 102.7 eV. Off angle XPS spectra (60° off normal emission) show that the new chemical species is surface localized with respect to the SiO2 signal from the degassed surface. Corresponding XPS spectra of the O 1s core levels for the same experimental steps are shown in Figure 4 and also display the growth of a single lower binding energy component peak at 531.2 eV BE following the thermal anneal. These XPS spectral changes along with the change in profile of the Mn 2p spectrum following thermal anneal shown in Figure 5 are consistent with the formation of a MnSiO3 layer as reported in previous studies.9,17,18 In addition, studies using X-ray absorption spectroscopy (XAS) by Mc Coy et al.19 and X-ray absorption fine structure spectroscopy (XAFS) by Ablett at al20 have shown that the dominant Mn chemical species formed following Mn interaction with a variety of dielectric substrates is MnSiO3. In the XAS study reported by McCoy et al.19 additional Mn oxidation states were shown to be present in the 2472
DOI: 10.1021/acsami.5b08044 ACS Appl. Mater. Interfaces 2016, 8, 2470−2477
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Figure 6. Optical microscope pictures of fabricated (a) no barrier, (b) MnSiO3 barrier, (c) dual nonbarrier/barrier MOS structures probed during electrical testing, (d) no barrier, and (e) MnSiO3 barrier following tube furnace annealing and adhesion tape testing showing the poor adhesion of Cu on the SiO2 compared to the MnSiO3 substrates.
Figure 7. CV sweeps of pure Cu reference MOS for as fabricated and annealed stages showing evidence of hysteresis and a negative flat band voltage shift following the 300 °C atmosphere anneal.
Figure 8. CV sweeps of MnSiO3 MOS for as fabricated and following annealing stages displaying thermal stability of the barrier layer structures.
silicate area prior to copper deposition. This meant that the deposited thick copper over layer was simultaneously deposited on the barrier region and directly onto the SiO2 surface. These structures, shown in Figure 6c were then probed across each distinct area within each MOS structure where upon it was found that the area of Cu not covering the MnSiO3 section of the MOS structures was easily scratched, in contrast to the area on the same MOS structures where the MnSiO3 layer was present. While this observation is not a definitive test, it does indicate the significant difference in Cu adhesion to the dielectric surface resulting from the presence of the MnSiO3
from contamination and the deposited Cu was fully metallic and contaminant free. Following fabrication and exposure to atmosphere, the MOS structures were probed on an electrical probe station using needle probe tips viewed under an optical microscope. Figure 6 displays optical microscope images of these devices which show evidence of probe induced scratching on the Cu/SiO2 sample (a) which is not observed on the Cu/MnSiO3/SiO2 barrier samples (b). To investigate this effect further, a separate sample was fabricated using a similar procedure to form the MnSiO3 layer, but the mask was subsequently misaligned with the Mn 2473
DOI: 10.1021/acsami.5b08044 ACS Appl. Mater. Interfaces 2016, 8, 2470−2477
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ACS Applied Materials & Interfaces
Figure 9. (a) XPS survey and (b) Cu 2p spectra of both MnSiO3 and a pure Cu reference samples following atmosphere anneal, with the binding energy of the Cu 2p peaks and presence of characteristic shakeup features indicative of a thick CuO oxide on the surface of both samples.
test due to poor adhesion, apparent from the removal of the gate material. In contrast, the MnSiO3 samples did not fail the tape test, with the gate material remaining on the dielectric layer (scratches are noted in the MnSiO3 MOS samples because of multiple attempts at trying to remove the material via tape testing). Capacitance−voltage measurements of the fabricated MOS structures for the Cu (no barrier) sample are shown in Figure 7. The CV profile for the as fabricated sample, is typical of an ideal MOS structure with clear accumulation, depletion, and inversion regions. The flatband position however is noted to be at negative values, indicating possible charge build up in the oxide material, potentially caused by X-ray irradiation of the sample during XPS analysis.21 In order to remove any defects caused during fabrication, a post metallization anneal (PMA) was performed in an N2 flow environment at 400 °C for 1 h. Following the PMA stage, a shift of flatband capacitance is noted toward ∼0 V, with no hysteresis. Following the same N2 anneal, the CV profiles for the Cu/MnSiO3/SiO2 sample shown in Figure 8 display identical behavior. Thus, it can be said that following the PMA stage, both the Cu/SiO2 and the Cu/MnSiO3/SiO2 samples appear to behave as ideal MOS structures and therefore, this is the reference point used in order to test for any failure of devices. Willis et al.22 have suggested that the origin of Cu+ ions found within dielectric layers of pure Cu MOS structures following device stressing is a result of oxidation of the Cu gate, thereby producing Cu+ ions which diffuse into the dielectric layer of the MOS device. Thus, to stress test these devices, both samples were annealed at 300 °C in atmosphere ambient within the class 1000 clean room to test the barrier effectiveness of the MnSiO3 sample at preventing Cu+ ion diffusion. CV data for both pure Cu and MnSiO3 barrier samples following this anneal are also displayed in Figure 7 and Figure 8, respectively. The post atmosphere anneal CV profile for the Cu/SiO2 sample exhibits hysteresis and a flatband voltage shift to negative voltage values. Hysteresis of the CV profile indicates the movement of charge within the dielectric film during the CV sweep.23 Shifting of the CV profile toward more negative values
Figure 10. Four point probe data of pure Cu (nonbarrier) and MnSiO3 barrier samples post atmosphere anneal showing that the barrier sample displays the same resistance as the pure Cu sample.
Figure 11. TEM images of (a) pure Cu reference (nonbarrier) and (b) MnSiO3 barrier samples showing clear evidence of a continuous interfacial layer on the barrier layer sample.
barrier layer. Further adhesion tests, as displayed in Figure 6d and e for pure Cu and MnSiO3 barrier samples respectively, involving tape tests were performed following tube furnace anneals. As can be seen, the pure Cu MOS gates fail the tape 2474
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Figure 12. ToF-SIMS depth profiles of samples with (a) no barrier layer and (b) with MnSiO3 barrier layer, showing the presence of copper in the SiO2 layer for the sample with no barrier. 3D SIMS images of the corresponding profiles are shown in (c) and (d) which further highlight the effectiveness of the barrier layer at preventing Cu diffusion into the SiO2 layer.
In addition to XPS of post atmosphere annealed samples, four point probe measurements were performed on the blanket portion of each sample and the corresponding sheet resistance values are shown in Figure 10. The data was calculated from an average of four measurements on different parts of each sample to ensure consistency. The identical sheet resistance value of 0.53 Ω/sq for both samples suggests that the MnSiO3 barrier, which has prevented Cu diffusion and increased adhesion to the dielectric layer, does not negatively impact upon the resistance of the Cu layer. Transmission electron microscopy (TEM) cross-sectional imaging was employed to study the structure of both the pure Cu reference and MnSiO3 samples following thermal stress treatments of 300 °C in atmosphere ambient and the images are displayed in Figure 11a and b, respectively. The SiO2 and Cu capping metal layers are clearly visible with the addition of a surface layer, identified as CuO by measuring the variations in the lattice constant, which is consistent with XPS analysis. When examined further, the MnSiO3 barrier layer sample in Figure 11b displays an interfacial layer consistent with the formation of a MnSiO3 barrier layer.10 Secondary ion mass spectroscopy (SIMS) was performed on both the Cu (nonbarrier) and MnSiO3 barrier layer MOS devices following the thermal stress of 300 °C in atmosphere ambient. Figure 12 (a and b) displays the SIMS depth profile of the Cu (nonbarrier) sample as well as a 3D SIMS representation of the distribution over the total sputtered depth. A surface layer of Cu oxide is evident from the depth profile, consistent with the post atmosphere anneal XPS results
also indicates a buildup of positive charge within the dielectric material which is consistent with previous reports of Cu+ ion diffusion into dielectric layers during CV analysis.22,23 In contrast, for the Cu/MnSiO3/SiO2 sample, there are no measurable changes in the CV profile following the atmosphere anneal at 300 °C. Previous reports have suggested that excess metallic Mn resulting from the incomplete conversion of Mn into MnSiO3 could diffuse through the deposited Cu film to the surface, resulting in the formation of Mn oxide layer thereby preventing Cu oxidation and hence inhibiting Cu diffusion into the dielectric.24−26 Thus, in order to ascertain whether the MnSiO3 barrier at the metal/SiO2 interface or a surface localized Mn oxide is responsible for the stability of the MnSiO3 sample, XPS measurements of both samples were performed to determine the surface chemical composition post atmosphere ambient anneal. The survey spectra for both samples, shown in Figure 9a, reveal that the only elements present in the top surface of the samples are copper, oxygen and traces of adventitious carbon, within XPS detection limits. Corresponding high resolution, narrow scans of the Cu 2p photoemission line, as shown in Figure 9b indicate that the chemical state of Cu within both samples is identical and representative of a CuO species.27 No traces of Mn were found in the surface of the Cu/MnSiO3/SiO2 sample, suggesting that no excess Mn has diffused to the surface. This is in agreement with the fact that the Cu surface in both samples appears to be in the same chemical state. This result strongly indicates that the stability of the MnSiO3 sample is due to the presence of the ultrathin barrier layer formed during initial device fabrication. 2475
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ACS Applied Materials & Interfaces and TEM measurements, with a metallic Cu layer still present between the Cu and SiO2, as evidenced by the Cu3− profile and the decrease in the oxygen signal. This Cu metal signal continues to be detected into the SiO2 region of the sample, all the way up to the Si substrate interface, and is consistent with previous SIMS and sputter depth profile studies of Cu diffusion.4,20 Figure 12c and d displays the corresponding SIMS depth profiling spectrum of the MnSiO3 barrier layer sample. As can be seen from the depth profile, a surface layer of Cu oxide is again observed, however, slightly thinner than on the sample with no barrier layer. Again, a Cu3− signal is observed between the copper oxide and SiO2 layers, indicative of metallic copper, however in contrast to the Cu reference spectrum, a decrease in signal is noted at the Cu/SiO2 interface. This decrease in Cu signal corresponds spatially to the location of the MnSiO3 ion signal coming from the barrier layer. No Cu ions are detected beyond the location of the MnSiO3 ion signal, indicating that this layer has prevented the diffusion of Cu into the underlying oxide, which is consistent with the CV measurements. There is no evidence of metallic Mn peaks in the SIMS spectra over the total sputtered depth, indicating that the deposited metallic Mn has fully oxidized. However, this may be due to residual, unreacted Mn diffusing through the metallic Cu layer to form MnO upon interaction with oxygen during formation of the MnSiO3 barrier layer, with MnO2 detected in the Cu layer, and at the surface of the copper oxide (not shown). Considering no Mn is detected at the surface of the samples using XPS, this would suggest that the level of any Mn diffusion to the surface is very low (
