Coupling Two-Dimensional MoTe2 and InGaZnO Thin-Film Materials

Apr 24, 2017 - We report the fabrication of hybrid PN junction diode and complementary (CMOS) inverters, where 2D p-type MoTe2 and n-type thin film ...
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Coupling Two-Dimensional MoTe2 and InGaZnO Thin-Film Materials for Hybrid PN Junction and CMOS Inverters Han Sol Lee,† Kyunghee Choi,‡ Jin Sung Kim,† Sanghyuck Yu,† Kyeong Rok Ko,† and Seongil Im*,† †

Institute of Physics and Applied Physics, Yonsei University, 50 Yonsei-ro, Seodaemun-gu, Seoul 120-749, South Korea ICT Materials & Components Research Laboratory, Electronics and Telecommunications Research Institute(ETRI), 218 Gajeong-ro, Yuseong-gu, Daejeon, 34129, Republic of Korea

‡

S Supporting Information *

ABSTRACT: We report the fabrication of hybrid PN junction diode and complementary (CMOS) inverters, where 2D p-type MoTe2 and n-type thin film InGaZnO (IGZO) are coupled for each device process. IGZO thin film was initially patterned by conventional photolithography either for n-type material in a PN diode or for n-channel of top-gate field-effect transistors (FET) in CMOS inverter. The hybrid PN junction diode shows a good ideality factor of 1.57 and quite a high ON/OFF rectification ratio of ∼3 × 104. Under photons, our hybrid PN diode appeared somewhat stable only responding to high-energy photons of blue and ultraviolet. Our 2D nanosheet−oxide film hybrid CMOS inverter exhibits voltage gains as high as ∼40 at 5 V, low power consumption less than around a few nW at 1 V, and ∼200 μs switching dynamics. KEYWORDS: 2D MoTe2 nanosheet, IGZO thin film, PN junction diode, complementary inverter, hybrid device

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rare.6,27,28 If it is possible to combine such 2D channels with conventionally established ones for CMOS device, then more practical and breakthrough applications could be expected. In the present study, we exhibit a hybrid material system which couples a dry-transfer-processed 2D p-type MoTe2 and a conventional photolithography-patterned n-type amorphous thin-film InGaZnO (IGZO) inspired by technological importance. Both PN junction diode and CMOS inverter are nicely realized by such novel hybrid material system that now opens any further possibilities toward practical applications of 2D nanosheets combined with existing technologies.

INTRODUCTION Transition metal dichalcogenides (TMDs) are well-known 2D nanomaterials with the common formula MX2, where M is a transition metal element from group IV−VII (M = Mo, W, Nb, Re, and so on) and X is a chalcogen element (X = S, Se, and Te). In general, M atoms are sandwiched between X atoms to form a single layer, and each layer can be stacked together via van der Waals forces.1−8 Recently, hexagonal α-MoTe2 (2H phase) among many semiconducting TMDs has been attracting attention due to its favorable optical and electronic properties.9−14 Monolayer α-MoTe2 exhibits a direct optical bandgap of 1.10 eV,13 while its bulk form is an indirect semiconductor with a band gap of 0.88−1.0 eV.10 Few-layer α-MoTe2 fieldeffect transistors (FETs) with Ti source and drain contacts has recently been reported, showing ambipolar15,16 conduction, while MoTe2 nanosheet FETs with thermally annealed or deep work function source/drain contacts have mostly shown strong p-channel operation.12,16 Practical devices such as heterojunction PN (p-MoTe2/n-MoS2) diode, dual gate p-channel MoTe2 FET, and complementary metal oxide semiconductor (CMOS) inverter with p-channel MoTe2 and n-channel MoS2 have also been reported.17−19 In fact, complementary and complementary-like circuits based on 2D TMD semiconductors are numerous in reports mainly focusing on the electrostatic voltage transfer characteristics (VTC).6,15,19−26 However, until now, any 2D CMOS researches toward practical applications seem to be lacking. CMOS inverter with single nanosheet TMD channel has rarely been successful yet,24,25 while reports on coupling 2D FET and industry-proven FET are also very © XXXX American Chemical Society

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RESULTS AND DISCUSSION Photos of our hybrid PN diode are respectively shown in Figure 1a and its inset while magnified optical microscopy (OM) image is also captured from the inset (red dotted circle) to show more details on p-MoTe2/n-IGZO junction in Figure 1b (top). A 50 nm thick amorphous IGZO was deposited by sputter deposition and patterned by photolithography (indicated by blue dotted rectangle), and then a part of its surface was junctioned by 6 nm (or 9-layer) thin MoTe2 flake (indicated by red dotted box) by a dry transfer method, whose details are again explained in CMOS fabrication.13 A 3D device scheme for the PN junction is shown in Figure 1b (bottom) and atomic force microscopy (AFM) results are displayed in Received: February 27, 2017 Accepted: April 24, 2017 Published: April 24, 2017 A

DOI: 10.1021/acsami.7b02838 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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Figure 1. (a) Photo of patterned diode arrays as fabricated on glass and an inset optical microscopy (OM) image of our hybrid diode. (b) Magnified OM image and 3D illustration of our diode as captured from the inset of panel a. (c) Thickness profile, OM image, and 3D scan image of 6 nm thin MoTe2 nanosheet as obtained by AFM.

Figure 2. (a) Dark and photoinduced I−V curves of a hybrid PN diode on glass under red, green, blue, and UV illumination in logarithmic scale. Dark I−V curve was again obtained in linear scale. (b) Linear scale I−V curves obtained under red, green, blue, and UV. Very small VOC of 0.004 V was obtained only under blue and UV as seen in the inset. (c) Energy band diagram of 2D MoTe2 and a-IGZO thin film before realizing 2D−3D hybrid heterojunction. (d) Energy band diagram after interfacing MoTe2 and IGZO for our hybrid p−n junction diode. Note that the charge depletion region exists mainly in IGZO after contact, and it is also noted that before contact the Fermi energy of IGZO is quite close to that of MoTe2 (4.5 eV vs 4.7 eV). ET, EV−N, EC−P, and EF−P represent trap energy level, valence band maximum of n-IGZO, conduction band minimum of pMoTe2, and Fermi level of p-MoTe2, respectively.

However, apparently low photosensitivity was observed particularly under IR, R, and G photons although only ∼0.94 eV is expected as the band gap of our 6 nm thin MoTe2.10 This is possibly because hole density in MoTe2 is much higher than electron density in IGZO,12,29 so a high electric-field region (charge depletion region) may mainly exist in IGZO thickness beneath the junction. As is well-known, MoTe2 has shown a strong p-type conduction in general,2,12 and semiconducting IGZO displays not only a weak n-type conduction if without gate charging but also has defect trap densities in 2.3 eV (trap energy level, ET) below conduction band minimum (EC) but more likely 2.7 eV below its conduction band minimum.30

Figure 1c for MoTe2 thickness (left inset is 3D image showing a step as MoTe2 thickness when AFM probe line-scanned across the junction area as indicated in right OM image). Figure 2a displays the current−voltage (I−V) characteristics of our PN diode in the dark and under energetic photons of near-infrared (IR, 808 nm = 1.53 eV, power density, 0.53 kW/ m2 or 53 mW/cm2), red (R, 630 nm = 1.96 eV, 53 mW/cm2), green (G, 540 nm = 2.3 eV, 35 mW/cm2), blue (B, 450 nm = 2.75 eV, 41 mW/cm2), and ultraviolet (UV, 365 nm = 3.4 eV, 41 mW cm2) laser illuminations. A good ideality factor of 1.57 was obtained from our PN diode in forward bias regime and a high ON/OFF current ratio of 3 × 104 was also observed. B

DOI: 10.1021/acsami.7b02838 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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Figure 3. (a) Photo of patterned CMOS inverter arrays and inset OM image of our hybrid inverter as fabricated on glass. (b) The selected device is magnified in OM to show more details of CMOS, while a typical CMOS circuit is also located below the OM image. (c) Thickness profile, OM image, and 3D scan image of 4 nm thin MoTe2 nanosheet as obtained by AFM. (d) Schematic 3D image of hybrid CMOS inverter.

Figure 4. Device fabrication steps in order: (a) IGZO deposition and patterning by photolithography, (b) Au/Ti bilayer deposition and patterning for source/drain electrodes of IGZO channel and for gate electrode of MoTe2 channel, (c) 50 nm thick Al203 deposition for common gate dielectric, (d) aligned attachment of exfoliated MoTe2 flake on dielectric, below which a patterned gate is located, (e) Pt layer (Pt/Ti/Pt trilayer) deposition for source/drain electrodes of MoTe2 channel and for gate electrode of IGZO channel, and (f) cross-sectional schematics and photo of our hybrid CMOS (note the via hole region).

Hence, it is very likely that the photoresponse from our PN diode originates from IGZO under the illuminations of B (2.75

eV) and UV (3.4 eV, which is even higher than IGZO band gap).29 Such I−V curves were replotted in linear scale in Figure C

DOI: 10.1021/acsami.7b02838 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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Figure 5. (a) Transfer characteristics of the p-MoTe2 and n-IGZO transistors (as measured at different drain voltages). Yellow and green curves show gate leakage current of p- and n-FETs, respectively. (b) Output characteristics of the p- and n-FETs and their linear regime field effect mobility plots [inset: MoTe2 (black curve) and IGZO (blue curve)]. (c) Voltage transfer characteristics (VTC) of our hybrid CMOS inverter with the p- and n-FETs. Peak voltage gains (= −dVOUT/dVIN) appear to be 7.5, 22, and 40 under VDD = 1, 3, and 5 V. The inset shows dynamic inverter switching behavior under 1 V of VDD obtained at a switching frequencies of 1 kHz. (d) Power consumption characteristics of the CMOS inverter display 4 (inset plot), 120, and 300 nW as peaks for VDD = 1, 3, and 5 V.

2b to find any photovoltaic (PV) effects, but those are hardly observed. Only a small open circuit voltage (VOC) of 0.004 V is seen under UV and B (see the inset plot). According to the literature, the conduction band minimum and Fermi levels of IGZO are ∼4.2 and 4.5 eV, respectively, while the valence band maximum of MoTe2 is ∼4.7 eV which would be almost the same as its Fermi level (EF).31−33 Thus, the small VOC is understandable because two Fermi levels are quite close each other. All the details of the above-discussed PN junction events are well-described with energy band diagrams in Figure 2c,d where the two states of p-MoTe2/n-IGZO couple are respectively shown as before and after contact. Photo and OM images of our hybrid CMOS inverters are shown in Figure 3a, where nine devices could be fabricated in principle following our pattern design, but three devices were fabricated here for process convenience. The selected device among these three is magnified in Figure 3b showing more details of CMOS with MoTe2 nanosheet (red dotted line triangle) and amorphous IGZO channels (blue dotted line rectangle). A typical CMOS circuit is also located below the magnified OM image of Figure 3b, but a real connection scheme and details for the circuit are shown in Figure S1. Figure 3c shows the thickness profile and 3D scan image of selected p-channel MoTe2 as measured by AFM, and its inset OM image also shows the scanned part as dashed white line. The thickness of our MoTe2 appears to be ∼4 nm which would be equivalent to 6 layers (6L).13 Figure 3d shows a schematic

3D view of our CMOS inverter, of which the fabrication process details are to be described in the following figures. Figure 4a−e displays a step-by-step process to achieve our hybrid CMOS inverters on glass substrate. Amorphous n-type IGZO was deposited to 50 nm thickness and subsequently patterned by conventional photolithography as shown in Figure 4a and its OM images. Then, by the sputter-deposition of Au/ Ti and the same photolithography, Au/Ti source/drain contact and bottom gate electrode formations were simultaneously patterned for n-channel IGZO and p-channel MoTe2 FETs, respectively (Figure 4b and OM image). A 50 nm thick Al2O3 layer is then deposited at 100 °C by atomic layer deposition (ALD) as a common dielectric for both bottom-gate p-MoTe2 FET and top-gate n-IGZO FET (Figure 4c). On the dielectric layer, 6L thin MoTe2 flake is transferred by direct imprint technique (dry transfer) but aligned on the Au/Ti bottom gate electrode as seen in Figure 4d and the OM image. As a last step, Pt/Ti/Pt layers were deposited on top of the Al2O3 layer and patterned simultaneously for source/drain contacts of p-MoTe2 channel and for top-gate electrode of n-IGZO channel (Figure 4e). (Details on such dry transfer technique using polydimethylsiloxane (PDMS) are found elsewhere and in the Experimental Section.)17,34,35 As a result, we could achieve a hybrid CMOS after making via hole contacts between top Pt/ Ti/Pt and bottom Au/Ti, as shown in the CMOS crosssectional scheme and photo of Figure 4f. We note that this hybrid technique for CMOS is quite novel and promising because conventional amorphous IGZO top-gate FET process D

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nW) by decreasing the VDD to 1 V (inset). Such high power consumption at 5 V is attributed to the high OFF ID of pMoTe2 FET as shown in the transfer curves of Figure 5a. These static VTC and power consumption measurements in our CMOS inverter indicate that the device can be useful as ac amplifier at high VDD and as digital switches at low VDD in dynamic operations.

supports the whole CMOS process using its own dielectric layer without any problem. We in fact measured two other CMOS devices that were fabricated using the patterned IGZO FETs (Figures S2 and S3) and found that each CMOS device operates without any significant problem although each shows somewhat different properties depending on the size and thickness of p-channel MoTe2 flake.12 Figure 5a displays three transfer characteristic curves (drain current−gate voltage; ID−VGS) of p-channel MoTe2 and nchannel amorphous IGZO FETs at VD = −0.1 (and 0.1), −1 (and 1), and −5 (and 5) V, respectively. IG exhibits low gate leakage current of ∼10 pA for both FETs. Those two FETs show very different subthreshold swing (SS) values (as 130 mV/Dec for n-FET and 850 mV/Dec for p-FET) and OFF ID current (∼20 fA for n-FET and ∼100 pA for p-FET). In particular, the OFF ID of p-MoTe2 FET is at least 2 orders of magnitude higher than that of n-channel IGZO FET, while the ON current levels of n- and p-FETs are relatively similar. The high OFF ID of p-MoTe2 FET is known to be due to the small band gap of MoTe2 (∼0.94 eV for 6L).10 According to output characteristics (drain current−drain voltage; ID−VDS) of the pMoTe2 and n-IGZO FETs (Figure 5b), they appear quite symmetric in all voltage ranges, and their linear regime behavior seems to support ohmic contacts in both FETs.36,37 Inset plots are the results from linear mobility estimation in n- and pFETs, and according to the plot, the respective threshold voltages of n- and p-FETs appear to be ∼1 and −1 V. In the present CMOS device, p-MoTe2 FET has a 5−6 times higher value (∼22.4 cm2 /V s) than that of n-FET (∼4.2 cm2 /V s) in mobility although ON ID values are similar. It is simply attributed to the difference in width/length (W/L) ratios of nand p-FETs (respectively, W/L = 6 and 1.3). Static inverter curves as voltage transfer characteristics (VTC) are measured to be shown in Figure 5c, where transition voltages and peak voltage gains are displayed as obtained in a supply voltage (VDD) range of 1−5 V. All transition voltages are nicely located between 0 and each VDD (1, 3, and 5 V), and 3 V operation appears to obtain almost ideal transition voltage (VDD/2). Quite high peak voltage gains of 40, 23, and 7.5 were achieved at respective VDD’s of 5, 3, and 1 V (even higher voltage gains of more than ∼60 are also observed from other CMOS devices in Figure S2). Dynamic inverter switching behavior under 1 V of VDD is displayed in the inset of Figure 5c, which was obtained at a switching frequencies of 1 kHz. As a result, ∼200 μs RC delay is observed at 1 kHz from 1 V full-scale square pulse input (VIN). Such RC delay is attributed to some overlap capacitances and contact resistance in the p- and n-FETs of our complementary device on glass. Even though the I−V curve characteristics in Figure 5b appear quite linear, contact resistance and small Schottky barrier in p-MoTe2/Pt interface are unavoidable. According to the temperature-dependent analysis for Schottky barrier, the barrier height is estimated to be ∼0.135 eV. (Details for this analysis are shown in Figure S4, following a general gate voltage sweep method to find the barrier at the flat band state.)38 We can also suspect the via hole region as an overlap capacitance source because the gate/source overlap in our n- and p-FET design appears very small in Figure 3b; during any patterning (lithography) process some photoresist residue may remain between two metals (see Figure 4f) causing some parasitic capacitance. Figure 5d shows the static power consumption characteristics of our hybrid CMOS device. Relatively high power consumption of ∼300 nW was observed at 5 V of VDD, but it can be dramatically reduced (down to 3−4

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CONCLUSION We have fabricated 2D TMD-IGZO hybrid PN junction diode and CMOS inverter which couple dry-transfer-processed 2D pMoTe2 and conventional photolithography-patterned amorphous thin-film n-IGZO. In view of CMOS architecture, it is regarded as unique that top-gate amorphous IGZO n-FET is initially fabricated at ease by conventional photolithography, which simultaneously supports the fabrication of bottom-gate p-MoTe2 2D FET providing with common Al2O3 dielectric layer. Our 2D nanosheet−oxide film hybrid CMOS inverter exhibits high voltage gains as high as ∼40 at 5 V, low power consumption less than about a few nW at 1 V, and ∼200 μs switching dynamics. Our hybrid PN junction diode shows a good ideality factor of 1.57 and quite a high ON/OFF rectification ratio of ∼3 × 104. Under photons, our hybrid PN diode appeared somewhat stable, only responding to highenergy photons of blue and ultraviolet. We conclude that our MoTe2 /IGZO coupled devices would be promising and practically useful, opening further possibilities toward practical applications of 2D nanosheets as combined with existing device technologies.

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EXPERIMENTAL SECTION

Purchase and Hall Measurements of Bulk MoTe2 Crystals. Bulk MoTe2 crystals were purchased (from HQ Graphene Co.) and characterized by Hall measurement system at room temperature, at which a hole concentration of ∼1017/cm3 was measured with van der Pauw sample geometry and Pt contact (Figure S5). It is regarded that this p-type conduction might be caused by nonstoichiometric MoTe2 with excess Te.39 PN Junction Diode Fabrication. On a precleaned corning glass substrate, a 50 nm thick amorphous InGaZnO (a-IGZO) thin film was deposited in LG Display Co., by using dc magnetron sputtering system at room temperature. [Electron concentration in IGZO film was provided as ∼1015/cm3 from the company for our information.] For patterning a-IGZO layer, conventional photolithography and wet etch using diluted buffered oxide etchant (B.O.E) solution (200:1) were carried out; then, a-IGZO was annealed at 170 °C for 2 h in ambient using hot-plate. For the ohmic contact of a-IGZO, Au/Ti (20 nm/10 nm) bilayers were deposited by using dc magnetron sputtering system and patterned by conventional photolithography.36,37 A α-MoTe2 nanoflake was mechanically exfoliated from bulk crystal using polydimethylsiloxane (PDMS) stamp, and then we transferred the α-MoTe2 nanoflake on patterned IGZO by direct imprinting method (dry transfer) using a CCD-equipped photomask microaligner.17,34,35 Next, metal deposition for the ohmic contact of α-MoTe2 was conducted by using Pt/Ti/Pt (30 nm/30 nm/50 nm) trilayer (dc magnetron sputtering and conventional photolithography were used for the trilayer patterning). Final annealing was implemented at 200 °C for 10 min in air ambient to improve source/drain contact by removing any photoresist residue. CMOS Inverter Fabrication. A 50 nm thick Al2O3 layer as a gate dielectric was deposited on patterned IGZO channel (with Au/Ti source/drain contacts) by using atomic layer deposition (ALD) system. As a next step, a α-MoTe2 nanoflake was mechanically exfoliated from bulk crystal using polydimethylsiloxane (PDMS) stamp, and then α-MoTe2 nanoflake was transferred on the Al2O3 dielectric above the bottom gate electrode (patterned already by Au/ E

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ACS Applied Materials & Interfaces Ti bilayer before ALD) by direct imprinting method using a CCDequipped photomask microaligner.17,34,35 Then, to interconnect pchannel drain and n-channel drain electrodes, we attempted via hole lithography by patterning and etching Al2O3 layer near the corner of a drain electrode of a-IGZO so that the interconnection for VOUT might be formed directly by the metal deposition for the source and drain electrodes of α-MoTe2 and for top gate electrode of a-IGZO. Finally, such metal deposition for the ohmic contact of α-MoTe2 and top gate of a-IGZO was conducted by using Pt/Ti/Pt (30 nm/30 nm/50 nm) trilayer (dc magnetron sputtering and conventional photolithography were used for the trilayer patterning). For CMOS inverter measurement setup, we connected the Au/Ti bottom gate electrode of αMoTe2 FET and Pt/Ti/Pt top gate electrode of amorphous-IGZO FET by Al wire bonding (Figure S1). Measurement. The current−voltage (I−V) characterizations for all the devices were measured in the dark at room temperature using a semiconductor parameter analyzer (HP 4155C, Agilent technologies). For dynamic measurement, we used a function generator (AFG 310, Tektronix) and an oscilloscope (TDS210, Tektronix). The thickness of α-MoTe2 nanoflake was characterized by atomic force microscopy (AFM, Nanowizard I, JPK Instrument). For the photostability measurements in near-IR and visible range, four diode lasers were used: near-IR (808 nm, 53 mW/cm2), R (630 nm, 53 mW/cm2), G (540 nm, 35 mW/cm2), B (450 nm, 41 mW/cm2), and UV (365 nm, 41 mW/cm2).

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ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.7b02838. Real connection scheme for the circuit; photo and optical microscopic images; transfer curves, VTC curves, output voltage gain, and power consumption of additional inverter 2 and 3; transfer curves of MoTe2 FET with temperature increase; effective barrier height for MoTe2−Pt contact. Room temperature Hall measurement results under high magnetic field (H in Tesla) of MoTe2 with Pt contact. (PDF)

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AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. Phone: 82-2-2123-2842. Fax: 82-2-392-1592. Address: Electron Device Laboratory, Science Building, Room 240, Yonsei University, Seoul, 120-749, Korea. ORCID

Seongil Im: 0000-0003-0723-5075 Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS This work was supported by NRF (NRL program: Grant No. 2014R1A2A1A01004815), Creative Materials Discovery Program through NRF funded by the Ministry of Science, ICT and Future Planning (Grant No. 2015M3D1A1068061), the Global Leading Technology Program funded by the Ministry of Trade, Industry and Energy, Republic of Korea (Grant No. 100424332012-11), and Brain Korea 21 plus Program.

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REFERENCES

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ACS Applied Materials & Interfaces

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DOI: 10.1021/acsami.7b02838 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX