Article pubs.acs.org/JPCC
Critical Impact of Gate Dielectric Interfaces on the Contact Resistance of High-Performance Organic Field-Effect Transistors Chuan Liu,† Yong Xu,*,‡ Yun Li,§ William Scheideler,∥ and Takeo Minari*,†,⊥ †
International Center for Materials Nanoarchitectonics, National Institute for Materials Science, Tsukuba, Ibaraki 305-0044, Japan Institut de Microélectronique Electromagnétisme et Photonique−Laboratoire d’Hyperfrequences et de Caractérisation, 3 Parvis Louis Neel, BP 257, 38016 Grenoble, France § School of Electronic Science and Engineering, Nanjing University, Nanjing 210093, People’s Republic of China ∥ Department of Electrical and Computer Engineering, Duke University, Durham, North Carolina 27708, United States ⊥ RIKEN, Wako, Saitama 351-0198, Japan ‡
S Supporting Information *
ABSTRACT: Extensive research on organic field-effect transistors (OFETs) performed to date investigated separately the electronic contact and the gate dielectric interfaces but rarely probed the relation between the two. In this report, the strong impact of the gate dielectric on the contact resistance (Rc) is revealed. With the same semiconductor dioctylbenzothienobenzothiophene (C8-BTBT) and the same device configuration, the Rc value varies greatly from 10 to 66 kΩ·cm depending on the gate dielectric interfaces. Also, the gatevoltage dependency of Rc exhibits an unexpectedly large discrepancy when different dielectrics are used. Intuitive comprehension points to the possibility that the gate dielectric interface affects the morphology of semiconductor and thus the charge injection. However, from microstructure study, albeit the semiconductor film exhibits structural defects on certain dielectrics, the impact on the injection is not crucial. Instead, bias-stress test correlates well with the contact resistance on different dielectric interfaces. At a quantitative level, gate-voltage-dependent Rc can be described by taking into account the different charge trapping induced by the gate dielectrics. The origin of the varied Rc is thus attributed to the trapped charges, which screen the gate field and reduce the carrier mobility simultaneously. A general method is proposed to examine whether the charge injection is significantly influenced by the charge trapping effect due to the gate dielectrics. of semiconductor film, the resident trap densities, or the energetic disorder in semiconductor caused by the internal dipole of the dielectric.11−17 Correspondingly, judiciously choosing polymers or self-assembling monolayer (e.g., with hydrophobic end groups) for the dielectric surface can tune the semiconductor/dielectric interfacial properties and enhance carrier mobility up to orders of magnitude.18−20 As seen above, a large amount of effort has been invested in either one of the two aspects, and these efforts have tremendously advanced interfacial science and device technology. However, investigations closely linking the two factors together are still lacking. Mentioned before, in both the contact and dielectric regions, multiple factors are involved and the mechanisms are complex. Thus, imaginably it would be difficult to build up a direct relationship between dielectric layer and contact resistance (Figure 1a). Yet such effort would be highly valued, because it will help comprehend the origin of low injection efficiency and provide new perspectives and methods to understand device performance.
1. INTRODUCTION Successful demonstrations of using organic field-effect transistors (OFETs) to build up flexible, multifunctional circuits have provoked considerable excitement in lab research.1−3 Researchers try to improve the performance of OFETs by studying the limiting factors and overcoming them, which are found to mainly lie in two aspects: charge injection at the contacts and carrier transport in the channel.4 For the former, various studies support a general principle that the contact resistance increases with a larger injection barrier but decreases with higher carrier mobility or gate voltage, although a detailed prediction is hardly possible.5 These findings have led to many innovations on lowering contact resistance and enhancing injection efficiency, mainly by reducing the energy mismatch at the contact/semiconductor interface, engineering the local film morphology adjacent to the contacts, or lowering access resistance by designing geometrical configurations.5−7 In the meantime, remarkable progress has also been made in understanding carrier transport along the semiconductor/ dielectric interface.8,9 The major findings include that charge transport takes place in a thin accumulation layer at the semiconductor/insulator interface,10 and the gate dielectric layer affects the channel transport by changing the morphology © 2013 American Chemical Society
Received: March 8, 2013 Revised: May 13, 2013 Published: May 17, 2013 12337
dx.doi.org/10.1021/jp4023844 | J. Phys. Chem. C 2013, 117, 12337−12345
The Journal of Physical Chemistry C
Article
Figure 1. (a) Schematic representation of the scope of this study: correlation between the underlying dielectric layer and the injection into organic semiconductor (OSC). (b) Scheme of device configuration and chemical structure of polymer dielectrics.
Figure 2. (a−d) Current−voltage transfer characteristics in the saturation regime (Vd = −40 V) for transistors on various dielectric layers: (a) SiO2, (b) PVP, (c) PMMA, and (d) CYTOP. Channel length L = 300 μm and channel width W = 1000 μm. (e, f) Mobility of the transistors with error bars is shown in (e) saturation regime and (f) linear regime. Channel length ranges from 50 to 350 μm.
considering cumulative trapping effect. Also, the study provides a simple analytical method to examine the trapping effect on contact injection.
In this work, we focus on the impact of dielectric on the contact resistance (Rc) of OFETs. The target material is dioctylbenzothienobenzothiophene (C8-BTBT),21 which attracts much interest for its strong intermolecular packing force and superior carrier mobility.22−24 Gate dielectrics are varied by placing a series of polymer dielectrics on top of SiO2/Si substrates (Figure 1b). The use of SiO2/Si substrates is to avoid charge transport across the bulk of polymer dielectric layers and thus extra leakage current.25,26 Though the same electrodes and architecture are used, an unanticipated large discrepancy is found among those dielectrics in terms of contact resistance, in both magnitude and gate-voltage (Vg) dependence. We then probe the origin of such behavior mainly from film morphology and charge trapping induced by the gate dielectrics. Though there are notable differences in film morphology, it is found that charge trapping rather than film morphology is the primary cause for contact resistance behavior. Further analysis confirms that the gate-voltage dependence of Rc could be described by
2. EXPERIMENTAL METHODS Highly doped silicon wafers with 50-nm-thick oxide layer were used as the substrates. The substrates were ultrasonically cleaned in acetone and 2-propanol for 10 min each, followed by UV ozone treatment for 5 min. The polymer dielectric films were deposited with the SiO2 layer underneath to avoid charge transport across the bulk of polymer dielectric layers and thus extra leakage current.25,26 The polymer layers were formed by spin-coating in ambient atmosphere poly(4-vinylphenol) (PVP, Aldrich, Mw 25 000) in tetrahydrofuran (THF), poly(methyl methacrylate) (PMMA, Fluka, Mw 100 000) in anisole, and CYTOP in solvent (solution:solvent = 1:5), to form 30−60 nm thick films, and the films were annealed at 100 °C for 15 min get rid of any residual solvents. The semiconductor C8-BTBT 12338
dx.doi.org/10.1021/jp4023844 | J. Phys. Chem. C 2013, 117, 12337−12345
The Journal of Physical Chemistry C
Article
Figure 3. (a) Analysis of total resistance to extract Rc of SiO2 devices in linear regime (Vd = −1 V), by fitting with modified TLM. (b) Same analysis on Rc for devices with different dielectrics (Vg = −40 V and Vd = −1 V). Error bars are given. (c) Gate-voltage dependence of Rc for devices with different dielectrics (width normalized). Inset: zoom-in view of data for PMMA and CYTOP.
highest mobility is 3.1 cm2·V−1·s−1 (PMMA, L = 50 μm). Generally, the μsat values of PMMA and CYTOP devices are higher than those of SiO2 and PVP devices. The same trend is also observed in the linear regime. Yet linear regime mobility (μlin) varies to a much higher degree than does the saturation regime mobility, from dielectric to dielectric and also from short channel to long channel (Figure 2f). For example, as L increases from 50 to 350 μm, μlin of PVP increases from 0.12 to 0.67 cm2·V−1·s−1, increased 5-fold, while that of PMMA increases 3-fold. The results of linear mobility reflect vital impacts of contact resistance (Rc) in device operation,28 and such impacts are dependent on the gate dielectric. Usually, Rc of devices in the identical architecture is presumed to be very similar and noticeable variations in Rc are observed only when contact metals or device configurations are varied.5,6,29 Therefore, it is important and interesting to conduct quantitative comparison among the devices and figure out the origin of such dependency. In extracting Rc, we use the modified transfer-line method (MTLM) first on the SiO2 device (Figure 3a):5,30
was vacuum-evaporated onto the substrates (30 nm thick, 0.01 Å·s−1,
