Cyclical Annealing Technique To Enhance Reliability of Amorphous

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Cyclical Annealing Technique To Enhance Reliability of Amorphous Metal Oxide Thin Film Transistors Hong-Chih Chen,† Ting-Chang Chang,*,‡ Wei-Chih Lai,*,† Guan-Fu Chen,‡ Bo-Wei Chen,§ Yu-Ju Hung,§ Kuo-Jui Chang,∥ Kai-Chung Cheng,∥ Chen-Shuo Huang,∥ Kuo-Kuang Chen,∥ Hsueh-Hsing Lu,∥ and Yu-Hsin Lin∥ †

Department of Photonics, National Cheng Kung University, Tainan 701, Taiwan R. O. C. Department of Physics and §Department of Photonics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan R. O. C. ∥ New Display Process Research Division, AU Optronics Corporation, Hsinchu 300, Taiwan R. O. C. ‡

ABSTRACT: This study introduces a cyclical annealing technique that enhances the reliability of amorphous indium-gallium-zinc-oxide (a-IGZO) via-type structure thin film transistors (TFTs). By utilizing this treatment, negative gate-bias illumination stress (NBIS)-induced instabilities can be effectively alleviated. The cyclical annealing provides several cooling steps, which are exothermic processes that can form stronger ionic bonds. An additional advantage is that the total annealing time is much shorter than when using conventional longterm annealing. With the use of cyclical annealing, the reliability of the a-IGZO can be effectively optimized, and the shorter process time can increase fabrication efficiency.

KEYWORDS: indium-gallium-zinc-oxide (IGZO), thin film transistors (TFTs), negative bias illumination stress (NBIS), oxygen vacancies (Vo), metal oxide, anneal, reliability, X-ray photoelectron spectroscopy (XPS)

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cyclical low-temperature annealing (220 °C) process is used to improve metal oxide semiconductors and significantly reduce the fabrication time required; the low-temperature annealing is also suitable for use on a plastic substrate. The total annealing time will be reduced when compared to conventional long-term annealing such that the fabrication throughput can be increased.

INTRODUCTION Recently, the use of flexible display technologies has flourished due to their application in wearable devices and in flexible applications such as foldable displays and e-paper. Amorphous indiumgallium-zinc-oxide (a-IGZO) materials have demonstrated higher electron mobility (10−100 cm2/(V s)) than that of conventional amorphous Si TFTs (1 cm2/(V s)). This a-IGZO material is considered as a potential candidate for use in future display industry applications due to its excellent uniformity (better than LTPS, which possesses a grain boundary) as well as its competitive mobility (a-IGZO: 10−100 cm2/(V s), LTPS: 100 cm2/(V s), and a-Si: 1 cm2/(V s)). In addition, a-IGZO features transparency and room temperature fabrication, which are compatible with flexible plastic substrate display applications.1−3 In addition, a-IGZO demonstrates a low leakage current while in a thin film transistor (TFT) matrix, which results in lower power consumption. However, there are still reliability issues in a-IGZO TFTs, especially due to light illumination when integrated in active matrix liquid-crystal displays (AMLCDs) and in active matrix organic light emitting diodes (AMOLEDs). The transistors are turned off most of the time by light, so the reliability under negative gate-bias illumination stress (NBIS) is very important.4−6 Many studies have investigated gate-bias reliability issues under ambient gases and light illumination for a-IGZO TFTs. Methods for improving annealing have been proposed, including ultraviolet irradiation, microwave energy, temperature modulation, and partial pressure gases.7−9 In this study, a © XXXX American Chemical Society

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EXPERIMENT The n-type a-IGZO TFTs used in the experiment were prepared with an inverted staggered via-contact and etching-stoplayer (ESL) structure which were fabricated on a glass substrate. First, the Ti/Al/Ti (50/200/50 nm) film was deposited by sputtering an argon ion bombardment and was wet etched to form the gate electrode. Next, a SiOx film with a thickness of 200 nm was deposited on the gate metal using plasma enhanced chemical vapor deposition (PECVD) with a SiH4/N2O gas flow ratio of 10:50 sccm at 350 °C to act as the gate insulator. Then, a 60-nm-thick a-IGZO active layer was deposited by a DC-type sputtering system with an atomic molar ratio target of In2O3/Ga2O3/ZnO = 1:1:1 at room temperature, followed by a Special Issue: Materials and Interfaces for Next Generation Thin Film Transistors Received: November 1, 2017 Accepted: February 12, 2018

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DOI: 10.1021/acsami.7b16307 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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semiconductor parameter analyzer and a Cascade M150 microprobe station. The normalized drain current (NID) was defined as ID × L/W, where L and W were the channel length of 20 μm and the channel width of 16 μm for the annealing experiment, respectively. In this work, the threshold voltage (VTH) was defined as the gate voltage (VG) when NID reaches 1 nA in the linear region. The transfer characteristics were measured by

200-nm-thick SiOx etch-stop layer (ESL) deposited by PECVD at 220 °C. In order to avoid SiOx etch selectivity problems between the gate insulator and etch-stop layer, which may cause device breakdown, an etch-stop layer was patterned using inductively coupled plasma (ICP) of CF4 gas, followed by plasma etching of the IGZO thin film at a gas flow of BCl3/Ar (10:10 sccm). The via-contact-type source and drain (S/D) electrodes of Ti/Al/Ti (50/200/50 nm) were formed by sequential sputtering deposition and then were wet etch patterned. Finally, the devices underwent one of two kinds of annealing, either a conventional 1 h annealing in O2 ambient conditions at 220 °C or a cyclical annealing process in O2 ambient conditions at 220 °C (shown in Figure 1), composed of alternating heating

Figure 1. Steps of the cyclical annealing process.

and cooling cycles. This process progressed through four 4 min steps, composed of 3 min of 220 °C annealing followed by a 1 min cooling period. The structure of the inverted coplanar a-IGZO TFTs are shown in Figure 2a. The electrical properties of the a-IGZO TFTs were analyzed using an Agilent B1500A

Figure 3. Energy band diagrams of the proposed mechanisms for negative gate-bias illumination stress, showing the metal oxide semiconductor energy band during the stress for these two distinctive regions: (a) more oxygen vacancies before annealing and (b) fewer oxygen vacancies after annealing.

Figure 2. (a) Inverted coplanar a-IGZO TFTs in an oxygen environment after a 220 °C annealing process. (b) The light spectrum used in these experiments. Time evolution after NBIS of VS = 0 V, VG = −30 V, and VD = 0 V for (c) preannealing and (d) postannealing. B

DOI: 10.1021/acsami.7b16307 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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in NBIS reliability. This was independently verified by applying the bottom gate NBIS vertical electric field. To clarify the mechanism of this phenomenon under negative gate- bias illumination stress conditions, metal oxide semiconductor energy-band diagrams during the stress are shown in Figure 3. According to previous reports, after annealing, the number of oxygen vacancies can be verified by the amount of NBIS degradation.10−13 Owing to the fact that the IGZO has an n-type channel, the holes for the minority carriers and the absorbed photons generate electron−hole pairs, the gate voltage is negative, and the band bends upward when there are a large number of active layer oxygen vacancies. The holes generated via trap-assisted photoexcitation in the a-IGZO bulk by the vertical electric field VG and thermal field emissions are trapped at the interface of the a-IGZO active layer/dielectric layer and in the gate dielectric bulk (shown in Figure 3a) resulting in degradation of a

gate voltage sweeping. In addition, an X-ray photoelectron spectroscopy (XPS) measurement was carried out to examine the surface element combinations of the a-IGZO film after O2 annealing treatment.

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RESULT AND DISCUSSION Figure 2c displays the ID−VG curves as a function of the applied stress versus time for the a-IGZO TFT before and after gatebias illumination stress. The light source was a halogen lamp shown in Figure 2b, and the bias stress conditions were VG = −30 V for 2000 s. The pronounced negative shift after light illumination implies that the illuminated bias stress is caused by light-induced instability in the IGZO bulk. The curve shifted monotonically in the negative direction due to the gate-biasinduced hole-trapping effect. Figure 2d shows the VTH shift after a conventional 1 h O2 annealing, showing an improvement

Figure 4. (a−d) Four cycles of rapid annealing. Annealing time was 3 min, followed by 1 min of cooling, in each of the four cycles. (e) After uncycled oxygen annealing for 1 h, the VTH shift improves by 7.36 V. (f) After cyclical annealing, the VTH shift improves by 13 V. C

DOI: 10.1021/acsami.7b16307 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ACS Applied Materials & Interfaces negative VTH shift, shown in Figure 2c. With the increase in oxygen due to the annealing process, the number of oxygen vacancies can be effectively reduced (Figure 3b), thereby suppressing the hole trapping and reducing the tunneling VTH shift, as shown in Figure 2d. We next compared the results after one relatively long annealing time to the results after multiple short duration annealing cycles and note that the differences observed may be due to the number of annealing cycles rather than the overall length of annealing time. The rapid cyclical annealing process progressed through four steps, each of 3 min followed by a 1 min cooling period, as shown in Figure 1. The results are shown in Figure 4a−d, which illustrates that the time evolution of the transfer curve (ID−VG) for these devices with a channel experiences NBIS of a certain duration after each of the four cycles. Results indicate that the parallel negative VTH shift degradation decreases as the number of annealing cycles increases. A comparison between this cyclical annealing process and the conventional longer annealing process is shown in Figure 4e,f. In the conventional 1 h process, the VTH shift improves by 7.36 V; in contrast, the cyclical annealing process results in a 13 V improvement in VTH. This decrease in the negative VTH shift degradation confirms the importance of filling the oxygen vacancies by annealing multiple times versus a single longer annealing cycle. We investigated the relationship between IGZO transistor oxygen vacancies (Vo) and NBIS reliability from examining how the number of annealing times affected filled oxygen vacancies in the metal oxide semiconductor. The state remains large, trapping two electrons and forming a deep fully occupied state. The Vo2+ in amorphous IGZO is a large deep state, and the Vo+ is smaller space, causing electron trapping to the tail state level in the band gap. Repeated experiments of oxygen cyclical annealing were conducted to confirm that metal oxide semiconductors can indeed reduce defects, and these confirmed that the annealing cooling process is the most important key to bonding. Figure 5a shows from a material standpoint that the

residual stress, the distance between the molecules becomes small, and the thin film becomes denser.14 Next, the amorphous IGZO annealing forms a thin film with fewer oxygen vacancies, as shown in Figure 5c. Here, the annealing affects the position of atoms in space, including the bond lengths, bond angles, and dihedral angles between the three adjacent atoms. Figure 5d shows the amorphous active layer bulk. If the distance between the atoms is longer, then they are less likely to form bonds while cooling. On the other hand, when the distance between the atoms becomes smaller, the ability of the oxygen to bond becomes stronger, as shown in Figure 5e.15−17 When the amorphous IGZO possesses oxygen vacancies and atoms without a periodic arrangement of nonuniformity, the oxygen is annealed and oxygen-atom bonding is associated with atom bond length. If the Vo2+ or Vo+ atomic spacing is too large, it will cause the device to shrink during cooling, such that oxygen bonding does not easily fill oxygen vacancies in the film. After cooling, which fills the oxygen vacancies, internal defects in the material are eliminated, which releases the residual stress of the thin film.18−20 The process as described above describes short duration lowtemperature annealing, which allows recrystallization factors to be ruled out. Next, X-ray photoelectron spectroscopy (XPS) was applied to verify the surface elemental compositions in these IGZObased films. Figure 6 shows the XPS experimental results of the

Figure 6. X-ray photoelectron spectroscopy (XPS) results for the IGZO (O2 annealing of four 3 min cycles) films and IGZO (O2 annealing for 1 h) films.

Figure 5. (a−c) The densities of oxygen-filled a-IGZO films improve as the number of annealing cycles increases. The filling of oxygen vacancies produces a shorter distance between atoms prior to the subsequent annealing. (d) If the atomic spacing is too far, it is not conducive to oxygen bonding. (e) The shorter atomic spacing favors oxygen bonding.

IGZO (O2 annealing for 1 h) and IGZO (O2 annealing for four 3 min cycles) films, where In 3d5/2, Ga 3d5/2, Zn 3d5/2, and O 1s C 1s peaks were obtained. In addition, the atomic ratio of each element was calculated and found to be In/Ga/Zn/O/C equal to 11.69:33.1:11.8:25.33:18.1 for the IGZO (O2 annealing 1 h) film, and In/Ga/Zn/O/C equal to 13.15:29.52:13.66:28.45:15.20 for the IGZO (O2 annealing four 3 min cycles) films. This is compared to pure IGZO where In/Ga/Zn/O/C is 11.82:29.08:9.36:23.85:25.89 (initial). It can be observed here that the concentration of O is clearly higher after O2 cyclical annealing. Moreover, the cyclical O2 annealing treatment has a higher concentration of O on the surface.

annealing process uses oxygen to fill the a-IGZO bulk pores, and the binding of the exothermic reaction eliminates the defects shown in Figure 5b. After the film material releases its

CONCLUSION The effect of a cyclical annealing technique on gate-bias stress under light illumination for an IGZO TFT was investigated,

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DOI: 10.1021/acsami.7b16307 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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(7) Nomura, K.; Kamiya, T.; Ohta, H.; Hirano, M.; Hosono, H. Defect Passivation and Homogenization of Amorphous Oxide ThinFilm Transistor by Wet O2 Annealing. Appl. Phys. Lett. 2008, 93, 192107. (8) Teng, L. F.; Liu, P. T.; Lo, Y. J.; Lee, Y. J. Effects of Microwave Annealing on Electrical Enhancement of Amorphous Oxide Semiconductor Thin Film Transistor. Appl. Phys. Lett. 2012, 101, 132901. (9) Kim, Y. H.; Heo, J. S.; Kim, T. H.; Park, S.; Yoon, M. H.; Kim, J.; Oh, M. S.; Yi, G. R.; Noh, Y. Y.; Park, S. K. Flexible Metal-Oxide Devices Made by Room-Temperature Photochemical Activation of Sol-Gel Films. Nature 2012, 489, 128−132. (10) Ryu, B.; Noh, H. K.; Choi, E. A.; Chang, K. J. O-Vacancy as the Origin of Negative Bias Illumination Stress Instability in Amorphous In−Ga−Zn−O Thin Film Transistors. Appl. Phys. Lett. 2010, 97, 022108. (11) Ji, K. H.; Kim, J. I.; Jung, H. Y.; Park, S. Y.; Choi, R.; Kim, U. K.; Hwang, C. S.; Lee, D.; Hwang, H.; Jeong, J. K. Effect of High-Pressure Oxygen Annealing on Negative Bias Illumination Stress-Induced Instability of InGaZnO Thin Film Transistors. Appl. Phys. Lett. 2011, 98, 103509. (12) Chen, T. C.; Chang, T. C.; Hsieh, T. Y.; Lu, W. S.; Jian, F. Y.; Tsai, C. T.; Huang, S. Y.; Lin, C. S. Investigating the Degradation Behavior Caused by Charge Trapping Effect Under DC and AC GateBias Stress for InGaZnO Thin Film Transistor. Appl. Phys. Lett. 2011, 99, 022104. (13) Liao, P. Y.; Chang, T. C.; Su, W. C.; Chen, Y. J.; Chen, B. W.; Hsieh, T. Y.; Yang, C. Y.; Huang, Y. Y.; Chang, H. M.; Chiang, S. C. Effect of Mechanical-Strain-Induced Defect Generation on the Performance of Flexible Amorphous In−Ga−Zn−O Thin-Film Transistors. Appl. Phys. Express 2016, 9, 124101. (14) Noh, H. K.; Chang, K. J.; Ryu, B.; Lee, W. J. Electronic Structure of Oxygen-Vacancy Defects in Amorphous In-Ga-Zn-O Semiconductors. Phys. Rev. B: Condens. Matter Mater. Phys. 2011, 84, 115205. (15) Ueoka, Y.; Ishikawa, Y.; Bermundo, J. P.; Yamazaki, H.; Urakawa, S.; Fujii, M.; Horita, M.; Uraoka, Y. Density of States in Amorphous In-Ga-Zn-O Thin-Film Transistor Under Negative Bias Illumination Stress. ECS J. Solid State Sci. Technol. 2014, 3, Q3001− Q3004. (16) Lee, S.; Paine, D. C. Identification of the Native Defect Doping Mechanism in Amorphous Indium Zinc Oxide Thin Films Studied Using Ultra High Pressure Oxidation. Appl. Phys. Lett. 2013, 102, 052101. (17) Gan, J.; Lu, X.; Wu, J.; Xie, S.; Zhai, T.; Yu, M.; Zhang, Z.; Mao, Y.; Wang, I. S. C.; Shen, Y.; Tong, Y. Oxygen Vacancies Promoting Photoelectrochemical Performance of In2O3 Nanocubes. Sci. Rep. 2013, 3, 1021. (18) Ueoka, Y.; Ishikawa, Y.; Bermundo, J. P.; Yamazaki, H.; Urakawa, S.; Fujii, M.; Horita, M.; Uraoka, Y. Density of States in Amorphous In-Ga-Zn-O Thin-Film Transistor Under Negative Bias Illumination Stress. ECS J. Solid State Sci. Technol. 2014, 3, Q3001− Q3004. (19) Lee, S.; Paine, D. C. Identification of the Native Defect Doping Mechanism in Amorphous Indium Zinc Oxide Thin Films Studied Using Ultra High Pressure Oxidation. Appl. Phys. Lett. 2013, 102, 052101. (20) Nguyen, T. T. T.; Renault, O.; Aventurier, B.; Rodriguez, G.; Barnes, J. P.; Templier, F. Analysis of IGZO Thin-Film Transistors by XPS and Relation with Electrical Characteristics. J. Disp. Technol. 2013, 9, 770−774.

with the results indicating that the hole-trapping VTH shift decreases as the number of annealing cycles increases, compared to that of a conventional longer annealing process. The oxygen vacancies in the a-IGZO TFTs can be effectively filled by the cyclical annealing process, with the dominant bonding mechanism occurring during the repeated cooling phases. In addition, an annealing temperature of 220 °C extends the distance between the atoms and breaks the Zn−O weak bonds. The subsequent cooling process allows oxygen to refill vacancies and form more stable bonds, shortening the distance between molecules. Therefore, both a-IGZO and SiO2 defects can be effectively reduced. After repetition of the annealing cycles, ion bonds will be stronger and denser. This technique can be applied to metal oxide semiconductors to improve the reliability of the semiconductor industrial processes, reduce the total time of fabrication, and increase the throughput.

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AUTHOR INFORMATION

Corresponding Authors

*E-mail: [email protected] (T.-C.C.) *E-mail: [email protected] (W.-C.L.) ORCID

Ting-Chang Chang: 0000-0002-5301-6693 Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS

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REFERENCES

This work was performed at the National Science Council Core Facilities Laboratory for Nano-Science and Nano-Technology in the Kaohsiung-Pingtung area, and assisted with by the New Display Process Research Division, AU Optronics Co. and the Display Technology Center of Industrial Technology Research Institute. The authors acknowledge the financial support of the Ministry of Science and Technology, Taiwan (MOST) under Contract No. MOST-103-2112-M-110-011-MY3.

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DOI: 10.1021/acsami.7b16307 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX