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Cyclical thinning of black phosphorus with high spatial resolution for heterostructure devices Matthew C. Robbins, Seon Namgung, Sang-Hyun Oh, and Steven J. Koester ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.6b14477 • Publication Date (Web): 13 Mar 2017 Downloaded from http://pubs.acs.org on March 22, 2017

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ACS Applied Materials & Interfaces

Cyclical thinning of black phosphorus with high spatial resolution for heterostructure devices Matthew C. Robbins1, Seon Namgung1, Sang-Hyun Oh1, Steven J. Koester1* 1

Department of Electrical and Computer engineering, University of Minnesota-Twin Cities, 200 Union Street SE, Minneapolis, MN 55455 *Contact author: Ph: (612) 625-1316, FAX: (612) 625-4583, EMAIL: [email protected]

ABSTRACT A high-spatial resolution, cyclical thinning method for realizing black phosphorus (BP) heterostructures is reported. This process utilizes a cyclic technique involving BP surface oxidation and vacuum annealing to create BP flakes as thin as 1.6 nm. The process also utilizes a spatially patternable mask created by evaporating Al that oxidizes to form Al2O3 which stabilizes the unetched BP regions and enables the formation of lateral heterostructures with spatial resolution as small as 150 nm. This thinning/patterning technique has also been used to create the first ever lateral heterostructure BP MOSFET in which half of a BP flake was thinned in order to increase its band gap. This heterostructure MOSFET showed an on-to-off current ratio improvement of 1000× compared to homojunction MOSFETs.

KEYWORDS: black phosphorus, phosphorene, 2D material, heterostructure, MOSFET

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Introduction Black phosphorus (BP) emerged in recent years as a promising new van der Waals semiconductor. 1 - 3 With a thickness dependent direct band gap, 4 high mobility,2 and an anisotropic crystal structure,3 BP shows great promise for future use in electronic and optoelectronic devices. P-type and n-type transistors have been demonstrated showing highperformance with higher mobility, transconductance and on-state current than comparable devices made using transition metal dichalcogenides.4-10 BP has also been shown to be useful for photonic devices, including high-speed, high-responsivity photodetectors.

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These

demonstrations show BP’s potential for use in electronics and optoelectronics. However, the thickness-dependent band gap of BP which may prove to be its most useful property, has so far been largely unexplored for device applications. The band gap of BP varies from 0.3 eV (bulk) to 1.5-2.0 eV (monolayer) and is direct at the gamma point.4 In electronic devices such as metaloxide semiconductor field-effect transistors (MOSFET), the band gap impacts the ON/OFF ratio as well as the barrier height at metal-semiconductor interfaces. In optoelectronic devices, the band gap also determines its absorption/emission spectrum and can also determine other important properties of a device such as dark current and noise. In most materials, the band gap cannot be controlled in a practical manner, making any type of tunable performance difficult without using a different material. To date, the thickness-dependence of the band gap in BP has primarily been studied simply by utilizing the random variations in thickness resulting from mechanical exfoliation. These studies have yielded interesting results showing thickness dependent ON/OFF current ratios in MOSFETs4 and thickness dependent photoluminescence spectra.14 More recently, work has been reported on controlled thinning of BP using plasma-based processes 15-17 , Ozone oxidation18 ,


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and laser oxidation. 19 , 20 However, these methods do not provide cyclical thinning, thereby requiring precise calibration of etch time. A layer-by-layer scanning probe nanopatterning method 21 has been demonstrated， but layer-by-layer precision is lost when performing the process on insulating substrates that are necessary for device fabrication. In this work, we present a robust, cyclical, top-down, BP thinning process which represents a novel method for precise BP thickness control. This method also enables high spatial etch resolution which gives it the potential to enable a plethora of novel devices including double-heterostructure light emitters and a variety of heterostructure FETs. We use this process to fabricate BP MOSFETs and compare the transport characteristics of the thick and thin regions in addition to fabricating the first ever lateral 2D heterostructure BP MOSFET which shows 3 orders of magnitude improvement in offstate leakage with minimal degradation to the on-state current.

Experimental Our thinning process utilizes BP’s inherent reactivity in air as the primary mechanism for controlled thinning. It has been shown by multiple groups22-25 that as BP is exposed to ambient atmosphere and light the top layer(s) react with the adsorbed H2O and O2 on the surface creating large bubbles and enlarged flake volumes consisting of PxOy and HxPyOz compounds after prolonged exposure (greater than one week). It has also been shown that some of these compounds volatize if the sample is annealed at a high temperature leaving behind a thinner version of the original BP along with some residues.23,25 Multiple groups23,25,26,27 suggest that one of the reaction byproducts is P2O5 which is stable at high temperatures and could be a component of the residue observed in reference 25. However, Edmonds et al.26 showed via photo-electron spectroscopy that when ambient air exposure is limited (~ 5 minutes) the stable P2O5 does not form. Instead they provided evidence for the formation of more volatile phosphoric acid or


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physisorbed oxygen and nitrogen. Experimental results presented in this work support the findings that if the ambient exposure time is limited, the BP surface reacts with the air and forms volatile POx compounds. These volatile compounds are then removed by the subsequent 300 °C anneal, with 300 °C being a temperature at which BP has been shown to remain crystalline.28 We show that this property creates a platform for developing a cyclical thinning process for BP. To explore the use of this mechanism, a patterned thinning process was developed and used to fabricate samples containing BP flakes with spatially-controlled thickness variation. These patterned flakes were then characterized using optical microscopy, atomic force microscopy (AFM), Raman spectroscopy, and photoluminescence (PL) measurements. The procedure began by exfoliating BP (99.9% percent purity from Smart ElementsTM) using adhesive tape, then transferring the BP flakes on the tape to a polydimethylsiloxane (PDMS) stamp using a similar process to that of Castelannos-Gomez, et al..29 BP flakes were then transferred from the PDMS stamp to a Si substrate with a 290-nm-thick thermally-grown SiO2 layer on top and immediately cleaned with solvents and spin coated with Poly(methyl methacrylate) (PMMA) to act as a temporary passivation to BP as well as an electron-beam resist for the following pattering step. We then defined a pattern in the PMMA mask using electron-beam lithography (EBL) and deposited 1.5 nm of Al via electron-beam evaporation, followed by removal of the PMMA mask in acetone. The thin layer of Al reacts with air and forms 4-5nm of Al2O3 (verified by AFM in Figure S1) which has been shown to protect BP from degradation.30,31 Once the Al2O3 protection layer has been formed, the cyclic oxidation / annealing procedure is performed as shown in Figure 1a. One cycle consists of a ~10 minute exposure to ambient atmosphere (where the environmental conditions are well-controlled at 20 ̊C and 45% relative humidity) followed by annealing in N2 (20 sccm) at 300 ̊C at a pressure of approximately 1 Torr for ~10 minutes. These


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time scales were arrived at experimentally, however, it was observed that the process is robust against variations in the air exposure time, as well as the N2 anneal time. Cycles can be repeated until the desired thickness is reached. For all samples, an in situ deposition of 15 nm Al2O3 via atomic layer deposition (ALD) was performed after the last annealing step. This final Al2O3 layer acts as a protection layer for the entire sample so that characterization can be performed. Figure 1b shows optical micrographs after each cycle in the thinning process for a BP sample that underwent a total of 7 thinning cycles displaying a change in contrast after each cycle. A 3D topographic AFM image of this sample is shown in Figure 1c. AFM was used to characterize the thinning process by extracting the etch depth and measuring surface roughness. To determine the resulting thicknesses and accumulated roughness, statistical data was taken from rectangular regions of BP patterned flakes. Figures 2a and 2b show a typical patterned flake after 7 thinning cycles and how the thickness and roughness data were extracted. A two-dimensional height distribution mapping technique was used to extract the thicknesses of the thick and thin regions of the patterned BP flakes (Figure 2b). The positions of the peaks indicate the thicknesses of the patterned BP flake in addition to the Al2O3 mask. Once the thickness of the Al2O3 mask is subtracted out, the thicknesses of the thick and thinned BP regions can be measured directly. Figure 2c shows the etch depth as a function of the number of thinning cycles collected across 11 patterned BP samples. The linear fit of the experimental data through the origin gives a slope of 0.51 ± 0.08 nm/cycle. Given the experimental interlayer spacing24 of 0.55 nm, this result suggests that the process is very close to removing one BP layer for each cycle. The surface roughness of the thinned BP flakes was also extracted from the AFM data to provide an indication of flake quality and to determine the uniformity of the thinning process. In


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the inset in Figure 2c, we plot the flake root-mean-square (rms) roughness after thinning vs. the etch depth. The roughness extracted using the GwyddionTM software package based upon the AFM scan from a roughly 2 × 2 µm2 area. The data show a slight increase in the roughness with accumulated etch depth, going from 0.5 nm roughness after 1.5 nm of etching to 0.8 nm roughness after being etched 5.7 nm. The average roughness of the passivated unetched BP is 0.44 nm so, after the removal of 10 layers, the maximum additional roughness (0.36 nm) remains less than the thickness of single layer. This slight increase in surface roughness could indicate some formation of non-volatile surface oxides during the air exposure step. One primary advantage of this cyclical thinning process is its robustness to changes in the air exposure time and anneal time. The robustness of the process against changes in air exposure time is understood qualitatively from the observation that highly repeatable thinning results have been achieved (Figure 3c) while there is uncertainty in the exact exposure time throughout the fabrication process, particularly during the Al2O3 pattering process before the first N2 anneal. Based upon this observation, we examined the sensitivity of the thinning process to the air exposure time in a more quantitative manner by repeating the patterned thinning process with an increased air exposure time of 30 minutes. Figure S2 shows a side-by-side comparison of two patterned BP flakes that underwent 4 thinning cycles, one using ~10 minute air exposure steps and the other using ~30 minute air exposure steps. The etch depths were 1.99 nm and 2.07 nm respectively indicating that the etch rate is robust to small changes in the air exposure time. This result is important in that it indicates that precise control over BP thickness can be achieved in a process that does not require precise calibrations of etch times. Overall, the combination of the linearity of the etch depth vs. cycle number, the low degree of accumulated roughness and the closeness of the etch depth per cycle to the known interlayer


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spacing, provides evidence that the etching method could proceed in a layer-by-layer fashion. However, a comprehensive photoluminescence study revealing the optical band gaps of thinned BP flakes as well as the peak sharpness indicating the thickness uniformity would be necessary for further confirmation of layer-by-layer thinning and the increase in band gap of the thinned BP flakes. XPS measurements would also be important for detecting the presence of stable oxide species on the BP surface.17,26 Of course, because each cycle takes 20 minutes, this is an inherently slow thinning process and is not practical if deep etching is required. However, the slowness and controllability of this method becomes advantageous when precise control over the number of layers is desired. In addition to precise thickness control, another benefit offered by this thinning process is its ability to provide high spatial pattern resolution. Figure 2d shows an example of sub-150-nm lateral features consisting of 8-nm and 10-nm BP regions defined using electron-beam lithography. Further scaling is possible with optimization of the resist development and lift off processes, and therefore we believe this process could readily be scaled down to few-nanometerscale dimensions. We also note that this thinning process could be utilized to create self-aligned heterostructures, where the thinned region is aligned to the edge of a gate or contact in a device. This type of self-alignment could allow the device to be contacted in a thick, small band gap region while creating a thin, large band gap channel via the cyclical thinning process. Scalability like this is essential for fabricating high performance devices including scaled heterostructure MOSFETs or heterostructure tunneling field effect transistors (TFETs) and could also be interesting for exploring optical applications such as BP quantum well heterostructures and superlattices.


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The slow, cyclical nature of this thinning process also makes it an attractive method to consistently produce ultra-thin BP films. The tunable band gap of BP makes it interesting for optoelectronic devices from the mid-IR range to the visible range. However, if one wants to optimize devices for NIR and visible applications, ultrathin flakes are required. For example, a 4nm flake is predicted to have a band gap of ~0.8 eV which corresponds to an optical wavelength of about 1500 nm. 32 Our cyclical annealing thinning process shows promise in being able to achieve these flake thicknesses, as well as provide the ability to pattern large flakes and make novel heterostructures. Figure 3 shows the method by which ultra-thin BP flakes were fabricated and characterized. For these devices, a BP flake with some degree of spatial thickness variation was exfoliated and transferred to a SiO2 substrate (Figure 3a). 5 thinning cycles were used to thin the flake (Figure 3b) and then the BP was passivated by exfoliating and aligning a 17-nm-thick sheet of hexagonal boron nitride (h-BN) as shown in Figure 3c h-BN has previously been shown to be an effective passivation layer for BP 33 and produces a high quality interface with BP enabling Raman spectra, PL, and AFM measurements to be obtained on ultra-thin flakes.31 After h-BN passivation, the integrity of the ultra-thin BP flake was examined using AFM and Raman spectroscopy. Figure 3d shows the AFM topographic map of the h-BN passivated BP flake, indicating two lines in which the step heights were extracted. Figure 3e shows the thicknesses in these regions to be 1.6 nm and 7.3 nm in regions 1 and 2 respectively. In order to confirm that the thinned region contained crystalline BP (rather than an oxidized or amorphous layer), Raman spectra were collected from the two regions where the thicknesses of the BP were extracted. These results are plotted in Figure 3f where in both the 7.3-nm and 1.6-nm-thick regions, the in-plane A 2g and B2g modes and out of plane A1g mode are clearly visible, along with the Si substrate peak. A decrease in the A1g to Si peak ratio peaks was observed for the thinner


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flake, as expected due to a decrease in optical absorption as the BP gets thinner. Similar results have been reported by Favron, et al..22 The ratio of the A 2g to the A1g peak was also used by Favron, et al. as a measure of the BP oxidation where they indicated that A2g /A1g ratios > 0.2 are characteristic of low oxidation levels. Spectra from regions 1 and 2 show A 2g/A1g ratios of 0.31 and 0.74 respectively indicating low oxidation levels. The observation of the characteristic Raman peaks and A

2 g

/A1g > 0.2 in the thinned BP sample provide strong evidence that the cyclical

oxidation and annealing thinning process produces high purity BP layered crystals. Next, we use the thinning process to create lateral heterostructures in BP in order to observe the effects of the cyclic annealing thinning process on electrical performance as well as demonstrate a novel heterostructure MOSFET. To make this device, we first exfoliate and transfer BP onto a 290 nm SiO2/Si using the same transfer methods described in the previous section. Once a suitable thick flake was identified via optical microscopy, PMMA was spincoated and EBL was used to open patterns for two contacts. Ti/Au contacts (10 nm /45 nm) were then deposited using an electron-beam evaporation and liftoff process. Next, as shown in Figures 4a and 4b, the patternable cyclic oxidation/annealing procedure described previously was used to passivate the contacted regions of the flake and then thin the exposed region down. After the region was thinned, the same EBL/evaporation process was used to deposit two new contacts on the thin region. The two pairs of contacts were designed and positioned so that, not only could transport across the heterojunction be measured, but transport in thick and thin regions could also be measured independently. Following deposition of the contacts onto the thin region the device was passivated with 20 nm of Al2O3 using ALD. Figure 4c shows an optical micrograph of one of the completed devices.

Results and Discussion


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All device measurements were performed using an Agilent B1500A semiconductor parameter analyzer at vacuum levels less than 10-5 Torr. First, in order to examine the effect of thinning on homojunction BP MOSFETs, the transfer characteristics in the thick and thin BP regions were measured. It is important to note that since 290 nm of SiO2 was used as the gate dielectric, the gate capacitance is very low in comparison with other high performance BP MOSFETs fabricated using thinner SiO2 gate dielectrics or high-k gate dielectrics such as HfO2. This low capacitance results in high turn-on voltages, high subthreshold slopes, and low transconductance but still allows for analysis of the thick and thin BP channels through observing the ON-current and the ON/OFF ratios of the devices. Figure 5a shows the drain current, ID, vs. gate-to-source voltage, VGS, for the device in Figure 4 (device #1) at a drain-to-source voltage, VDS, of −0.1 V. A decrease in the OFF current and an increase in ON/OFF current ratio is observed after thinning. To calculate the ON/OFF current ratio, the OFF current was taken as the minimum current value, within the range of VGS values measured, while the ON current was taken as the ID value at a value of VGS that is 50 V more negative its value at the minimum current. After thinning, the ON/OFF ratio of device #1 increased from ~ 3.2 in the thick (11.7 nm) region to 2.8 × 103 in the thin (8.7 nm) region. The ID vs. VGS curves for the same device at VDS = −2.0 V are shown in Figure 5b and the results show that ON/OFF ratio is generally maintained, though the ambipolar behavior in the thinned region was enhanced compared to lower bias. A similar analysis was applied to a different device (device #2) and these results are shown in Figures 5c and 5d for VDS = −0.1 V and −2.0 V, respectively. Here, the ON current was taken as the ID value 80 V more negative than the minimum current value. The unthinned region had an ON/OFF ratio of 464 at VDS = −0.1 V, which is consistent with its smaller starting thickness


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(10.6 nm) compared to device #1. The thinned region, which had thickness of 6.9 nm, had an ON/OFF ratio of 4.9 x 104, once again, consistent with the results from device #1. For device #2, the improvement in ON/OFF ratio was maintained very well at VDS = −2.0 V as shown in Figure 5d. For both device #1 and #2, incomplete turn-off was observed in the thick regions, likely due to incomplete channel pinch off resulting from the thicker body and narrower band gap which prevents the channel from being fully depleted. After thinning, the ON/OFF current ratio improvement can be attributed to both the thinner BP, which ensures that the channel is fully depleted enabling complete channel pinch-off, as well as the wide band gap in the thinned regions. For example, A. Penumatcha, et al. extracted the BP band gaps from a Schottky barrier MOSFET model and found a band gap of ~0.5 eV for a 9-nm BP device and a band gap of ~0.6 eV for a 7-nm BP device.32 The thinned devices also show an improved subthreshold slope, which has also been shown to be associated with an increasing band gap in BP as thickness is decreased. Unfortunately, while the ON/OFF current ratio improves, the overall ON current decreases after thinning due in part to the increased Schottky barrier height between the Ti source contact and the valence band of the BP, which results in a more resistive path for carriers to be injected. An energy band diagram depicting the metal-semiconductor interface at the source is shown in Figure 6 and displays this idea clearly. Higher work function metals could be used to improve this trade-off in p-MOSFETs, however, lack of band-edge metals for contacting BP puts limitations on this method. In addition to an increased Schottky barrier height, the ON-current also may decrease because of a lower BP channel mobility. The mobility of BP decreases with a decrease in flake thickness9, but a decrease in mobility could also be attributed to BP degradation during the thinning process. The field-effect mobility values for the thick and thinned BP MOSFETs shown in Table 1 are in general agreement with that trend. The mobility was


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extracted from the transconductance of the BP MOSFETs in the linear regime (VDS = ‒0.1 V). The mobility is observed to drop after thinning, however additional studies are needed to determine to what extent the mobility degradation is due to the thinning process vs. simply the changes in band structure and scattering due to the absolute thickness of the sample itself. The above results suggest it would be desirable to achieve increased ON/OFF current ratio without sacrificing ON current, a result that can potentially be achieved by utilizing a heterostructure device configuration. To investigate this possibility, we fabricated a heterostructure device (device #3) with a 12nm-thick BP region and a thinned BP region that was 7.8 nm thick and measured the ID vs. VDS device characteristics and the ID vs. VGS device characteristics. We note that the sample was not passivated with a final ALD Al2O3 layer for these measurements in order to prevent any n-type doping in the thin channel from the ALD deposition process. Initially, the ID vs. VDS characteristics of the heterostructure device were measured, where the drain contact was the 12-nm-thick BP region and the source contact was the 7.8-nm-thick BP region and the drain-to-source voltage is swept from −1 V to +1 V. The characteristics are shown for VGS = −80 V and VGS = 0. Figures 7a and 7b show that the ID vs. VDS curve exhibits strong asymmetry with rectification on the order of 102 at VGS = ‒80 V and 103 at VGS = 0. This rectification can likely be explained by band gap asymmetry in the thick and thin BP regions. The band diagrams in Figure 7c show the anticipated band diagrams and the potential origin of the asymmetry. For the forward bias condition, the current initially increases exponentially, which can be attributed to an increase in thermionic emission of holes over the heterojunction barrier as the bias is increased. At higher values of VDS, the bias is high enough that the holes are largely unaffected by the energy barrier in the middle of the channel, and so the current is limited only by the small Schottky barrier to the narrow-gap BP at the drain. At sufficiently high bias, the current increase


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becomes more linear with VDS as the drain injection barrier becomes more transparent. In the reverse bias condition, the hole current injection from the source is suppressed due to the fact that the Schottky barrier for holes is now higher due to the presence of a larger band gap. These characteristics provide further confirmation of the enlargement of the BP band gap with thinning and shows how carrier transport is affected by the heterostructure. Next, we measured the ID vs. VGS characteristics of the device using four different contact combinations: two homojunction configurations where the source and drain contacts are both made to the (1) thick and (2) thin BP regions and two heterojunction configurations with (3) thin BP source / thick BP drain and (4) thick BP source / thin BP drain. Figure 8a shows the pMOSFET ID vs. VGS characteristics at VDS = −2 V for configurations (1)-(4). Here, VGS was swept from −80 V to +80 V, while VDS was kept at a constant −2V. For the thick homojunction device (config. #1), high current drive is obtained, but the gate is unable to completely turn off the channel. Conversely, the thin homojunction device (config. #2) shows good turn-off behavior, but the on-state current is roughly two orders of magnitude lower than the thick BP device. However, the heterojunction device with thick BP source and thin BP drain (config. #3) demonstrates the benefit of the heterojunction geometry. In this device, on-state current close to that of config. #1 is achieved, while excellent ON/OFF current ratio is obtained. Finally, config. #4 displays both low current drive and increased ambipolar current, as expected from a device with wide band gap source and narrow gap drain. The chart in Figure 8b shows a quantitative comparison of the device performance in the different contact configurations. Most importantly, the chart shows that the heterojunction configuration (config. #3) increases the ON/OFF ratio by over 103 in comparison to config. #1, while only slightly reducing the on current from 55 µA/µm to 37 µA/µm. Overall, these improvements in ON/OFF current ratios and ON-current are


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consistent with expectations based upon the change in band gap and Schottky barrier heights with BP thickness. The BP heterostructure device concept shown in this work exemplifies the usefulness of the cyclical thinning method in that precise control of the BP thickness at the drain of a MOSFET can be used to improve the subthreshold device performance. This scheme could be used to optimize conventional BP MOSFETs, and improve performance in other as novel electronic devices such as TFETs. For conventional MOSFETs, the heterostructure can be used to suppress leakage from the drain contact commonly called gate-induced-drain-leakage (GIDL) by increasing the semiconductor band gap in the drain contact region. Not only can this improve the ON/OFF ratio as we have demonstrated here, but suppression of GIDL could help ensure that the devices can achieve ideal subthreshold slope. Related work by our group has shown that excess GIDL current that occurs before turn-off of the source injection can actually lead to subthreshold slope > 60 mV/decade, particularly at high drain bias.34 In BP, the absence of band-edge contact metals and a narrow band gap make GIDL current and its effects particularly problematic. It should be noted that thinning will also result in a decrease in mobility in the thinned regions, however, devices could be designed such that only the region directly under the drain is thinned, thereby minimizing any potential impact to the ON-state current of the device. This same heterostructure principle has been used to enable TFETs in other materials systems with sub-60mV/decade subthreshold slope.35,36 TFETs with BP channels have been theoretically studied and have been predicted to provide enhanced performance compared to other material systems,37 and it is expected that the addition of a heterostructure could further enhance the performance by suppressing ambipolar leakage currents.


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BP heterostructures similar to the one shown in this work could also have a broad range of applications for optoelectronic devices. Heterostructure BP photodetectors with wide-gap contacts could be used to suppress dark current while utilizing the direct band gap of BP to efficiently absorb light. Perhaps the most exciting possibility is the potential to realize a doubleheterostructure suitable for use in light emitting diodes and lasers. Since it is expected that the band gap increases in an approximately symmetric fashion between conduction and valence bands,32 this indicates that thin/thick BP heterostructures create type-I heterostructures which are necessary for spatial confinement of electrons and holes. Efficient BP light emitters could create a whole new platform for 2D photonic circuits and their integration with existing CMOS technology.

Conclusion In this work, we utilize BP’s inherent reactivity with ambient atmosphere we created a cyclical, patternable thinning process. We show high resolution (sub-150 nm) patterns which could be scaled further by optimization of the EBL process. The thinning process has produced flakes as thin as 1.6 nm and shows promise for use in visible and near-IR tunable optical devices. The cyclical thinning process was also used to create the first ever heterostructure MOSFET which shows improved ON/OFF current ratios while maintaining a high ON-current in comparison with homojunction BP MOSFETs. Future work will include using methods such as XPS and PL spectroscopy to explore the thinned BP material quality and band gap. Other applications of the patternable cyclical thinning process in devices such as tunneling field-effect transistors and double heterostructure lasers should also be explored..

Supporting Information


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Supporting information includes: additional MOSFET characterization, photoluminescence characterization and plots relating to the AFM BP thickness extractions.

Corresponding Author * Phone: (612) 625-1316. Fax: (612) 625-4583. E-mail: [email protected].

Author Contributions M.C.R. and S.J.K. designed and directed this study and analyzed the results. M.C.R. fabricated all patterned BP samples and the MOSFET device. M.C.R. and S.N. performed all material characterization. M.C.R. and S.J.K. performed all electrical measurements. M.C.R., S.J.K. and S.-H. O. wrote the manuscript.

Competing Interests The authors declare no competing financial interests.

Acknowledgement This work was partially supported by the Air Force Office of Scientific Research under Award No. FA9550-14-1-0277, the National Science Foundation (NSF) under grant No. ECCS1102278, and the NSF through the University of Minnesota MRSEC under Award No. DMR1420013. Device fabrication was carried out in the Minnesota Nano Center, which receives partial support from NSF through the National Nanotechnology Coordinated Infrastructure (NNCI).


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