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May 12, 2016 - However, a detailed signature of oxide traps like capture cross-section, donor/acceptor behavior and profile in the bandgap, is not yet...
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Density and Capture Cross-Section of Interface Traps in GeSnO2 and GeO2 Grown on Heteroepitaxial GeSn Somya Gupta,*,†,‡ Eddy Simoen,†,§ Roger Loo,† Oreste Madia,∥ Dennis Lin,† Clement Merckling,† Yosuke Shimura,†,∥,# Thierry Conard,† Johan Lauwaert,⊥ Henk Vrielinck,§ and Marc Heyns†,‡ †

Imec, Kapeldreef 75, Leuven B-3001, Belgium Department of Metallurgy and Materials Engineering (MTM), KU Leuven, Kasteelpark Arenberg 10, Leuven B-3001, Belgium § Department of Solid State Sciences, Ghent University, Krijgslaan 281/S1, Gent B-9000, Belgium ∥ Department of Physics and Astronomy, KU Leuven, Celestijnenlaan 200D, B-3001 Leuven, Belgium ⊥ Department of Electronics and Information Systems, Ghent University, Sint-Pietersnieuwstraat 41, B-9000 Gent, Belgium ‡

S Supporting Information *

ABSTRACT: An imperative factor in adapting GeSn as the channel material in CMOS technology, is the gate-oxide stack. The performance of GeSn transistors is degraded due to the high density of traps at the oxide-semiconductor interface. Several oxidegate stacks have been pursued, and a midgap Dit obtained using the ac conductance method, is found in literature. However, a detailed signature of oxide traps like capture cross-section, donor/acceptor behavior and profile in the bandgap, is not yet available. We investigate the transition region between stoichiometric insulators and strained GeSn epitaxially grown on virtual Ge substrates. Al2O3 is used as high-κ oxide and either Ge1−xSnxO2 or GeO2 as interfacial layer oxide. The interface trap density (Dit) profile in the lower half of the bandgap is measured using deep level transient spectroscopy, and the importance of this technique for small bandgap materials like GeSn, is explained. Our results provide evidence for two conclusions. First, an interface traps density of 1.7 × 1013 cm−2eV−1 close to the valence band edge (Ev + 0.024 eV) and a capture cross-section (σp) of 1.7 × 10−18 cm2 is revealed for GeSnO2. These traps are associated with donor states. Second, it is shown that interfacial layer passivation of GeSn using GeO2 reduces the Dit by 1 order of magnitude (2.6 × 1012 cm−2eV−1), in comparison to GeSnO2. The results are cross-verified using conductance method and saturation photovoltage technique. The Dit difference is associated with the presence of oxidized (Sn4+) and elemental Sn in the interfacial layer oxide. KEYWORDS: virtual Ge substrate, GeSn, interface traps Dit, DLTS, capture cross-section switches like p-tunnel field-effect-transistors (pTFET)4,5and mid-infrared lasers3 to beyond 14 nm node devices and electronic-photonics integrated circuits (EPICs). The monolithic integration is facilitated as state-of-the-art growth of GeSn relies on heteroepitaxy, using strain relaxed Ge buffers on Si as virtual substrates.6 However, despite the elucidated promises of GeSn, one significant challenge which remains, is the capability to form a

H

istorically, nFETs have always outperformed pFETs because of the lower hole mobility in Si. This performance gap is narrowed by introducing compressive strain and higher hole mobility materials, and with a consensus, Ge has emerged as best option for pFETs in the past decade. Lately, a narrow bandgap semiconductor, Ge1−xSnx, comprising alloys of Ge and α-Sn (referred to as GeSn) is gaining interest for pFETs, because under compressive strain it has higher a hole mobility in comparison to Ge.1,2 Further, determined by the degree of strain relaxation and Sn content, the transition from indirect-L to direct-Γ bands takes place.3 By obtaining a direct bandgap, GeSn extends its scope with transport based © XXXX American Chemical Society

Received: February 9, 2016 Accepted: May 12, 2016

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DOI: 10.1021/acsami.6b01582 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ACS Applied Materials & Interfaces Table 1. Summary of Interface Trap Density (Dit) As Reported in the Literature for GeSn ref Gong

11

Lee13 Han1 Wirths15 Merckling7 Gupta12

Gupta Fang9

8

IL SiO2/Si SiO2 Si Cap GeOy Ge Cap native GeSnOy native GeOy GeOy GeSnOy

3.6 nm HfO2 Yb2O3 4 nm HfO2 HfO2 9 nm Al2O3 8 nm Al2O3

Cox (μF/ cm2)b

Dit (cm−2eV−1)a

Hκ

techniquec

σd

Sn content (%)

straine

structuref

1.7 × 10 (MG)

2.2

CP

3

F.S

pFET

∼4 × 1011(MG) 1.9 × 1012(MG) 5 × 1012(MG) 2 × 1012(MG), ∼1 × 1013(VB) 2 × 1012(MG), 1.3 × 1013(CB)

5 2 1.5 0.6

Gp/ω−ω CP Gp/ω−ω Gp/ω−ω Gp/ω−ω

5 5.3 6 5 5

−0.22% F.S +0.4% F.S −0.7%

pMOS-CAP pFET pMOS-CAP pMOS-CAP nFET

0.8

Gp/ω−ω

8.5

F.S

0.4

Gp/ω−ω

4.5

pMOS-CAP, nFET nFET

12

8 nm Al2O3 ∼7 × 1012 (CB) 1 nm Al2O3 ∼3 × 1011 (MG), ∼4 × 1011(CB) ∼2 × 1011 (VB) 20 nm 5.3 × 1011 (MG) Al2O3

σGe

a MG, VB, and CB represents interface states at midgap, close to valence band or conduction band, respectively. bCox is the capacitance at accumulation bias. If Cox < q.Dit, the measured impedance is dominated by Cox and thus Dit is underestimated. cGp/ω−ω and CP refers to ac conductance and charge pumping techniques, respectively. dσ is the capture cross-section. e(+) strain is tensile and (−) is compressive. F.S, fully strained. fFET is field effect transistor and MOS-CAP is metal-oxide-semiconductor capacitor.

overestimating the Dit. It is a shortcoming of the ac conductance technique that it cannot distinguish between response of minority and majority carriers. Second, slow traps with large time constants (>100 ms) cannot be measured using the ac conductance method.17 This explains the low Dit values, despite the overestimation due to minority response. And third, when the ac conductance technique is used, one has to assume the capture cross-section (σp) in order to calculate the Dit position in the bandgap. As seen from eq 1, σp can considerably shift the calculated Dit(Et − Ev) position w.r.t band edge. In this equation, ep is the hole emission time constant, vth is the thermal velocity, Nv is the density of valence band states, and k is the Boltzmann constant. The value of the assumed capture cross-section is unfortunately seldom stated in papers. We speculate that a capture cross-section (σp) of unstrained Ge is used (typically in order of ∼1 × 10−15 to 2 × 10−17 cm2).18

high quality oxide-semiconductor interface with sufficiently low interface state density (Dit).7,8 A high density of traps at the interface (Dit) and those bordering the interface (Nbt) is known to degrade the subthreshold swing.9 A reduction in mobility, caused by charging interface traps in strong inversion, in GeSn pFETs has also been reported.10 This negates the effect of alloying Ge with Sn. Therefore, if GeSn is to be incorporated in digital circuits, it is crucial at this point to analyze the oxidesemiconductor interface of GeSn. To obtain a low equivalent oxide thickness (EOT) in accordance with device scaling, Al, Yb or Hf based high-κ dielectrics, with or without surface passivation have been recognized as potential candidates.7−13 However, a high midgap Dit (>2 × 1012 cm−2 eV−1) is associated with the direct deposition of a high-κ oxide (Hκ) on GeSn7,12 and this has led to an interest in obtaining a good quality interfacial oxide layer (IL). To obtain an IL, a capping layer of Ge or Si is known to be deposited1,8 and then completely or partially oxidized. The marginal increase in EOT and in thermal budget due to the deposition step, is compensated by a reduction in Dit. Midgap Dit ranging from ∼4 × 1011 to 5 × 1012 cm−2 eV−1 has been reported at room temperature (RT) with varying IL and Hκ combinations (Table 1). Although a consensus of using IL on GeSn is apparent, the choice of IL still needs insight. In addition, due to the Dit dependence on strain, EOT thickness, and Sn % content,8 a careful comparison of the quoted Dit values in literature is necessary. In this work, we study the Dit for a gate stack consisting of 1.5 nm of GeSnO2 as IL,14 grown using molecular beam epitaxy (MBE) and 9 nm of Al2O3 as high-κ oxide (Hκ). The results are compared with a reference sample which consists of 1.5 nm of GeO2 as IL. In addition to those already elucidated in literature,16 we emphasize on three imprecisions introduced in the extracted Dit using the ac conductance technique, which is the predominant technique employed (see Table 1). First, the ac conductance technique is primarily used in depletion. In depletion, only one type of carriers (the majority carriers) fills/empties the traps because of the absence of minority carrier generation and ideally no gate leakage. However, for small bandgap materials, it has been shown that with increasing strain, minority carrier response onsets at lower bias,15 resulting in an obscure depletion regime. These minority carriers will lead to an increased parallel conductance in a MOS capacitor, thus

⎛ σpvthNv ⎞ ⎟⎟ Et − Ev = kT ln⎜⎜ ⎝ ep ⎠

(1)

Therefore, in this work, we use another well-established technique known as Deep Level Transient Spectroscopy (DLTS),19 to reliably extract the Dit. DLTS can distinguish the minority response from that of majority carriers and also distinguish the slow and fast interface traps. The steady state occupancy of the trap levels is changed using a DC bias in DLTS, whereas the ac conductance technique uses the gate voltage’s AC amplitude. We also report the capture crosssection for holes (σp) of Dit at the GeSn-oxide interface by measuring the capture kinetics with Isothermal Transient Spectroscopy (ITS). To the best of our knowledge, σp for Dit at the GeSn oxide interface has so far not been reported in literature. A nominal 40 nm thick, compressively strained and unintentionally doped, Ge0.92Sn0.08 layer is grown using chemical vapor deposition (CVD) on top of a strain-relaxed Ge(001) buffer (ν-Ge) on Si (001)6. The shallow ionized acceptor-type doping concentration (NA) is extracted to be 1.7 × 1016/cm3 from capacitance−voltage measurements at room temperature (RT). The p-doping arises from vacancy defects associated with dislocations, formed due to the lattice mismatch between Ge and Si. After CVD, an ex situ gate stack is processed in a molecular beam epitaxy (MBE) tool. The B

DOI: 10.1021/acsami.6b01582 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ACS Applied Materials & Interfaces

Figure 1. (a) High-resolution transmission electron micrograph (HR-TEM) showing the oxide-semiconductor interface for sample 1 with GeSnO2 as IL. The dark contrast in GeSn is due to roughness caused by focused ion beam milling during sample preparation. (b) XPS spectrum showing Sn4+ peak corresponding to SnO2 for the sample 1 with GeSnO2 as IL. The measurements are done after partial etching of Al2O3 to 5.5 nm to increase the depth resolution. Complete removal of the high-K oxide is avoided to prevent reaction of the etchant with the underlying oxide/substrate.

substrate is slowly heated to 500 °C for 30 min in ultrahigh vacuum, to thermally desorb the native oxide, which is confirmed by real time reflection high-energy electron diffraction (RHEED) analysis. The Ge0.92S0.08 surface shows a c(4 × 2) reconstruction as described previously7 and no Sn segregation is observed. X-ray diffraction and RHEED confirms the monocrystalline quality of GeSn prior and after heating, respectively. Samples are then cooled down to RT in UHV conditions. Subsequently, plasma oxidation at 150 °C is carried out to obtain 1.5 nm of Ge1−xSnxO2 (sample 1), as illustrated by transmission electron microscope image in Figure 1a. To obtain GeO2, Ge is grown on top of the GeSn layer using MBE just before plasma oxidation. The RHEED analysis shows the a(2 × 1) reconstruction as expected for Ge, confirming that no native oxide is present. Ge is then completely oxidized to obtain 1.5 nm of GeO2 (sample 2). Nine nanometers of Al2O3 is then deposited at 100 °C. Figure 1b shows the angle-integrated Xray photoemission spectroscopy (XPS) spectrum, revealing the presence of the oxidized state of Sn, (Sn4+ peak) at 486 eV for sample 1. Further, the thickness of the oxides is calculated from the intensity ratio of Ge4+ (Ge(Sn)O2) and Ge0 (GeSn), and is found to be 1.5 nm. No sub-oxides are present. Gate metallization with different contact areas is done using Ni through a shadow mask followed by a forming gas anneal at 400 °C for 25 min, to form MOS capacitors. The experimental capacitance voltage response in Figure 2 shows that the depletion capacitance is maintained in the inversion regime (positive voltage) at 1 MHz. It demonstrates that the minority carriers are not able to respond at high frequency, however, this does not exclude the possibility of minority carrier trapping by Dit. The absence of minority carrier’s contribution to the measured Dit is mediated below, using DLTS. Figure 3 shows the deep level transient Fourier spectroscopy (DLTFS) spectrum, over a continuously scanned temperature. b1 is the sine Fourier coefficient formed by numerical Fourier transformation of capacitance transient. The Fourier coefficient contains information about the entire transient at the particular temperature. The trap concentration is derived from the magnitude of b1.22,23 For analyzing traps at the oxidesemiconductor interface, the energy range in which carrier capture (or emission) by Dit takes place, is adjusted by the quiescent (VR) and filling pulse biases (VFILL). The sharp increase in amplitude of the spectrum at the lower temperature edge (70K), is observed when the filling pulse bias (VFILL) biases the capacitor in accumulation (−1.5 V). This response is

Figure 2. Experimental and simulated capacitance voltage (C−V) characteristics of a MOS capacitor for sample 1(GeSnO2 as IL), at 1 MHz. The bias is applied to the gate. The flat-band voltage, Vfb = −0.05 V, is calculated from multifrequency (C−V) curves.20 The simulated C−V profile is used to obtain the surface potential (φs) as shown in the inset.

Figure 3. Fourier transform DLTS spectra of the 600 μm diameter MOS capacitor with GeSnO2 as IL (sample 1). The quiescent reverse bias pulse is 2 V (VR). The filling pulse (VFILL) biases the capacitor in accumulation (−1.5 V, filled squares) and depletion (0.5 V, open squares). A pulse duration of 100 μs is sufficiently long to completely fill the traps, as further shown in Figure 5. The peak at 70K is due to Dit. The H1 and H2 peaks at 130 and 160 K, respectively, visualized by using deconvoluted spectra (green lines) are due to bulk traps in the Ge buffer.21 The peak response at 250 K is due to slow states (Nbt) and is not discussed in this work. The inset shows the shift in peak position as a function of period width Tw. C

DOI: 10.1021/acsami.6b01582 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ACS Applied Materials & Interfaces

because interface traps are inherently point defects and their emission and capture rates are linearly dependent on the hole occupation of the defect level. Resultantly, ΔC(t) depends exponentially on time, during capture and emission, as given by eq 2.24 In eq 2, ΔC is the magnitude of the capacitance transient proportional to abscissa b1, cp is the capture rate, NA is the doping concentration, p is the accumulation hole concentration, and φS is the surface potential. For obtaining p at −1.5 V, φS of −0.07 V is calculated from simulated C−V characteristics using the method described in reference,25 as shown in Figure 2. Further, to determine the capture rate (cp) and capture cross-section, we assume an energy independent capture cross-section for the measured Dit(E) lying between a small energy range EFA and EFQ. The assumption is justified because the slowest capture (i.e., smallest σp) will govern the capture kinetics. The capture rate of majority carrier (hole) Dit traps for the GeSnO2 IL is determined to be 4.2 × 107 s−1 and a cross-section of 1.7 × 10−18 cm−2 is calculated. The small magnitude of the capture cross-section indicates that the traps are positively charged donor states (+/0) at the p-GeSn/gate oxide interface. This is in good agreement with discrete σp measured in literature on Ge MOS capacitors.26 Additionally, the capture cross-sections of Dit associated with GeSnO2 and GeO2 on GeSn exhibits only a factor of 2 difference.

associated with traps at the semiconductor-oxide interface. Resultantly, the response is absent when VFILL biases the capacitor in depletion (0.5 V). The inset in Figure 3 shows that Dit peak shifts to higher temperatures with decreasing period width (Tw) demonstrating the thermally activated nature of hole emission from the traps. Figure 4 illustrates that for p-type

Figure 4. Band bending and carrier distribution in (a) accumulation and (b) quiescent reverse bias. The empty circles represent traps at the oxide/semiconductor interface filled with majority holes. The filled circles represents traps occupied by electrons. Arrows (1) and (2) represents diffusion of majority holes across quasi neutral region, depending on gate bias. With alternating, VAcc and VR pulse, the Dit lying between EFA and EFQ are filled and emptied by holes.

ΔC ∝ (1 − exp(−c pt )), where c p = σpvthp andnd p ⎛ φ⎞ = NA exp⎜ − s ⎟ ⎝ kT ⎠

GeSn, with an accumulation filling pulse the Dit hole traps in the lower half of the bandgap are probed. The studied Dit lie within the energy window between EFA and EFQ, which corresponds to Fermi levels at filling pulse bias (in accumulation) and quiescent reverse bias. The observed concentrations corresponds only to majority carrier traps. This is because at 70 K, there will be no thermal generation of minority carriers across the bandgap. Additionally, minority carriers generated by gate leakage will manifest itself as a negative peak in the DLTS spectrum, if captured by electron traps. Further, the long filling pulse duration of 100 μs used in Figure 3 ensures that the traps are completely filled. This is confirmed by the onset of saturated capture kinetics at 1 μs, as seen in the isothermal spectrum (ITS) of Figure 5. In Figure 5, the observed exponential capture is a typical signature of Dit,

(2)

Further, assuming a temperature independent capture crosssection, the energy dependence of Dit can be obtained using eqs 1 and 3. The hole mass (mdh = 0.3834 mo) is interpolated from ∼ theoretical curves27 for calculating Nv.24 In eq 3, b1 is the continuous coefficient, and is dependent on measurement conditions. It is numerically determined to be −0.7533 (see ref 22 for details). A is the area of the capacitor. The permittivity εGeSn = 16.64 is calculated based on a linear interpolation as a function of Sn content (x).28 Dit = −

εGeSnANACox b1 ∼ kTC R3 b1

(3)

Figure 6a shows the Dit profile obtained for GeSnO2 and GeO2 IL capacitors with respective capture cross sections. The Dit has a continuous energy distribution and increases toward the valence band edge (Ev). The lower Dit observed for GeO2 makes it a more suitable candidate for IL passivation in comparison to GeSnO2. To further substantiate the results as obtained by DLTS, Dit is also obtained using the conductance technique as shown in Figure 6b. As elucidated earlier, the conductance technique fails to distinguish between minority and majority carrier response and as a result a higher Dit is obtained in comparison to that extracted from DLTS. In corroboration with results obtained using DLTS, a higher trap density is measured for sample 1 with GeSnO2 as interfacial layer. The increase in trap density toward the valence band edge is also confirmed by the saturation photovoltage technique (SPV).17 Because the SPV technique collectively measures fast traps at the interface (Dit) and the slow traps present in the oxide (Nbt), an expected higher defect density (4×) is obtained, in comparison to DLTS. The presence of border traps, though not discussed in this work, is also established by DLTS as shown in Figure 3. The

Figure 5. Fast pulse isothermal spectrum (ITS) at 70 K, showing observed experimental capture kinetics of interface states. The solid lines shows the exponential fitting. D

DOI: 10.1021/acsami.6b01582 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ACS Applied Materials & Interfaces

Figure 6. (a) Profile of Dit as a function of energy position in the bandgap, obtained using DLTS. (b) The profile of traps obtained using SPV and conductance technique. The SPV technique could not be employed to extract Dit for sample 1 with GeSnO2 as IL, because of the observed Fermilevel pinning likely due to the higher density of interface traps. The energy position is extracted using the measured surface potential in b. The inset shows the conductance (/ω,ω) plot for the capacitor with GeO2 as IL exhibiting a conductance peak due to the energy losses associated with the change in the occupancy of the traps.

Present Address

same are known to be abundant in Ge-based/high-κ dielectrics.17 We attribute the high Dit in the GeSnO2 IL in comparison to GeO2 IL to the presence of Sn in elemental (Sn0) and/or oxidized (Sn4+) states in the interfacial layer. Because the bond strength of Sn−O is experimentally found to be lower than that of Ge−O as 528/kJ mol −1 and 657 ± 4.6/kJ mol −1 respectively,29 the presence of Sn4+ in the interfacial layer facilitates dangling bond formation leading to its inferior quality in case of sample 1. Further, the intensity ratio of Sn4+ and Ge4+ obtained by angle integrated XPS is used to obtain the composition of Ge0.9Sn0.1O2 (referred to as GeSnO2) in sample 1, reflecting 2% higher Sn concentration in the oxide as compared to the crystalline Ge0.92Sn0.08 as obtained from the reciprocal-space XRD map (also see the Supporting Information). This indicates a Sn enrichment during the oxidation step, a phenomenon which has also been previously reported.30 The XPS results are obtained with a repeatability of 99%. The presence of the Ge-cap layer in sample 2 prevents Sn enrichment from the underlying GeSn during oxidation, leading to an IL with lower Dit. In summary, we show that the traps at the oxidesemiconductor interface of strained-GeSn, reveals significant difference for Ge-based interfacial layers, GeSnO2 and GeO2. With one order lower Dit (2.65 × 1012 cm−2eV−1), closer to the VB edge, GeO2 on GeSn is demonstrated to be a better interfacial layer oxide. Small capture cross-sections of 1.7 × 10−18 cm2 and 1.0 × 10−18 cm2 are measured for GeSnO2 and GeO2, respectively. The small capture cross-section indicates that Dit are single donor-like centers, capturing in neutral state (+/0) in the lower half of the GeSn bandgap. A u-shaped Dit distributed profile is foreseen from the literature, because of an increased tail of Dit at the band edges.

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#

Y.S. is currently at Department of Electronics and Material Science, Shizuoka University, 3−5−1, Johoku, Naka-ku, Hamamatsu, 432−8011, Japan. Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS The authors thank Dr. Matty Caymax from Imec and Prof. Valeri Afanasiev from KU Leuven for helpful discussions. The authors also thank Paola Favia from Imec for TEM.

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(1) Han, G.; Su, S.; Zhan, C.; Zhou, Q.; Yang, Y.; Wang, L.; Guo, P.; Wei, W.; Wong, C. P.; Shen, Z. X.; Cheng, B. High-Mobility Germanium-Tin (GeSn) P-Channel MOSFETs Featuring Metallic Source/Drain and Sub-370 °C Process Modules. IEEE Int. Electron Devices Meet. 2011, 16.7.1−16.7.3. (2) Liu, M.; Han, G.; Liu, Y.; Zhang, C.; Wang, H.; Li, X.; Zhang, J.; Cheng, B.; Hao, Y. Undoped Ge0.92Sn0.08 Quantum Well PMOSFETs on (001), (011) and (111) Substrates with in Situ Si2H6 Passivation: High Hole Mobility and Dependence of Performance on Orientation. Symp. VLSI Technol., Dig. Technol. Pap. 2014, 1−2. (3) Wirths, S.; Geiger, R.; von den Driesch, N.; Mussler, G.; Stoica, T.; Mantl, S.; Ikonic, Z.; Luysberg, M.; Chiussi, S.; Hartmann, J. M.; Sigg, H.; Faist, J.; Buca, D.; Grützmacher, D. Lasing in Direct-Bandgap GeSn Alloy Grown on Si. Nat. Photonics 2015, 9, 88−92. (4) Wirths, S.; Tiedemann, A. T.; Ikonic, Z.; Harrison, P.; Holländer, B.; Stoica, T.; Mussler, G.; Myronov, M.; Hartmann, J. M.; Grützmacher, D.; Buca, D.; Mantl, S. Band Engineering and Growth of Tensile Strained Ge/(Si)GeSn Heterostructures for Tunnel Field Effect Transistors. Appl. Phys. Lett. 2013, 102, 192103. (5) Yang, Y.; Su, S.; Guo, P.; Wang, W.; Gong, X.; Wang, L.; Low, K. L.; Zhang, G.; Xue, C.; Cheng, B.; Han, G.; Yeo, Y.-C. Towards Direct Band-to-Band Tunneling in P-Channel Tunneling Field Effect Transistor (TFET): Technology Enablement by Germanium-Tin (GeSn). IEEE Int. Electron Devices Meet. 2012, 16.3.1−16.3.4. (6) Vincent, B.; Gencarelli, F.; Bender, H.; Merckling, C.; Douhard, B.; Petersen, D. H.; Hansen, O.; Henrichsen, H. H.; Meersschaut, J.; Vandervorst, W.; Heyns, M.; Loo, R.; Caymax, M. Undoped and inSitu B Doped GeSn Epitaxial Growth on Ge by Atmospheric PressureChemical Vapor Deposition. Appl. Phys. Lett. 2011, 99, 152103. (7) Merckling, C.; Sun, X.; Shimura, Y.; Franquet, A.; Vincent, B.; Takeuchi, S.; Vandervorst, W.; Nakatsuka, O.; Zaima, S.; Loo, R.; Caymax, M. Molecular Beam Deposition of Al2O3 on P-Ge(001)/

ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.6b01582. Details about the XPS depth resolution plot (PDF)

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REFERENCES

AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. E

DOI: 10.1021/acsami.6b01582 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

Letter

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DOI: 10.1021/acsami.6b01582 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX