Direct Observation of CdCl2 Treatment Induced Grain Boundary

Article pubs.acs.org/JPCC

Direct Observation of CdCl2 Treatment Induced Grain Boundary Carrier Depletion in CdTe Solar Cells Using Scanning Probe Microwave Reflectivity Based Capacitance Measurements Mohit Tuteja,† Prakash Koirala,§ Vasilios Palekis,∥ Scott MacLaren,‡ Chris S. Ferekides,∥ Robert W. Collins,§ and Angus A. Rockett*,† †

Department of Materials Science and Engineering and ‡Frederick Seitz Materials Research Laboratory, University of Illinois, Urbana, Illinois 61801, United States § Department of Physics and Astronomy, University of Toledo, Toledo, Ohio 43606, United States ∥ Department of Electrical Engineering, University of South Florida, Tampa, Florida 33620, United States ABSTRACT: Device grade polycrystalline CdTe films, grown by rf-sputtering (yielding up to 13% efficient devices) and closespaced sublimation (CSS) (yielding up to 16% efficient devices), have been analyzed using scanning microwave impedance microscopy (sMIM). In order to study the effect of Cl on the electronic properties of grain boundaries in CdTe, sMIM based capacitance measurements were performed on the surfaces of asdeposited and CdCl2 annealed CdTe films. The measurements were performed with an sMIM instrument operating at ∼3 GHz probe signal frequency in conjunction with a combination of ac and dc voltage biases applied to the tip. It was found that CdCl2 annealed CdTe samples deposited using both CSS and sputtering exhibit carrier depletion along the grain boundaries as compared to the grain bulk. The grain boundary carrier depletion was not observed in samples that have not been CdCl2 annealed and hence have no incorporated Cl.

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INTRODUCTION Recently, 22.1% device efficiencies have been achieved in CdTe based solar cell fabrication.1 These high efficiency devices use CdTe in polycrystalline thin-film form as the active absorber layer. In polycrystalline photovoltaic (PV) materials, the electrical properties are often affected by the presence of twodimensional grain boundaries due to (a) photogenerated carrier recombination and (b) charge trapping and obstruction of carrier transport by localized grain boundary states in the energy bands.2 Despite these effects, polycrystalline thin-film CdTe solar cells regularly outperform their single crystal counterparts.3 There have been several investigations of the electrical properties of the grain boundaries in CdTe.3−8 Some of these studies suggest that grain boundaries can provide electrically active, low resistance conduction channels to the front contact.4 CdCl2 annealing is an important step in the device fabrication that leads to improved open circuit voltage, short circuit current, and fill factor of the device.9,10 It is widely accepted that the CdCl2 anneal treatment aids recrystallization of CdTe, can lead to an increase in its grain size, and enhance the minority carrier lifetime in the CdTe films, based on atomic force microscopy, scanning electron microscopy, X-ray diffraction, and time-resolved photoluminescence measurements.10−12 Recently, it has been demonstrated that post CdCl2 anneal the Cl incorporated in the CdTe film segregates along the grain boundaries,5,7,13 and the presence of Cl, an ndopant for CdTe, at grain boundaries results in local doping © 2016 American Chemical Society

type inversion/carrier depletion, resulting in p-doped CdTe grains separated by n-type/depleted p-type grain boundaries.3,7 Probing the properties of individual grain boundaries is difficult as most device characterization techniques measure macroscopic areas and hence yield results that are a convolution of the electrical properties of the grain bulk and grain boundaries. Individual grain boundary properties have been investigated via electron beam induced current (EBIC);5,7,14,15 combinations of scanning capacitance microscopy (SCM), conductive atomic force microscopy (C-AFM), and scanning Kelvin probe force microscopy;3,16,17 near-field optical beam induced current (OBIC);15,18 and scanning spreading resistance microscopy.19 These studies showed that the grain boundaries in CdTe are electrically active and provide efficient conduction pathways for electrons. Only SCM is capable of determining the carrier concentrations and type, but only a few SCM based studies have been reported focusing on the grain boundaries in CdTe.3,16 Thus, the electronic properties of grain boundaries in polycrystalline-CdTe and their role in photogenerated charge separation remain topics of wide debate. Previously, we reported on the observation of grain boundary depletion in sputter-deposited CdTe solar cells and demonstrated that scanning microwave impedance Received: January 27, 2016 Revised: March 14, 2016 Published: March 18, 2016 7020

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performance transmission line incorporating a specialized AFM tip with a shielded cantilever probe.32 In the current experiments, a low power (−5 dBm) rf signal at ∼3 GHz interacts with the sample, resulting in changes in reflection and absorption of the rf power. The reflected signal consists of an in-phase and out-of phase component, which contains information about the local permittivity (capacitance) and conductivity (resistance) of the sample. After proper calibration, using a purely capacitive (dielectric) sample made of Al2O3 dots on top of SiO2/Si, the capacitive and resistive channels are isolated, mapped spatially, and displayed independently. Further details of the microwave electronics, tuning, and calibration procedures can be found in refs 27 and 29. sMIM measurements were performed at the University of Illinois in an Asylum Research MFP-3D AFM using commercially available cantilevers from PrimeNano Inc. dC/dV measurements were performed in contact mode, with the conductive sMIM tip and the oxide coated sample effectively forming a metal−insulator−semiconductor (MIS) structure. The transparent contact (TCO layer) of each of the samples was electrically grounded, and a dc bias and/or a 250 kHz ac bias were applied to the tip. All ac bias voltage amplitudes given below are half of the peak-to-peak signal values; thus, a 1 V ac bias refers to sweeping the signal by ±1 V. The capacitance change caused by the ac bias was measured using a lock-in amplifier. A schematic of the experimental setup and the tip signal used to perform the measurements is given in Figure 1 of ref 8. The measured capacitance is composed of the capacitances of the oxide and the semiconductor space charge layer connected in series. Since the frequency of the capacitance probe signal is ∼3 GHz, we obtain the high f requency capacitance−voltage (C−V) behavior of the MIS structure in the sMIM capacitance (sMIM-C) channel.33,34 For only a dc bias (Vdc) applied to the tip, the capacitance response of the sample at Vdc is probed. Hence, by performing multiple scans while changing Vdc for each scan, we can acquire a C−V map of the sample area being scanned. For a combination of dc and ac biases applied to the tip and a lock-in measurement at the ac bias frequency, we probe the differential capacitance (dC/dV) signal, i.e., the slope of the C−V curve at Vdc. The magnitude of the dC/dV signal (|dC/dV|) resulting from a given change in tip voltage, due to the time varying ac bias, is a function of the carrier concentration of the semiconductor. The phase of the dC/dV signal (θc) is indicative of the type of dopant in the sample. Hence, we can measure the relative carrier concentration and type by spatially mapping the dC/dV amplitude and phase signal, respectively.34,35 In this configuration, our measurement is similar to open loop SCM imaging, but in SCM the bias is conventionally applied to the sample as opposed to the tip, as in our study. The shielded cantilever probe design used in sMIM also greatly reduces parasitic tip− sample coupling that leads to environmental noise pickup,27 hence yielding results superior to SCM. Previously, it has been shown that in dC/dV measurements using sMIM, the topographical artifacts do not obscure the electronic properties of the grain boundaries.8 The same is found in all results presented here. The data for CSS samples were acquired with a 1 V amplitude ac and no dc bias applied to the sMIM tip (applied voltage thus sweeping from −1 to +1 V), and a lock-in amplifier was used to measure the dC/dV signal. For rf-sputtered CdTe films 1.5 V ac and −2 V dc biases were applied to the tip to obtain the dC/dV signal. In all measurements presented here,

microscopy (sMIM) based high frequency differential capacitance (dC/dV) scan data can be used to investigate the local carrier concentration in CdTe.8 In order to clarify the effect of Cl incorporation on the electrical properties of the grain boundaries in CdTe, we compare close-spaced sublimation (CSS) and rf-sputtered thin-film CdTe, with and without CdCl2 annealing. This analysis was accomplished using sMIM, which is a scanning probe technique that enables highresolution nanoscale spatial mapping of carrier concentration. CdTe films, both with and without CdCl2 annealing, were analyzed by sMIM in order to ascertain the effects of CdCl2 on the electronic properties of the grains and the grain boundaries.

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EXPERIMENT The sputter-deposited CdTe films studied here were grown at the University of Toledo on commercial NSG-Pilkington TEC15 glass substrates coated with a SnO2 high resistivity transparent (HRT) layer. CdS and CdTe were sequentially deposited on these substrates by magnetron sputtering at a substrate temperature of 250 °C, an rf power of 200 W, and Ar pressures of 15/10 mTorr for CdS/CdTe depositions, respectively. One sample was taken out at this stage, and the other was subsequently CdCl2 treated by applying a saturated aqueous solution of CdCl2 to the CdTe film surface and by annealing in dry air for 30 min at 387 °C. sMIM measurements were performed on the surfaces of the CdTe films. Additional details of the deposition process along with process parameter correlations with device performance may be found in ref 20. The devices fabricated on the TEC-15/HRT using this procedure (after CdCl2 annealing) regularly exhibit an open circuit voltage (Voc) of ∼0.8 V, a fill factor (FF) of ∼70%, a short circuit current (Jsc) of ∼22−23 mA/cm2, and an efficiency of ∼12−13%. Higher efficiencies up to 14% have been achieved with this process using optimized ZnO:Al coated glass substrates.21 The CSS grown samples were fabricated on Corning EagleXG glass at the University of South Florida. Indium tin oxide deposited by sputtering was used as the transparent conducting oxide (TCO) front contact. CdS and CdTe were then deposited by chemical bath deposition and CSS, respectively. During CSS growth, the substrate temperatures were in the range of 550−600 °C and source temperatures in the 650−680 °C range. One sample was taken out at this stage, and the other was subjected to CdCl2 deposition by evaporation followed by annealing in He and O2 ambient (20% partial pressure of O2) at 400 °C for 30 min. Additional details of the growth process can be found in ref 22. Devices fabricated using this process (after CdCl2 annealing) regularly exhibit Voc ∼ 0.80−0.85 mV, Jsc ∼ 20−23 mA/cm2, FF ∼ 70−75%, and efficiency ∼ 11−15%. In the case of both CSS and sputtered CdTe films, prior to the sMIM measurements, a 5 nm thick layer of Al2O3 was grown on the CdTe surface using atomic layer deposition to enhance the capacitance signals. sMIM, a high-resolution cantilever based scanning probe technique, is a versatile variant of an array of recently developed near-field reflective microwave imaging technologies.23−26 It offers the ability to spatially map material permittivity and conductance with high sensitivities and signal-to-noise ratios at resolutions primarily limited by the tip size.27−29 sMIM is based on the reflection of electromagnetic radiation in the microwave wavelength regime at the interface between two materials, which offers insights into the electronic properties of materials.30,31 The high spatial resolution (≈50 nm) is provided due to near-field reflectivity imaging achieved by a high 7021

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The Journal of Physical Chemistry C the combination of ac and dc bias was chosen to maximize the dC/dV signal. The difference in bias values did not affect the qualitative behavior of the results. The AFM system was in a lightproof enclosure such that there was no external light source apart from the AFM tracking laser illuminating the sample. The AFM tracking laser wavelength is ∼850 nm (1.45 eV), which is slightly lower in energy than the band gap of CdTe (1.45−1.53 eV, depending on film stress);20,22,36 thus, no appreciable amount of photocarriers were generated by that laser. In addition, the laser spot was carefully centered on the cantilever such that the overflow of the laser over the sides of the cantilever was minimized.

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RESULTS AND DISCUSSION Figures 1a−d show the simultaneously acquired |dC/dV| and AFM topography signals overlaid for the as-deposited and Figure 2. Corresponding sMIM dC/dV phase plots overlaid on AFM topographic images for the four samples studied. For larger grains, the entire grain usually shows a slightly higher phase contrast compared to smaller grains. There is some correspondence with the amplitude data such that areas close to grain boundaries tend to show lower phase angles. However, the appearance of the phase plots is quite distinct from the amplitude plots. The as-deposited CSS film shows contrast in phase image but not in the amplitude plot. Note: the color bar is common for all images and is centered at 0°. The actual variation from the center of the scale bar is ±2°, ±8.5°, ±6°, and ±8° for (a)−(d), respectively, over the scan area. Sample grain (G) and grain boundary (GB) positions are marked.

exhibit a lower majority carrier concentration than the grain bulk. Further, the corresponding θc images, shown in Figures 2b and 2d, for the CdCl2 annealed samples exhibit at most a phase variation of only 16° and 17°, respectively, throughout the scan area. Although the phase signal is slightly lower along the grain boundaries as compared to the grains, a 16° or 17° phase difference is not indicative of a dopant-type inversion as dopant-type inversion warrants a phase flip of ∼180°. This follows directly from the mirror image like nature of the C−V curves for the n- and p-doped semiconductor samples along the capacitance (y) axis. Figures 1a and 1c show the |dC/dV| signals obtained from rf-sputtered and CSS-grown CdTe films, respectively, without CdCl2 annealing. The CSS-grown samples, with and without CdCl2 anneal treatment, share similar rms surface roughness values of 145 and 163 nm, respectively, but as can be seen from Figures 1c and 1d, the grain boundaries in the CSS grown CdTe films do not exhibit reduced carrier concentrations (higher |dC/dV| signal) in the non-CdCl2 annealed sample. Similarly, grain boundary carrier concentration reduction is not observed in rf-sputter deposited CdTe sample without the CdCl2 annealing, as can be seen from Figure 1a. This reduced majority carrier concentration along the grain boundaries in the CdCl2 treated samples coupled with the lack of dopant-type inversion between the grains and the grain boundaries implies that the grain boundaries are less pdoped as compared to the grain bulk. Cl acts as an n-type dopant in CdTe,7 and upon CdCl2 anneal, Cl incorporated in CdTe segregates along the grain boundaries, as shown by electron energy loss spectroscopy,5,7,37 secondary ion mass spectrometry,13 atom probe tomography,38 and Auger electron spectroscopy39 measurements. The observation of lower carrier concentration along grain boundaries in both rf-sputtered and CSS-grown CdTe films

Figure 1. sMIM dC/dV amplitude data overlaid on AFM topographic images for the four samples studied. The signal qualitatively represents the hole concentrations, with high values representing low concentrations. The two CdCl2 annealed samples show increased amplitude in the grain boundaries while the as-deposited samples do not. The scan areas are 5 μm × 5 μm. The RMS roughnesses are 27, 144, 163, and 145 nm for (a)−(d), respectively. Note: the color bar is common for all images and is centered at 0 mV. The actual variation from the center of the scale bar is ±120, ±265, ±190, and ±240 mV for (a)−(d), respectively, over the scan area. Sample grain (G) and grain boundary (GB) positions are marked.

CdCl2 annealed CdTe samples grown using rf-sputtering (Figures 1a,b) and CSS (Figures 1c,d). Although the actual |dC/dV| signal ranges for Figures 1a−d are slightly different, they have been put on the same color scale to enable easy comparison. Figures 2a−d show the simultaneously acquired dC/dV phase angle, θc, signal overlaid on the AFM topography for the as-deposited and CdCl2 annealed CdTe samples, grown using rf-sputtering and CSS. Similar to |dC/dV| in Figures 1a− d, the θc signals in Figures 2a−d are plotted on the same scale for all samples. It is seen from Figures 1b and 1d that several areas in the CdCl2 annealed CdTe samples corresponding to the grain boundaries have much higher |dC/dV| signals than the grain bulk. A higher |dC/dV| signal corresponds to a steeper C−V curve, which is a result of lower local carrier concentration.34 Hence, Figures 1b and 1d show that the grain boundaries in CdCl2 annealed CdTe, grown using both rf-sputtering and CSS, 7022

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effectively acts as an electron reflector. However, both these alternate models rely heavily on the data obtained from the “front” CdTe surface that forms the interface with CdS. In the present article we study the “back” surface of the CdTe film, and our findings do not support the conclusions arrived at in refs 14, 15, 40, and 41. It is possible that the nature of the grain boundary electrical properties changes along the thickness of the CdTe film, but such a conclusion warrants further investigation into the depth dependence of the electrical properties of the grain boundaries in CdTe film, possibly on a bevel polished sample.

after CdCl2 annealing points to p-doping compensation due to incorporation of Cl, a donor impurity in CdTe. Further, this gives one explanation for the universally beneficial effect of CdCl2 treatment on the efficiencies of polycrystalline CdTe solar cells as the carrier depletion induces band bending along the grain−grain boundary interface. This promotes photogenerated charge carrier separation as electrons will segregate along the grain boundaries and holes will remain in the grain bulk. This effect is described in Figure 3. We note that the exact

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CONCLUSIONS We employed sMIM based dC/dV measurements to determine the electronic properties and associated relative carrier concentrations at grain boundaries with respect to the grain bulk in polycrystalline CdTe films. We found evidence of carrier concentration reduction along the grain boundaries in CdCl2 annealed CdTe films deposited by both sputtering and CSS. This effect was absent in samples that have not been CdCl2 annealed. Hence, we validate the hypothesis of grain boundary carrier depletion in CdTe caused by CdCl2 annealing, likely due to Cl incorporation. The carrier depletion creates band bending along the grain−grain boundary interface, which facilitates photogenerated carrier separation. Further it was shown that CdCl2 annealing increased the grain size for sputtered CdTe, likely generating carrier depleted grain boundaries that extend throughout the thickness of the CdTe film and hence enabling the formation of effective paths for electron flow. These two effects collectively explain the universally beneficial nature of the CdCl2 anneal treatment in relation to the device efficiency of polycrystalline CdTe solar cells.

Figure 3. A cartoon diagram representing the p-doped CdTe grains separated by the relatively carrier depleted/compensated grain boundaries in polycrystalline CdTe, likely due to Cl segregation along grain boundaries. The band bending at the grain boundaries favors the separation of photogenerated electrons and holes.

nature of the electronic properties of the grain boundaries is dependent on the nature of CdCl2 annealing, which determines the amount of Cl incorporated in the material, as a large amount of incorporated Cl will dope the grain boundaries ntype, as claimed in ref 7. A second explanation of the benefit of CdCl2 treatment is recrystallization of CdTe grains, hence increasing open-circuit voltage and grain size. This can be most directly observed by comparing Figures 1a and 1b, where it can be seen that CdTe grain size in sputter deposited films increases dramatically upon CdCl2 annealing. The grain coarsening also leads to a significant increase in surface roughness for the sputter deposited film upon CdCl2 annealing. The two effects of grain size increase and roughening do not occur, however, for the CSS deposited CdTe. It has been shown that the grain boundaries in CdTe provide low resistance paths for electrons to travel to the front contact,4 which indicates that it is better for CdTe devices to have large columnar grains with grain boundaries running throughout the thickness of the CdTe layer such that the photocurrent does not cross grain boundaries to reach a contact. It has been shown that the larger CdTe grains exhibit enhanced carrier depletion along grain boundaries and hence enable greater photogenerated carrier separation.8 Hence, an increase in the size of CdTe grains upon CdCl2 annealing also potentially influences the device efficiency and the current collection ability, at least in sputter deposited CdTe PV devices. It is worth mentioning that there are alternate theories about the electronic properties of the grain boundaries in polycrystalline CdTe. One model describes a stronger p-doping immediately next to the grain boundaries based on in-plane electrical characterization of the front (interface with CdS) surface of “lift-off” CdTe films.40,41 This results in an energy barrier to the flow of minority carriers just before the grain boundary. A second model supports the existence of enhanced p-doping at the grain boundaries as compared to the grain bulk by using EBIC and OBIC measurements,14,15 and the resulting upward band bending at the grain−grain boundary interface

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AUTHOR INFORMATION

Corresponding Author

*E-mail [email protected] (A.A.R.). Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS The authors are thankful for the financial support from the U.S. Department of Energy, Office of Energy Efficiency and Renewable Energy (Contract DE-EE0005405). The authors are grateful to Dr. David Strickler of NSG-Pilkington for supplying the TEC-15/HRT substrate materials, Dr. Ted Limpoco of Asylum Research, and Dr. Stuart Friedman of PrimeNano Inc. for useful suggestions. This work was carried out in part in the Frederick Seitz Materials Research Laboratory Central Research Facilities, University of Illinois.

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DOI: 10.1021/acs.jpcc.6b00874 J. Phys. Chem. C 2016, 120, 7020−7024