Double-Balanced Graphene Integrated Mixer with Outstanding

Sep 17, 2015 - A monolithic double-balanced graphene mixer integrated circuit (IC) has been successfully designed and fabricated. The IC ... It demons...
2 downloads 12 Views 6MB Size
Download PDF
Letter pubs.acs.org/NanoLett

Double-Balanced Graphene Integrated Mixer with Outstanding Linearity Hongming Lyu,*,† Huaqiang Wu,*,†,‡ Jinbiao Liu,§ Qi Lu,† Jinyu Zhang,† Xiaoming Wu,† Junfeng Li,§ Teng Ma,∥ Jiebin Niu,§ Wencai Ren,∥ Huiming Cheng,∥ Zhiping Yu,† and He Qian†,‡ †

Institute of Microelectronics, Tsinghua University, Beijing, China 100084 Tsinghua National Laboratory for Information Science and Technology (TNList), Beijing, China, 100084 § Institute of Microelectronics, Chinese Academy of Sciences, Haidian District, Beijing, China 100029 ∥ Shenyang National Laboratory for Materials Science, Institute of Metal Research, Chinese Academy of Sciences, Shenyang, China, 110016 ‡

S Supporting Information *

ABSTRACT: A monolithic double-balanced graphene mixer integrated circuit (IC) has been successfully designed and fabricated. The IC adopted the cross-coupled resistive mixer topology, integrating four 500 nm-gate-length graphene field-effect transistors (GFETs), four on-chip inductors, and four on-chip capacitors. Passive-first-active-last fabrication flow was developed on 200 mm CMOS wafers. CMOS back-end-of-line processes were utilized to realize most fabrication steps followed by GFETcustomized processes. Test results show excellent output spectrum purity with suppressed radio frequency (RF) and local oscillation (LO) signals feedthroughs, and third-order input intercept (IIP3) reaches as high as 21 dBm. The results are compared with a fabricated single-GEFT mixer, which generates IIP3 of 16.5 dBm. Stand-alone 500 nm-gate-length GFETs feature cutoff frequency 22 GHz and maximum oscillation frequency 20.7 GHz RF performance. The double-balanced mixer IC operated with off-chip baluns realizing a print-circuit-board level electronic system. It demonstrates graphene’s potential to compete with other semiconductor technologies in RF front-end applications. KEYWORDS: Graphene, mixer, integrated circuit, RF electronics t has been a decade since the first discovery of graphene1 which bears great expectations in high frequency electronics due to its irreplaceably high carrier mobility. However, even though graphene field-effect transistors (GFETs) have reached intrinsic cutoff frequency ( f T) higher than 400 GHz,2 the pace of the development of graphene radio frequency (RF) circuits seems slower. Questions are raised about the feasibility of using graphene in real RF communication systems. One obstacle is the integrated circuit (IC) process complexity. Aimed at two-dimensional materials, however, both Han et al. and our group have recently devised the passive-first-active-last fabrication flow for graphene integration.3,4 It utilizes standard silicon fabs to fabricate passive components, interconnects and buried gate structures, followed by chemical vapor deposition (CVD) graphene transfer and

I

© XXXX American Chemical Society

GFET-customized processes. Habibpour et al. demonstrated a graphene microwave IC in microstrip technology.5 However, it required unusual processes such as substrate thinning and through-substrate-via etching. Besides these groups, most graphene circuits are performed at equipment level with externally connected passive components, and limited to singletransistor designs. The fundamental process issue apparently hinders the progress of graphene electronics research. Another obstacle is concerned with the unique electronic property of graphene due to its absence of bandgap. The lack of current saturation hinders graphene’s progress in analog Received: June 24, 2015 Revised: September 14, 2015

A

DOI: 10.1021/acs.nanolett.5b02503 Nano Lett. XXXX, XXX, XXX−XXX

Letter

Nano Letters

Figure 1. Fabrication of the graphene IC. (a−d) Schematic of the inverted process. BEOL processes are used for passive components, necessary routings, and buried gates followed by GFET processes. (e) Photograph of the 200 mm wafer. (f) The integration flow.

amplifiers. Several groups made efforts to generate gains.6−8 With a standard surface mount inductor soldered on the input port, Andersson et al. proposed the first GFET amplifier matched to 50 Ω at microwave frequencies.6 The work of Han et al. was the first graphene IC able to perform amplification when loaded with 50 Ω impedance. However, the gain was barely 4 dB.3 These works simply adopted conventional topologies successful in traditional semiconductor technologies (e.g., Si CMOS), which were not intended for lack-of-saturation graphene situations. On the other hand, graphene passive circuits are promising. Pioneering works on graphene analog electronics led to the demonstration of graphene-based frequency doublers,9,10 modulators,11,12 and mixers.5,13−17 The frequency doubler utilizes the graphene’s unique property of electron and hole symmetry, and by superimposing an sinusoidal signal on the charge neutrality point (Dirac point), the drain current containing the double-frequency component is generated. Taking it one step further, several groups demonstrated binary digital modulation schemes, binary phase-shift keying (BPSK) and binary frequency-shift keying (BFSK).11,12 Graphene mixers are especially widely discussed.5,13−17 The mixer is a key component in virtually all telecommunication and radar equipment and limits the intermodulation performance of a receiver front-end. The most commonly used mixers in microwave systems employ Schottky-barrier diodes or active FETs as the mixing elements.18 Because these devices are very strongly nonlinear, the linearity of these active mixers is low. On the contrary, various semiconductor transistors, including MESFET, HEMT, and Si CMOS, have been used for resistive mixers in linear regions and achieve higher linearity.19−22 A 90 nm CMOS resistive FET mixer achieved third-order input intercept (IIP3) of 16.5 dBm at an LO power of 4 dBm and a conversion loss (CL) of 11.6 dB.21 Another resistive mixer fabricated in 90 nm SOI CMOS technology achieved an excellent IIP3 of 20 dBm.22 Graphene’s linear output characteristic makes it particularly suitable for this kind of circuit application. The lack of saturation, though detrimental

for conventional amplifier circuits, is now an advantage for resistive mixers. The circuit is also insensitive to operation bias parameters due to its passive nature. This feature is especially attractive for graphene at the present stage, as GFETs inevitably suffer from process variations. Pioneering works realized a resistive mixer with epitaxial graphene as the first graphene IC.16 Moon et al. demonstrated a record-high IIP3 up to 27 dBm17 and Habibpour et al. achieved functionality up to 30 GHz.5 A table comparing recent reports on graphene mixers is shown in Table S1 in Supporting Information. In this paper, we report a significant progress for the graphene resistive mixer. A four-GFET double-balanced mixer with cross-coupled structure is proposed to further enhance the linearity and generate output spectrum purity. The circuit integrated four GFETs, four on-chip inductors, and four onchip capacitors, being one of the most complex graphene ICs in literature. It achieved IIP3 of 21 dBm with a modest −2.6 dBm LO signal at 3.5 GHz. In comparison, a single-GFET mixer was also fabricated and characterized. IC Fabrication. The process for graphene IC integration is divided into two parts: structure patterning by CMOS backend-of-line (BEOL) technology and GFET processes. The essence of the integration scheme is reversing BEOL processes for passive components and interconnects and front-end-of-line (FEOL) processes for active transistors, as what we call “inverted process”.4 Schematic of the process flow is shown in Figure 1a−d. A 200 mm Si wafer with resistivity >1000 Ωcm is employed. A 5 μm thick SiO2 layer was deposited by PECVD method on the wafer. Both the high resistivity wafer and thick SiO2 layer were for the purpose of reducing substrate losses. On-chip inductors and the bottom plate of metal−insulator−metal (MIM) capacitors were first formed in the first metal layer (M1) using the etching process. The M1 was 500 nm thick Al. Another layer of SiO2 was deposited, followed by the second metal layer (M2) formed by damascene process. The M2 was 500 nm W and served as the top plate of MIM capacitors, the buried structure of the GFETs and necessary routings. B

DOI: 10.1021/acs.nanolett.5b02503 Nano Lett. XXXX, XXX, XXX−XXX

Letter

Nano Letters

Figure 2. Double-balanced mixer diagram and DC performance. (a) Schematic of the double-balanced mixer with external baluns. The IC is shown in the red frame. (b) Fabricated double-balanced mixer on PCB. (c) Optical image of the mixer. (d) SEM image of the mixer with the scale bar 200 μm. (e) The drain currents as a function of gate bias.

CMOS IC backbones, which is promising considering that graphene with its ultrahigh carrier mobility could replace traditional technologies in certain RF applications. Double-Balanced Mixer. The double-balanced mixer circuit is featured because of good suppression of the RF and LO feedthroughs and even-order intermodulation products.29 Theoretical analysis is given in Supporting Information. The schematic and photograph of the fabricated double-balanced mixer are shown in Figure 2a,b, respectively. The RF, LO, and IF signals are coupled with off-chip baluns, while the red frame in Figure 2a indicates the monolithic double-balanced mixer IC. The IC was bonded to the printed circuit board (PCB) connecting discrete baluns (see Supporting Information). The bonding wires were limited to about 2 mm, which introduced about 1 nH/mm parasitic effects. The RF/LO baluns externally made the RF and LO signal differential, converting a 50 Ω signal source into two symmetrical 100 Ω signal sources superimposed on the mixer IC. Microstrip lines with 50 Ω impedance were employed on the PCB. The IF output signals of the IC were combined by an off-chip IF balun. Figure 2c displays the optical image of the mixer IC that takes up 1.5 mm2 area. It consists of four GFETs, four on-chip spiral inductors and four on-chip MIM capacitors. Stand-alone inductors show inductance of 5 nH and Q-factor 4.2, which are consistent with simulations (see Supporting Information Figure S1). Stand-alone capacitors are 4 pF. Figure 2d shows the SEM image of the mixer IC with the inset displaying the close-up image of the adopted two-finger-structure GFET. These GFETs feature W/L = 8 μm/0.5 μm dimension for each finger.

Chemical mechanical planarization (CMP) process guarantees the flatness of the wafer surface, which is necessary for the successfulness of the later graphene transfer process. The buried gates eliminated the need of seed layers for nucleation of gate dielectrics on graphene. In this work, 7.6 nm HfO2 (EOT = 2 nm) was formed by atomic layer deposition (ALD) method as the gate dielectric with the potential for further scaling. These process steps were accomplished in a standard Si CMOS fab. A fabricated wafer is displayed in Figure 1e. Graphene in this work was formed by CVD method on Pt substrate as previously reported.23,24 “Bubbling” method was used to transfer graphene to the patterned wafer on a die-by-die basis, limiting by the maximum size of an individual piece of Pt foil (see Supporting Information).23,24 The graphene channel was defined by contact photolithography and oxygen plasma etching. Finally, 40 nm Pt was deposited by sputtering as source/drain contacts. The ICs have not gone through the last passivation step, which might cause hysteresis in particular.25 However, the mixers’ operation frequency was so fast limiting the time over which charge trapping can occur.26 Several reports have shown various dielectrics, such as Si3N4,27 BN,28 Al2O3,25 and so forth, could effectively protect graphene devices, which increase the stability and reliability of future graphene ICs. The inverted process avoids the possible deterioration of the GFET due to BEOL processes (i.e., contaminations and high temperatures). Also, by reversing the conventional IC fabrication flow, the inverted process fully utilizes existing Si fabs. The whole process flow is reviewed in Figure 1f. Potentially, it could realize graphene circuits on the top of Si C

DOI: 10.1021/acs.nanolett.5b02503 Nano Lett. XXXX, XXX, XXX−XXX

Letter

Nano Letters The GFETs’ functionality was first examined by DC transfer characteristics. Because of the cross-coupled circuit topology, the measurement of a certain GFET inevitably included another. The DC measurement results are demonstrated in Figure 2e. The gate leakage current is less than hundreds of fA, eliminating the shot noise and 1/f noise in the GFET resistive mixers.15 Even though ideal double-balanced mixers should have identical transistors, mismatch existed between the GFETs in this work. To further determine the cutoff frequency (f T) and maximum oscillation frequency ( f max) of the GFETs, we performed on-chip microwave measurement with identical stand-alone GFETs (we used Agilent N5230A network analyzer in the range of 100 MHz to 40 GHz). Careful de-embedding procedures were performed using the exact pad layout as “open”, “short”, and “through” structures.30 A typical 500 nm gate-length GFET achieved f T of 22 GHz and f max at a very close value of 20.7 GHz, as shown in Figure 3. The inset shows

the Raman spectrum of the transferred graphene, proving that it is monolayer and of high quality. The high f max is primarily attributed to the low resistance of the buried gates and welldesigned two-finger GFET layout. Figure 4a displays the output power spectrum of the doublebalanced mixer with input signals f LO = 3.5 GHz (8.9 dBm) and f RF = 3.6 GHz (−1.5 dBm). Despite the mismatch among the GFETs, the double-balanced mixer exhibits excellent output spectrum purity. The down-mixing signal f RF − f LO = 100 MHz is clearly shown, while higher orders of intermodulations are invisible. Also, the LO and RF feedthroughs were as low as −21 and −38 dBm, respectively. Suppression of these unwanted signals is attributed to the cross-coupled circuit topology. Simulation with GFET compact models also confirms the double-balanced mixer’s advantage in spectrum purity (see Supporting Information). It is worth noting that both the RF and LO signals were biased at zero voltage. Therefore, no power consumption was required. The CL was measured to be 33 dB. Modifications to improve CL should employ load-pull simulations with precise GFET large-signal models, as well as high-frequency PCB laminates (e.g., Rogers) and baluns with low insertion losses. The CL dependence on frequency is displayed in Figure 4b, which peaks at 3.5 GHz, determined by the performances of the circuit’s passive components. The linearity was first characterized by examining the output IF signal power dependence on RF signal input power. The power of IF signal is linearly proportional to that of the input RF signal in the test range (from −6.5 to 3.5 dBm), as shown in Figure 4c. Two-tone measurement was used for intermodulation measurement with f RF,1 = 3.59 GHz, f RF,2 = 3.61 GHz and f LO = 3.5 GHz (see Supporting Information Figure S3 and S4). The downconverted IF responses were at f IF,1 = 90 MHz and f IF,2 = 110 MHz, and third-order intermodulation responses at 2f IF,1 −

Figure 3. RF performance of a typical 500 nm gate-length GFET. The inset is the Raman spectrum of the graphene.

Figure 4. Performance of the double-balanced mixer. (a) The output spectrum of the double-balanced mixer. (b) The normalized CL as a function of frequency. (c) Measured IF power versus RF power at 3.5 GHz. (d) Measured two-tone spectrum of the mixer. (e) Linear and third-order responses versus RF power. D

DOI: 10.1021/acs.nanolett.5b02503 Nano Lett. XXXX, XXX, XXX−XXX

Letter

Nano Letters

Figure 5. Single-GFET mixer diagram and performance. (a) Optical microscope image of the single-GFET mixer. (b) Schematic of the mixer with one GFET, one inductor, and one capacitor. (c) Output spectrum of the mixer. (d) Normalized CL as a function of frequency. (e) Measured twotone spectrum of the mixer at 5 GHz. (f) The linear and third-order responses versus RF power.

f IF,2 = 70 MHz and 2f IF,2 − f IF,1 = 130 MHz, as shown in Figure 4d. The IIP3 is extrapolated to be 21 dBm, as demonstrated in Figure 4e. Single-GFET Mixer. To compare with the double-balanced mixer, ordinary single-GFET resistive mixers have been fabricated and tested. The passive components and GFET are exactly identical to those in the double-balanced mixer. The optical microscope image and schematic of the circuit are shown in Figure 5a,b, respectively. The DC characterization of the circuit is shown in Supporting Information Figure S2. Figure 5c shows the output power spectrum with input signals f RF = 5.1 GHz (−4.1 dBm) and f LO = 5.0 GHz (7.4 dBm). The purity of the output spectrum is inferior to that of the double-balanced counterpart. Despite the sum (10.1 GHz) and difference (100 MHz) signals, several unwanted signals are visible, including intermodulations at 200 MHz, 4.8 GHz, 4.9 GHz and a spurious signal at about 870 MHz, and the LO and RF feedthroughs were −22 and −12 dBm, respectively. The CL was 26 dB. Figure 5d shows the CL’s dependence on LO frequency, which peaks at frequency f LO = 5.0 GHz. Two-tone measurement was conducted with f RF,1 = 5.09 GHz, f RF,2 = 5.11 GHz, and f LO = 5.0 GHz. A measured two-tone spectrum is shown in Figure 5e, and the extracted IIP3 is 16.5 dBm as displayed in Figure 5f. Discussion. The double-balanced graphene resistive mixer, compared with the single-GFET counterpart, offers higher linearity and suppression of feedthroughs and unwanted signals in the output power spectrum. We show that even with transistors’ mismatch, the double-balanced resistive mixer can offer excellent linearity at low LO power. Considering graphene’s unique ultrahigh carrier mobility, the circuit is

promising to compete with compound semiconductor technologies in RF front-end applications. Stand-alone 500 nm gate-length GFETs in this work achieved f T/f max = 21/20.2 GHz with the potential for further scaling. The essence of the resistive mixer is to utilize the linear region of the output characteristics, which makes graphene stand out due to the absence of bandgap. The circuit’s passive nature makes it tolerant for GFETs’ process variations. We would list the limited conversion efficiency as a shortcoming for this kind of circuit. However, saved dc power by biasing at zero voltage can be used for adding a low-noise amplifier (LNA) stage in front of the mixer in real applications. The noise figure is limited by the mediocre conversion gain at the present stage.15 However, unlike active mixers, resistive mixers are only subjected to thermal noise.15 The IC fabrication scheme utilizes CMOS fabs to the maximum extend by reversing the BEOL and graphenecustomized FEOL processes, which reduces the cost for the potential graphene IC mass production. The demonstrated double-balanced mixer is listed as one of the most complex ICs in literature. It offers further potential to be integrated with CMOS circuit backbones. Also, this work for the first time demonstrates a graphene active IC coupled with off-chip passive components, realizing a PCB electronic system. It is a significant step forward for graphene electronics.

■

ASSOCIATED CONTENT

* Supporting Information S

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.5b02503. Additional information and figures. (PDF) E

DOI: 10.1021/acs.nanolett.5b02503 Nano Lett. XXXX, XXX, XXX−XXX

Letter

Nano Letters

■

(23) Xiao, K.; Wu, H.; Lv, H.; Wu, X.; Qian, H. Nanoscale 2013, 5, 5524. (24) Gao, L.; Ren, W.; Xu, H.; Jin, L.; Wang, Z.; Ma, T.; Ma, L. P.; Zhang, Z.; Fu, Q.; Peng, L. M.; Bao, X.; Cheng, H. M. Nat. Commun. 2012, 3, 699. (25) Sagade, A. A.; Neumaier, D.; Schall, D.; Otto, M.; Pesquera, A.; Centeno, A.; Elorza, A. Z.; Kurz, H. Nanoscale 2015, 7, 3558. (26) Carrion, E. A.; Serov, A. Y.; Islam, S.; Behnam, A.; Malik, A.; Xiong, F.; Bianchi, M.; Sordan, R.; Pop, E. IEEE Trans. Electron Devices 2014, 61, 1583. (27) Lee, J.; Tao, L.; Parrish, K. N.; Hao, Y.; Ruoff, R. S.; Akinwande, D. Appl. Phys. Lett. 2012, 101, 252109. (28) Wang, L.; Chen, Z.; Dean, C. R.; Taniguchi, T.; Watanabe, K.; Brus, L. E.; Hone, J. ACS Nano 2012, 6, 9314. (29) Kanazawa, K.; Kazumura, M.; Nambu, S.; Kano, G. O. T. A.; Teramoto, I. W. A. O. IEEE Trans. Electron Devices 1985, 32, 2717. (30) Vandamme, E. P.; Schreurs, D. M.; Van Dinther, C. IEEE Trans. Electron Devices 2001, 48, 737.

AUTHOR INFORMATION

Corresponding Authors

*(H.L.) E-mail: [email protected]. *(H.W.) E-mail: [email protected]. Author Contributions

H.M.L. conceived and designed the experiment. H.M.L., J.Y.Z., and Z.P.Y. conceived and designed the circuit. H.M.L., H.Q., X.M.W., and H.Q.W. developed the integration process. H.M.L., J.B.L., J.B.N., and J.F.L. fabricated the circuits. T.M., W.C.R., and H.M.C. synthesized the CVD graphene. H.M.L. wroted the paper. All authors discussed the results and comments on the manuscripts. Notes

The authors declare no competing financial interest.

■

ACKNOWLEDGMENTS This research was supported by the National Basic Research Program (2013CBA01604), the National Natural Science Foundation (61474072), and the National Science and Technology Major Project (2011ZX02707).

■

REFERENCES

(1) Novoselov, K. S.; Geim, A. K.; Morozov, S. V.; Jiang, D.; Zhang, Y.; Dubonos, S. A.; Grigorieva, I. V.; Firsov, A. A. Science 2004, 306, 666. (2) Cheng, R.; Bai, J.; Liao, L.; Zhou, H.; Chen, Y.; Liu, L.; Lin, Y. C.; Jiang, S.; Huang, Y.; Duan, X. Proc. Natl. Acad. Sci. U. S. A. 2012, 109, 11588. (3) Han, S. J.; Garcia, A. V.; Oida, S.; Jenkins, K. A.; Haensch, W. Nat. Commun. 2014, 5, 3086. (4) Lv, H.; Wu, H.; Liu, J.; Huang, C.; Li, J.; Yu, J.; Niu, J.; Xu, Q.; Yu, Z.; Qian, H. Nanoscale 2014, 6, 5826. (5) Habibpour, O.; Vukusic, J.; Stake, J. IEEE Trans. Microwave Theory Tech. 2013, 61, 841. (6) Andersson, M. A.; Habibpour, O.; Vukusic, J.; Stake, J. Electron. Lett. 2012, 48, 861. (7) Han, S. J.; Jenkins, K. A.; Valdes-Garcia, A.; Franklin, A. D.; Bol, A. A.; Haensch, W. Nano Lett. 2011, 11, 3690. (8) Guerriero, E.; Polloni, L.; Rizzi, L. G.; Bianchi, M.; Mondello, G.; Sordan, R. Small 2012, 8, 357. (9) Wang, H.; Nezich, D.; Kong, J.; Palacios, T. IEEE Electron Device Lett. 2009, 30, 547. (10) Parrish, K. N.; Akinwande, D. Appl. Phys. Lett. 2011, 99, 223512. (11) Yang, X.; Liu, G.; Balandin, A. A.; Mohanram, K. ACS Nano 2010, 4, 5532. (12) Lee, S.; Lee, K.; Liu, C. H.; Kulkarni, G. S.; Zhong, Z. Nat. Commun. 2012, 3, 1018. (13) Wang, H.; Hsu, A.; Wu, J.; Kong, J.; Palacios, T. IEEE Electron Device Lett. 2010, 31, 906. (14) Liao, L.; Bai, J.; Cheng, R.; Zhou, H.; Liu, L.; Liu, Y.; Huang, Y.; Duan, X. Nano Lett. 2012, 12, 2653. (15) Andersson, M. A.; Habibpour, O.; Vukusic, J.; Stake, J. IEEE Trans. Microwave Theory Tech. 2012, 60, 4035. (16) Lin, Y. M.; Valdes-Garcia, A.; Han, S. J.; Farmer, D. B.; Meric, I.; Sun, Y.; Wu, Y.; Dimitrakopoulos, C.; Grill, A.; Avouris, P.; Jenkins, K. Science 2011, 332, 1294. (17) Moon, J. S.; Seo, H. C.; Antcliffe, M.; Le, D.; McGuire, C.; Schmitz, A.; Nyakiti, L. O.; Gaskill, D. K.; Campbell, P. M.; Lee, K. M.; Asbeck, P. IEEE Electron Device Lett. 2013, 34, 465. (18) Microwave Mixers; Artech House, Inc.: Norwood, MA, 1986. (19) Maas, S. A. IEEE Trans. Microwave Theory Tech. 1987, 35, 425. (20) Andersson, K.; Desmaris, V.; Eriksson, J.; Rorsman, N.; Zirath, H. IEEE Int. MTT-S. 2003, 2, 1303. (21) Motlagh, B. M.; Gunnarsson, S. E.; Ferndahl, M.; Zirath, H. IEEE Microw. Wirel. Co. Lett. 2006, 16, 25. (22) Ellinger, F. IEEE Trans. Microwave Theory Tech. 2005, 53, 2559. F

DOI: 10.1021/acs.nanolett.5b02503 Nano Lett. XXXX, XXX, XXX−XXX