200 GHz Maximum Oscillation Frequency in CVD Graphene Radio

Sep 19, 2016 - The quality of the CVD graphene on SiO2/Si transferred by Au film is evaluated using Raman spectroscopy, (Shown in Figure S2), the grap...
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200 GHz Maximum Oscillation Frequency in CVD Graphene Radio Frequency Transistors Yun Wu,† Xuming Zou,‡ Menglong Sun,† Zhengyi Cao,† Xinran Wang,§ Shuai Huo,† Jianjun Zhou,† Yang Yang,† Xinxin Yu,† Yuechan Kong,† Guanghui Yu,# Lei Liao,*,‡ and Tangsheng Chen*,† †

Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Device Institute, Nanjing 210016, China ‡ Department of Physics and Key Laboratory of Artificial Micro- and Nano-structures of Ministry of Education, Wuhan University, Wuhan 430072, China § National Laboratory of Solid State Microstructures, School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093, P. R. China # Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai 200050, P. R. China S Supporting Information *

ABSTRACT: Graphene is a promising candidate in analog electronics with projected operation frequency well into the terahertz range. In contrast to the intrinsic cutoff frequency ( f T) of 427 GHz, the maximum oscillation frequency (f max) of graphene device still remains at low level, which severely limits its application in radio frequency amplifiers. Here, we develop a novel transfer method for chemical vapor deposition graphene, which can prevent graphene from organic contamination during the fabrication process of the devices. Using a self-aligned gate deposition process, the graphene transistor with 60 nm gate length exhibits a record high f max of 106 and 200 GHz before and after de-embedding, respectively. This work defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra high frequency circuits. KEYWORDS: field-effect transistors, radio frequency, self-aligned, maximum oscillation frequency, parasitical resistance

G

the drain to source resistance, Rl is access resistance, Rs is source resistance, Ri is input resistance, and Rg is gate resistance. Because of the different emphasis in eqs 1 and 2, the main reason for the discrepancy is due to high contact resistance and gate resistance, as well as large gds leading to hardly any channel saturation. Another key challenge to device applications is wafer-scale precise manufacturing. With recent advances, chemical vapor deposition (CVD) techniques yield the repeatable and reliable production of large-area, high-quality graphene films,7 which could meet the engineering requirement in RF device. Unlike thermal decomposition methods, which use high-cost SiC substrates, CVD utilizes inexpensive and readily accessible Ni or Cu substrate8,9 and is suitable for large scale production. Although smart transfer method can be convenient to transfer CVD graphene to any substrate, a current generally accepted transfer method uses poly(methyl methacrylate) (PMMA) or other organic compound as a supporting layer. However, the organic residue from this transfer process and the

raphene is recognized as a promising candidate material for high-speed field-effect transistors operating well into the terahertz range, profiting from its intrinsic low dimensionality, high carrier mobility, and large saturated carrier velocity.1 Since the first large-scale patterning of graphene field-effect transistors (GFETs),2 the device performance has been improved at a rapid pace. For radio frequency (RF) transistors, a 67 nm channel-length GFET with an intrinsic cutoff frequency (f T) of 427 GHz has been reported,3 which is comparable to the same scaled state-of-the-art Si MOSFETs.4 Despite the high f T of GFETs, the maximum oscillation frequency ( f max), which represents the spped of power transmission, remains at a low level, directly limiting its practical application in RF devices.5,6 Usually, analytical expressions of f T and f max can be derived as fT = gm /2πCg

(1)

fmax = fT /2[gds(R l + R ds + R i) + 2πCgR gfT ]1/2

(2) Received: May 15, 2016 Accepted: September 19, 2016

Where gm is transconductance, Cg is the total top-gated capacitance, gds = 1/Rds is the output conductance with Rds is © XXXX American Chemical Society

A

DOI: 10.1021/acsami.6b05791 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ACS Applied Materials & Interfaces

Figure 1. Schematic illustration of transfer process: CVD graphene is transferred with (a) PMMA, (b) Au film.

residue, but these especial methods are not suitable for fabrication of GFET process which requires lithography time after time. To overcome this issue, we first deposited 30 nm Au film on the surface of as-grown CVD graphene on Cu substrates as the supporting layer, so as to form pristine Au/ graphene contact after the transfer process. Importantly, the cleanup of supporting layer is omissible as Au and graphene can form good Ohmic contact as the source (and drain) of the GFET in latter self-aligned process (as shown in Figure 1b), and the covered Au film can prevent graphene from photoresist and other organic contamination during the whole fabrication process of the devices. Schematic illustrating of self-aligned method is shown in Figure 2. After the transfer process, standard lithographical method is used to define the regions of the GFET. Gold film outside the channel is wet etched away by aqueous KI:I2 solution and the graphene film outside the channel is removed by oxygen plasma etching. In order to reduce the gate resistance, trilayer photoresist for T-gates is patterned on the gold film in the channel regions using e-beam lithography (Figure 2b).17 The gold film under the T-gates is wet etched away by aqueous KI: I2 solution (Figure 2c). The unetched gold film outside the T-gates form self-aligned source and drain Ohmic contacts automatically. In particular, the proper etching time depended on the thickness of Au film can be designed to control the lateral-etching in the solution-etching process, which can ensure the insulated isolation between the source (drain) and the gate electrode with a tiny space. And then, the sample is deposited 1 nm Al and exposed in air for 10 h to form self-oxidized Al2O3 buffer layer. After that 8 nm thick Al2O3 film is deposited by ALD as gate dielectric and 50 nm Ti/450 nm Au is deposited by e-beam evaporation as the top-gated electrodes (Figure 2d).The device fabrication is accomplished following lift-off (Figure 2e). With this method, the graphene in the channel could keep away from the organic solution directly

following lithography process is hard to clean out and could be a limiting factor for the frequency performance of the GFET: bad metal/graphene contact and bad gate dielectrics growth.10,11 It is for these reasons that the f max of CVD graphene device has thus far shown inferior performance compare to thermal decomposition graphene based on SiC. Recently, using metal as the sacrificial transfer layer for CVD graphene and protecting layer of thermal decomposition graphene have been reported,6,12 but excellent f max performance for CVD graphene FET has not been demonstrated. In this work, we present a novel method for fabricating high performance top-gated FET arrays with CVD graphene, using Au film as the sacrificial transfer layer instead of polymers. The Au film forms Ohmic contact with graphene transistors, which also enables a self-aligned gate process that minimizes the ungated graphene region. These novel processes keep CVD graphene free from organic contaminations not only in the transfer but also in the later lithography process. Together with improved transfer method, self-aligned technique and T-gate structure, the parasitical resistance and gate resistance of GFET are minished. As a result, f T of 255 GHz and f max of 200 GHz are achieved in our devices with a gate length of 60 nm after deembedding process. The current generally accepted transfer method using PMMA as a supporting layer: graphene surface is coated with PMMA, and the metal catalyst is then etched using an etchant. Subsequently, the polymer-supported graphene is readily transferred onto a desired substrate, and then the cleaning of supporting layer is done in organic solvent such as acetone.13 But unfortunately, cleaning process is inadequate for completely removing the organic residue as strong chemical adsorption between graphene and organic compound, exposing the graphene to organic compound in this transfer and the followed lithography process that can leave behind contaminants on graphene surface (shown in Figure 1a). Several efforts, such as searching substitution in transfer process or annealing in especial ambience,14−16 have been done to removed the B

DOI: 10.1021/acsami.6b05791 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ACS Applied Materials & Interfaces

access resistance induced by source-gate spacing results in a main contribution to the f T and f max, and the source-gate spacing of GFET is a key factor for the design of the device performances.19 Though shorter ungated channel could be achieved by especial self-aligned technology in which the source and drain are separated by gate electrode,3 it cannot be compatible with T-gate. In this work, T-gate is formed with 60 nm gate length combining 350 nm cap, and the extend-cap could restrain the gate resistance. The optimized parasitical contact resistance and gate resistance are designed for high-frequency performance. The DC performance of the GFET devices with 60 nm gate length (two-finger design, with channel width 10 μm) is shown in Figure 4. The device showed that a clear increase in conductance is induced by the gate voltage, and completely linear behavior at low drain-source bias suggests typical metal/ zero band gap semiconductor junctions. From the output characteristics at low drain-source bias in Figure 4a, the total on resistance (Rtotal) is 220 Ω μm.20 To determine the mobility and the parasitic resistances of the device, a GFET with 1 μm gate length has been prepared with same preparation process. Rtotal is modeled as the sum of an ideal graphene channel resistance modulated by the top gate and a parasitic resistance Rc (sum of contact resistance and ungated graphene resistance)20,21 and Rtotal is given by

Figure 2. Schematic illustration of the fabrication of self-aligned GFETs by solution-etching. (a) 30 nm Au/graphene on Si substrate with 300 nm SiO2; (b) trilayer photo resist for T-gates are patterned by EBL; (c) gold film under the T-gates is wet etched away concomitant transverse etched space; (d) Ti/Au is deposited on top as the gate metal after 8 nm Al2O3 is deposited by ALD as dielectric with 1 nm Al self-oxidized seed layer; (e) after lift-off, GFETs are formed; (f) photo image of transferred graphene with Au film on 3 in. Si substrate; (g) photo image of GFETs on 3 in. Si substrate.

R total = R c + Lg /eμW [n0 2 + Cg 2(Vg − Vdir)2 /e 2]1/2

(3)

Where Lg is the access region length, W is the device width, μ is the carrier mobility, q is electron charge, n0 is the minimum sheet carrier density determined by disorder and thermal excitation. Cg, which is the total top-gate capacitance, are determined by C−V measurement and found to be 5 × 10−7 F/ cm2. Using the extraction method described in refs 28 and29, the measured data and the fitting results is shown in Figure S3 and the hole mobility of 3560 cm2/(V s) are obtained for graphene channel. It is meaningful that the fitted parasitic resistance of 6.5 Ω (105 Ωμm) is smaller than other GFETs from the CVD graphene,22,23 as the contact resistance is minimized by forming clean graphene/Au contact and the ungated graphene resistance is minimized by self-aligned technique. Because of this small contact resistance, a current density as large as 2.32 mA/μm is observed at Vds = 0.8 V and Vgs = −1 V, and I−V characteristics of the devices show a clear saturation, rather an inflection point at relatively small Vds, which must be owned to high-quality dielectric layer and low parasitic resistance. The similar current saturation are previously only reported in GFETs made by high-quality exfoliated graphene,24and long channel device made by CVD graphene.25 As shown in Figure S4, the saturation current suggests smaller gds, which is conducive to optimize f max.25 Figure 4b shows the transfer characteristics of the top-gated GFET. Characteristic V-shaped ambipolar behavior is not appeared in the range of −1 V to 1 V, which could be attributed to p-doped by self-oxidized Al seed layer. The corresponding gm is raised with Vds and approached saturation, a maximal gm of 11.8 mS is measured at Vgs = −1 V and Vds = 0.3 V. The good gm performance also indicates that there is a good quality dielectric layer, owed to clean graphene surface and selfoxidized Al2O3 buffer layer. The gate leakage current is less than 3 nA with 8 nm Al2O3 dielectric layer by ALD (Figure S5), indicating the gate leakage current is negligible.

during the device fabrication, which is verified as being beneficial for the performance improvement of our GFETs. Atomic force microscope (AFM) is employed to check out the surface of sample from PMMA transferred. The sample has been dipped in acetone for 16 h to dissolve PMMA; however, the contamination is still observed in the surface of graphene, compared to clean surface of Si/SiO2 substrate, as shown in Figure S1. The similar problem will appeared in lithography process, and the Ohmic contact and the growth of gate dielectrics will be seriously affected by these organic residue. It is obvious that the graphene from Au transferred will not be troubled with these. The quality of the CVD graphene on SiO2/Si transferred by Au film is evaluated using Raman spectroscopy, (Shown in Figure S2), the graphene is monolayer domains for narrow fwhm and I2D:IG > 1, and the weak D peak suggests weak damage from the transfer process.18 Figure 3 shows scanning electron microscope (SEM) image of GFET and the section of the gate by focused ion beam. With the help of self-aligned technology, a tiny space with only 30 nm between gate and source (drain) is achieved, and this level could exceed alignment accuracy by generic lithography tool and even e-beam lithography. Current investigation reveals that

Figure 3. Images of GFET: (a) SEM image of a typical dual-gate GFET; (b) cross-section FIB image of a GFET overall device layout. C

DOI: 10.1021/acsami.6b05791 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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Figure 4. Typical room-temperature DC and RF electrical characteristics of a GFET with a device channel width of 20 μm. (a) Ids−Vds output characteristics at various gate voltages (Vgs= −1, −0.5, 0, 0.5, and 1 V; (b) transfer characteristics at different bias voltage for GFET (Vds = 0.1, 0.15, 0.2, 0.25, and 0.3 V); (c) H21 versus frequency of GFET before de-embedding (black dot) and after de-embedding (red dot); (d) U1/2 of GFET before de-embedding (black dot) and after de-embedding (red dot).

reported values for any GFETs. As shown in experiential eq 2, minishing the Rg, Rs, and channel conductance (gds) could be key factor for higher f max. In our work, T type gate have been design to minish Rg, optimize transfer method carries out small contact resistance, and self-alignment helps to restrain tandem resistance between gate and source (drain). Noteworthy, the carrier in channel could be accelerated to soft saturation more easily at smaller parasitical resistance. As showed in Figure S4, this nonlinear variety in current means minished gds, which is profitable for improved f max. Figure S8 shows the f T and f max comparisons of our GFETs with the other reports.4,6,7 As shown in Figure S8, for the same gate-length, our device shows the outstanding RF performance in CVD GFETs, and the f max value of 200 GHz is much higher than the reference data. It is no doubt that the extrinsic f max, higher than 100 GHz in our work, indicates preponderant design for restraining parasitical resistance, and it takes an important step for future applications of graphene based devices in RF circuits. We believe the frequency performance of the device can be further improved by improving graphene quality and restraining scatting of the interface in future. In summary, this work provides the experimental evidence of controlling parasitic effect for GFET. Using Au film as the supporting layer, the graphene is kept away from organic contamination in the whole techniques process, which is important to form good Ohmic contact and high-quality gate dielectrics. With the optimized transfer method, self-alignment and T-gate technique, the excellent DC performance with a small parasitic resistance of 105 Ωμm and RF performance with a record f max of 200 GHz are achieved. Our studies open a pathway to high frequency performance in GFETs, and show a great engineering potential for CVD graphene in RF power device applications.

The hysteresis characteristic of the GFETs are measured by double scanning mode, as shown in Figure S6, the Autransferred GFET shows obvious optimized performance contrasted with PMMA-transferred sample, this result is consistent with previously reported.12 Generally, hysteresis is related to the interface trap density from the interface,26 these results imply that clean surface of graphene without organic residue could enhance performance of GFETs, which could provide suitable carrier concentration and decrease the interface trap density. For RF transistors, the two most important small-signal figures of merit are f T, and f max. In this work, high-frequency scattering parameters (S-parameters) of the GFETs have been measured up to 66 GHz under ambient conditions using standard ground-signal-ground (GSG) microwave probes. The system was calibrated with the short-open-load-through (SOLT) process to eliminate the parasitic effects of the wiring and the probes,27 relevant de-embedding process and deembedding structures are provided in Figure S7. Before de-embedding, a maximum f T of 70 GHz is measured for a device with 60 nm gate length at Vgs = 0.6 V and Vds = 0.35 V (Shown in Figure 4c). This f T value is the highest cutoff frequency reported to date for GFETs on any substrates without de-embedded.7,28 To remove the effects of probing pads, we use a de-embedding procedure similar to that described in previous report.29 After the de-embedding process, f T values of 255 GHz were measured on 60 nm gate length devices. Two higher reported values are reported by IBM and UCLA, but costly diamond-like carbon is employed as substrate to restrain scatter and high-quality graphene is exfoliated from bulk natural graphite crystals by micromechanical cleavage, respectively. f max is the highest possible operating frequency before a transistor loses its ability to amplify power. As shown in Figure 4d, our transistors exhibit excellent microwave power gain with f max up to 106 and 200 GHz before and after de-embedding process at Vgs = 0.6 V and Vds = 0.35 V, both are the highest D

DOI: 10.1021/acsami.6b05791 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.6b05791. AFM images of the samples, Raman spectroscopy of our graphene from Au transferred, measured and the fitted resistance of the GFET with 1 μm gate length, conductance between source and drain (gds) of GFET, gate leakage current for GFETs, hysteresis characteristic for the GFETs, graphene FET de-embedding structures and the de-embedding process, f T and f max comparisons with data in refs 4, 6, and7, device fabrication and measurements (PDF)

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AUTHOR INFORMATION

Corresponding Authors

*E-mail: [email protected]. *E-mail: [email protected]. Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS This work was supported by 973 grants of MOST (2013CBA01604 and 2011CB932704), NSFC grants (61222402 and 61574101), as well as Ten Thousand Talents Program for Young Talents.

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REFERENCES

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DOI: 10.1021/acsami.6b05791 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX