A New Approach for Micro-fabrication of Printed Circuit Boards

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Surfaces, Interfaces, and Applications

A New Approach for Micro-fabrication of Printed Circuit Boards with Ultra-fine Traces Seyed M Mirvakili, Kurt Broderick, and Robert S. Langer ACS Appl. Mater. Interfaces, Just Accepted Manuscript • Publication Date (Web): 04 Sep 2019 Downloaded from pubs.acs.org on September 4, 2019

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ACS Applied Materials & Interfaces

A New Approach for Micro-fabrication of Printed Circuit Boards with Ultra-fine Traces Seyed M Mirvakili1,*, Kurt Broderick2, and Robert S Langer1,* 1Mechanical

Engineering Department, Massachusetts Institute of Technology, Cambridge, MA 02139, USA.

2Microsystems

Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA 02139, USA.

Corresponding to [email protected], [email protected], and [email protected]. Keywords: printed circuit boards, microfabrication, additive manufacturing, micro-coils, microelectronics

Abstract The advances in micro/nanofabrication techniques have enabled miniaturization of printed circuit boards for various applications including portable devices, smart sensors, and IoTs, to name a few. Printed circuit boards provide electrical connectivity between the components as well as mechanically support. Down-scaling of printed circuit boards is crucial for miniaturization of large systems and devices. Currently, micro-traces down to 25 µm can be microfabricated with the current microfabrication processes at an industrial scale. In the present work, we report a new approach for micro-fabrication of printed circuit boards with trace widths down to 3 microns on commercially available PCB substrates. We used electroplating/electroetching, sputtering, and photolithography to achieve these fine trace sizes. The proposed fabrication technique can be used in microelectronics, system on chip (SoC), MEMS, and miniaturized circuits and systems in general. Introduction The number of transistors in a dense integrated circuit (IC) doubles almost every two years, according to Moore’s law.1 Increasing the population density of transistors enables smaller ICs with the same or even higher computing power. In parallel with the enhancements in the fabrication

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of ICs, size and performance of other surface mount devices (SMDs) such as resistors, capacitors, and inductors have improved as well. Due to these improvements, miniaturization of circuit boards is now possible, which enables down-scaling of the printed circuit board (PCB) real estate to reduce the space, weight, and manufacturing cost and time. Since the invention of the first generation of PCBs in 1955, the trace size has been reduced from 250 µm to 10 µm which has enabled fabrication of smaller portable electronics such as smartphones, smartwatches, sensors, and even miniature device such as micro/nanosatellites,2,3 micro-actuators,4 micro-gas chromatograph,5 MEMS,6 and micro-fluidics/lab-on-chip.7,8 PCBs are often made of one or more films of copper laminated/cladded onto and/or between layers of a dielectric material such as FR1−6, Teflon, and CEM1−5. Conversely, for flexible electronics and stretchable electronics different platforms are used which do not utilize most of the fabrication techniques commonly used for rigid PCBs.9–11 Currently, the typical feature size that can be fabricated with PCB manufacturing technology is 50 – 250 μm.12 Using additive manufacturing techniques, fabrication of traces down to 25 μm is now possible but with a manufacturing cost of 7 – 10 k$.13 One of the limitations imposed by the traditional wet-etching processes is the isotropic etching rate of etchant solutions for copper which limits the controllability of the aspect ratio (i.e., width/height) of the traces.14,15 For example, traces with an aspect ratio of 1 cannot be easily fabricated with the traditional PCB fabrication. Ion-mill or focused ion beam can be used to etch copper atoms with an excellent spatial resolution, but they are time-consuming, require long exposure of the substrate to a high vacuum environment (leading to degassing of the substrate and increasing the surface roughness), and are not economically viable.16 In the present work, we report a relatively low cost and easy microfabrication technique that can be used to fabricate copper traces down to 3 µm in width. This technique involves 2 ACS Paragon Plus Environment

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electrochemical etching, photolithography, and a semi-additive metallization process (sputtering and electroplating) on almost any commercially available PCB. Results and Discussion In this work, we are presenting a relatively easy and fast approach for micro-fabricating micronsize copper traces on a PCB substrate. The novelty of our approach comes from the fact that we can apply it to almost any commercially available PCB (with minimum cost) which makes it adoptable wide variety of application from micro-circuits for space applications to high frequency RF circuits and power electronics. By using this fabrication process, we could demonstrate 3 μm wide copper traces with a spacing of 15 μm on an off-the-shelf PCB substrate (methods). Our proposed approach is a combination of electrochemical etching and semi-additive manufacturing processes (Fig. 1A). It consists of electrochemical etching of a copper cladded PCB substrate (methods) (Fig. 1B) followed by sputtering of a thin layer (< 300 nm) of copper. The electrochemical etching process (a.k.a., electroetching) is similar to the electroplating process except for the sample of interest is now used as a counter electrode (anode). At the anode, the solid copper etches away from the electrode forming Cu2+ and releases 2e− to the anode. The electroetching process can be optimized to etch the entire copper film or leave some copper traces as an adhesion layer for the sputtering step (Fig. 1B). SEM image analysis shows 43.2% (±1.9%) of the copper can be etched with the electroetching process at an equilibrium current density of 23.9 – 27.9 A/m2 with a 10 mm spacing between the working and counter electrode. Photolithography is then employed to create the desired trace patterns on the substrate. Copper is then electroplated to increase the trace height. The thickness of the photoresist sets the upper limit for the trace height. After the electroplating and photoresist stripping, the undesired copper layer under the just removed photoresist is etched away with a dilute nitric acid solution. In a traditional 3 ACS Paragon Plus Environment


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micro-fabrication technique, a thin layer of titanium/chromium (~ 20 nm) is sputtered directly on a substrate as a binding layer followed by deposition of a thin layer of copper (~ 200 nm) as the seed layer (methods - fabrication procedure 2). The photolithography and electroplating steps are similar to our proposed approach. This process enables micro-fabrication of fine features; however, the mechanical stability of the traces is weak and does not the pass tape-test (methods, supporting information). In contrast, all the traces that we micro-fabricated with our technique successfully passed the tape test with almost zero layer detached from the surface in the tape-test (methods, supporting information). A

B

C

D

Fig. 1. (A) Fabrication process: 1) The substrate is prepared and cleaned with ethanol and DI water. 2) Using a process (depicted in B) the copper is etched until small islands of copper are left as an adhesion layer. 3) A thin layer of copper is sputter-coated on the substrate as an electrically conductive seed layer. 4) Photo-lithography is performed, and the photo-resist is developed. 5) Copper is electroplated to increase the height of the traces. 6) The photo-resist is washed away with acetone, and excess seed layer copper is etched. (B) Illustration of fabrication process step 2. Electroplating with reverse polarity is used to etch away copper from the substrate. The copper islands act as an adhesion layer for the copper-electroplating process. Top-right corner: a zoomed-in version of the circle in figure 1B. The circle illustrates the copper islands after electrochemical etching. (C) and (D) Zoomed-in SEM image of the box in figure B


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top-right showing the copper islands after electrochemical etching. Scale bars: 0.1 mm for B and 12 μm for D.

In RF electronics, the surface roughness of conductive traces can affect the insertion loss due to the skin effect.17 Therefore, achieving a smooth surface finish is very desirable for such applications. We achieved surface roughness of 501.8 nm (± 97.2 nm) for micro-fabricated traces on a Rogers 3210 substrate (methods) with a surface roughness of 864.5 nm (± 19.82 nm). This sub-micron surface roughness of electroplated copper is close to that of a rolled-annealed copper sheet which has a relatively small amount of insertion loss for high frequency (> 1 GHz) RF circuits. Aside from the mentioned attributes (e.g., surface roughness, trace size, and mechanical stability), we found the electrical conductivity and thermal stability of the traces as well (Table 1). The measured electrical conductivity (methods) is very close to that of a pure copper sheet (i.e., 59.6 MS·m−1 at 20 °C). The micro-fabricated samples were heated up to 235 °C to test their thermal stability. Even after exposure to high temperatures, the traces maintained their mechanical stability and passed the tape test. Table 1 Characteristics of micro-fabricated traces Feature

Results

Trace Size (µm)

>3

Surface Roughness (nm)

501.8 ± 97.2

Tape Test (at 25°C)

Passes

Electrical Conductivity (MS·m−1)

60.6 ± 6.3

Thermal Stability (°C)

235

To evaluate performance of our micro-fabrication process, we fabricated two types of planar micro-coils on commercially available PCB substrates (methods). One is with a constant trace width for all the loops (Fig. 2A) and the other one is with a larger trace width for larger loops (Fig. 5 ACS Paragon Plus Environment


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2B) to compensate for their increase in resistance. The profiles of the traces for these two designs (Fig. 2C, D) show that for the constant width loops the height of each trace is almost constant; however, for the resistance-compensated traces, the height increases for the outer loops. This increase in height can be explained by the fact that smaller features exhibit less mass, therefore, under equal etching conditions (e.g., isotropic etching rate, temperature, etchant concentration), they are etched away faster. A

C

E

B

D

F

Fig. 2. (A) and (B) the resulting fabricated micro-coils. (C) and (D) traces profiles along the dashed-lines in figure A and B. (E) and (F) Zoomed-in SEM images of the boxes in figure A. Scale bars: 0.4 mm for (A) and (B), 30 μm for (E), and 50 μm for (F).

These micro-coils can be in for RF applications. As a demonstration, we excited the coils with a RF power amplifier and measured the spectral power as a function of distance from the center of the coil (Fig. 3A). In order to prevent any damages to the coils and the power amplifier, we first matched impedance of the coil to the output impedance of an RF power amplifier (50 Ω) using a matching network. A voltage standing wave ratio (VSWR) of 1.023 was achieved after matching the impedance at 777.42 MHz. The coil was excited at 777.42 MHz at an input power of 35 dBm, 6 ACS Paragon Plus Environment

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and the radiated power was measured using a calibrated probe connected to a spectrum analyzer (Fig. 3B). The probe output power and the magnetic flux density are related by the following equation: (1) where X is a calibration factor, F is the frequency (in MHz), and B is the magnetic flux density (in Tesla). The magnetic flux density is related to the distance, coil, and excitation parameters according to the following equation: (2) where V is the applied voltage to the coil, µo is the magnetic permeability, ρ is the electrical resistivity, ri is the radius of the loop number i, Ai is the cross-sectional area of the trace for loop number i, and Z is the vertical distance from the center of the loop. Combining the monotonically increasing function in equation 1 with equation 2, we can speculate that the output power decays with the inverse of the distance, which is what our measurements show (Fig. 3A). A

B

Fig. 3. (A) Power decay of the micro-coil (with six loops), excited at 777.416 MHz with RF input power of 35 dBm, as a function of distance. (B) Return loss of the micro-fabricated coil from 600 MHz to 1 GHz after impedance matching. Inset: Zoomed-in version of S11 curve (750 MHz – 800 MHz).



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Optical images of the micro-coils show optical reflectivity or surface finish of the traces (Fig. 4A, B). To illustrate solderability of the microfabricated circuits, an SMT capacitor and two pieces of a solid-core wire were soldered on a micro-fabricated coil without any issues (Fig. 4C). A

C

B

Fig. 4. (A) and (B) Optical Images of the micro-coils with 10-loops. The dimension of the traces is the same as the loops in Fig. 2. (C) Optical image of the micro-fabricated circuit with a surface mount capacitor soldered on the traces. Inset: the zoomed-in image of the micro-coil with 4-loops. Scale bars: 0.4 mm for (A) and (B), 2 mm for (C).

We fabricated other geometries to investigate other capabilities of our fabrication technique. In microfabrication of metals, preserving the sharpness of shapes with sharp corners is typically challenging due to the isotropic etching behavior of the etchants. Here, we designed some geometries with sharp corners, such as interdigitated electrodes and curved structures to examine the effect of isotropic etching rate. As shown in figure 5 B-F, the sharp corners are etched, but the overall shape at those edges are preserved.


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B

C

D

60 μm

40 μm

15 μm

E

F

20 μm

20 μm

90 μm

Fig. 5. (A) A 3 μm wide trace on PCB substrate. (B) Curved traces with a width of 25 μm. (C) Interdigitated traces. The red dashed-lines shows how the sharp corners etch away during the final etching process. (D) The inner loop is 6 μm wide. (E) Negative of the structure in (B). The spacing between the traces is 15 μm. Scale bar is 60 μm. (F) Optical zoomed-out image of the structure in (B).

The time and cost-efficient aspect of our proposed microfabrication technique come from the fact that we are using electroetching, which enables us to recover the copper that is chemically etched in the traditional processes and reuse it during the fabrication process. Additionally, the electroetching and electroplating processes are low-cost in terms of electrolyte and equipment and can be adopted into a time-efficient batch process, electro-etching/electroplating multiple substrates in parallel. Large scale copper electroplating is used during the minting of pennies in the US. Each penny contains about 20 microns of copper on a zinc core. The cost of electroplating of 20 microns of copper can be estimated to be between 1.1 $/m2 – 2 $/m2 in mass production. Aside from the electrochemical etching/plating step, the photolithography and sputtering steps are relatively lowcost in industrial mass-production scale. For example, sputtering of WO3 can be as low as 12 $/m2 to 34 $/m2 for in-line sputter deposition.18 Conclusion 9 ACS Paragon Plus Environment


In conclusion, we demonstrated that fine traces (down to 3 microns) could be microfabricated on almost any commercially available PCB substrates by employing a combination of etching, photolithography, and a semi-additive metallization process (sputtering and electroplating). These fine copper traces exhibit excellent mechanical stability even at high soldering temperatures and more importantly have a very smooth texture, which is essential for high-frequency applications. Reducing the trace width, increasing trace heights, and decreasing the spacing between the traces are three remaining challenges that will remain for future studies. The proposed approach, at its current state, can be used to micro-fabricate coils, solenoids for miniature NMR,19 micro-relays 20 and micro-electro-mechanical systems (MEMS), digital microfluidics,21 onboard strain gauge, biosensors,22 radio frequency identification tags, and microelectronic circuits in general. Methods A. Characterization Techniques and Equipment Adhesion strength/stability test: Tape test is commonly used technique to assess the adhesion of bound layers on a substrate. It involves using a piece of tape to peel-off an adhered layer to test its adhesion strength. In this work, we followed the ASTM D3359 protocol to evaluate the adhesion. Elcometer 99 Cross Hatch Adhesion Test Tape was used to carry out the text. The ranking of the tape test samples was found out by comparing the obtained results with the ASTM D3359 ranking table (supporting information). Electrical Conductivity Measurement: Four-terminal sensing technique (a.k.a., Kelvin sensing) gives an accurate measurement of electrical conductivity of materials. The technique consists of having four probes, equally spaced. The outer two probes apply a small current (Isource) and the inner two measures the drop voltage (Vsense). From the Isource and Vsense the resistivity can be


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calculated. A Keysight B2962A Low Noise Power Source was used in a Kelvin sensing configuration to measure the resistivity of the traces. Surface Characterization: Scanning electron microscopy was performed with a tabletop SEM (Hitachi TM3000) to investigate the morphology of the substrate during the fabrication process. Due to degassing of the substrate, it is very important to not perform SEM in high vacuum pressures. High energy electron radiation can damage the substrate as well. For surface roughness measurements, a Dektak 150 Surface Profiler, with a 2.5 µm stylus, was used. Density of the copper islands were estimated by performing image analysis of the SEM image in ImageJ software. RF Measurements: We used a spectrum analyzer (Rigol DSA815-TG) with a stub tuner (Maury microwave 1878A triple stub tuner) to measure the spectral power. The stub tuner was used to match the input impedance of the micro-coils to the output impedance of the RF power amplifier. To generate the RF input signals for the coils, we used a RF Signal Generator (Rigol DSG830) with a RF power amplifier (NuPower 13G05A Power Amplifier). B. Fabrication Procedure 1 Sample preparation: First, samples are cleaned with a soft cloth and ethanol/acetone and then are rinsed with ethanol and DI water. FR4 (1/16” thick Fiberglass-Reinforced Plastic, G-10/FR4 grade, Circuit Board)/Rogers 3210 (Rogers Corporation RO3210 Woven-Glass Reinforced PTFE Laminate) samples (43 mm × 33 mm) are cut with a diamond saw (Diamond Laser 5000) and are rinsed with ethanol and DI water. The copper on the substrates is electro-etched to form a rough and non-conductive surface at equilibrium current of 30 – 35 mA (@ 3V) (23.9 – 27.9 A/m2) with copper sulfate with 65.0 g/L±2 g/L Cu basis (high-speed bright copper electroplating solution, Sigma Aldrich) pumping rate of 0.5 mL/min with a syringe pump (World Precision Instruments Single-Syringe Pump)(Fig. 1B). Formation of bubbles is essential to clean the surface. 11 ACS Paragon Plus Environment


Sputtering: Before starting the sputtering, the surface of the substrates is cleaned in-situ by reverse biasing the sample plate at around 25 W for 1 min at 30 mT. The samples are metalized with copper at 100 W RF with a rate of 1.5 Å/s rate for 20 min to form a 180 nm copper. Photolithography: Photo-resist AZ 9260 is spin-coated at 2,000 RPM for 60 s and baked in a convection oven for 45 min to 1 h at 85 – 90 °C. To minimize the contact points of the substrate with the tray, we isolated the samples from inadvertent conduction heating. Samples are then exposed with Karl Suss MA4 mask aligner for 288 s (12 rounds of 24 s exposure with 24 s wait for gaps in between). Samples are then developed in AZ 435 for 7 – 10 min. Any trace residues from photoresist are etched with an Autoglow 100 Asher O2 plasma at 150 W for 1 min under pressure of 0.5 – 1 Torr. Electroplating: Copper electroplating in a high-speed bright copper electroplating solution (Sigma Aldrich) is performed in to increase the trace height for 6 min with 150 mA (limited at 1 V). Finally, the photoresist is stripped with acetone and rinsed with IPA, and the substrate is submerged in a dilute nitric acid solution (i.e., 10 mL HNO3 in 200 mL DI water) to remove the undesired seed layer under the just removed photoresist. C. Fabrication Procedure 2 Sample preparation: The sample preparation is similar to that of the fabrication procedure 1, except the FR4/Teflon (1/16″ thick Fiberglass-Reinforced Plastic G-10/FR4 grade board and 1/16″ inch thick Flame-Retardant Garolite Sheet 6″×6″) substrates that we used here were bare substrates without any copper sheet on them. Sputtering: Similar to the in-situ cleaning process in procedure 1, the substrate is cleaned. The metallization procedure is different from that of the fabrication procedure 1. Here the samples are


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metalized with one of the following two procedures for depositing the seed layers:  Ti on FR4 then Cu. 1. Sputter 20 nm of Ti @ 190 W RF with 1 Å/s rate for 3 min and 20 s. 2. Sputter 150 nm of Cu @ 100 W RF with 1.2 Å/s rate for 19 min and 20 s.  Ti on FR4 then Au. 1. Sputter 20 nm of Ti @ 190 W RF with 1 Å/s rate for 3 min and 20 s. 2. Sputter 150 nm of Au @ 60 W RF with a rate of 1.3 Å/s for 20 min. Photolithography and electroplating: The photolithography and electroplating steps are similar to those of the fabrication procedure 1. Both of these two seed layer deposition recipes (i.e., Ti/Cu and Ti/Au) yielded weak adhesion traces which could not pass the tape test. References: (1) (2) (3) (4) (5) (6) (7)

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TOC figure Copper

PCB Substrate

PCB Substrate

Ultra-fine Traces


A New Approach for Micro-fabrication of Printed Circuit Boards

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