All solid-state synaptic transistor with high temperature stability using

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Functional Inorganic Materials and Devices

All solid-state synaptic transistor with high temperature stability using proton pump gating of strongly correlated materials Chadol Oh, Minguk Jo, and Junwoo Son ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.9b00392 • Publication Date (Web): 10 Apr 2019 Downloaded from http://pubs.acs.org on April 10, 2019

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ACS Applied Materials & Interfaces

All solid-state synaptic transistor with high temperature stability using proton pump gating of strongly correlated materials

Chadol Oh, Minguk Jo, and Junwoo Son*

Department of Materials Science and Engineering (MSE), Pohang University of Science and Technology (POSTECH), Pohang 37673, Republic of Korea

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Abstract Designing energy-efficient artificial synapses with adaptive and programmable electronic signals is essential to effectively mimic synaptic functions for brain-inspired computing systems. Here, we report all-solid-state three-terminal artificial synapses that exploit proton-doped metalinsulator transition in a correlated oxide NdNiO3 (NNO) channel by proton (H+) injection/extraction in response to gate voltage. Gate voltage reversibly controls H+ concentration in the NNO channel with facile H+ transport from H+-containing porous silica electrolyte. Gateinduced H+ intercalation in the NNO gives rise to non-volatile multi-level analog states due to H+induced conductance modulation, accompanied by significant modulation of the out-of-plane lattice parameters. This correlated transistor operated by a proton pump shows synaptic characteristics such as long-term potentiation and depression, with nonvolatile and distinct multilevel conductance switching by a low voltage pulse ( 50 mV), with high energy efficiency (~ 1 pJ), and tolerance to heat ( 100 °C). These results will guide development of scalable, thermally-stable solid-state electronic synapses that operate at low voltage.

Keywords: synaptic transistor; artificial synapse; ionotronics; proton pump; metal-insulator transition *[email protected]


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Introduction Biological neural networks exhibit excellent computing efficiency by only consuming a very small amount of energy per event due to massively-parallel information processing.1,

2

Information processing and transmission are simulateneously modulated by ionic fluxes between neurons, which are interconnected to each other by synapses in a complex network (Fig. 1a).3, 4 As an example of the functions of a synapse, plasticity contributes to a computation by increasing (potentiation) or decreasing (depression) a synaptic weight as a result of neuronal activities of presynaptic and postsynaptic cells.5 The responsivity of a postsynaptic neuron to stimulation by a presynaptic neuron underlies learning and memory in a brain by strengthening (or weakening) the connection between neurons (i.e., synaptic weight). Therefore, the foundation of learning and memory in neural systems is based on the “synaptic plasticity” (i.e., the change of synaptic weights). Likewise, artificial electronic synapses with adaptive and programmable electronic signals between neurons are essential components for artificial intelligence that emulate synaptic functions in biological processing.5-10 Although efficient algorithm for artificial intelligence have been recently developed as demonstrated in recent accomplishment in the areas of pattern recognition and machine learning, currently-available neuromorphic circuits (i.e., electronic devices using traditional complementary metal-oxide-semiconductors) require a huge amount of memory and huge amounts of energy.1, 10, 11 Therefore, new neuromorphic hardwares that consume little power are being sought in order to overcome the limitation of the current neuromorphic devices.10 New types of neuromorphic electronic devices with long-term potentiation (LTP) and depression (LTD), in which the conductance is determined by external spike history, have been demonstrated mostly in two-terminal memristors,5, 8, 12-15 such as phase change memory (PCM),16 3 ACS Paragon Plus Environment


resistive switching memory (RRAM),9 or conductive bridge memory (CBRAM).5 Although use of crossbar structure in the memristers allows energy-efficient update of synaptic weights in parallel, two-terminal memristers suffer from excessive noise,17 write nonlinearities,18, 19 and high supply voltage20, 21 owing to the stochastic nature of the conducting path. Furthermore, unlike biological synapses, the two-terminal devices cannot perform learning (i.e., LTP and LTD) and signal transmission concurrently.22 For example, the conductance states of the devices cannot be altered reliably during the weight-update process. More importantly, the programming energy for current two-terminal artificial synapses (> 100 fJ) is still higher than that for biological synapses (~ 10 fJ), so new electronic synapse hardware must be developed to achieve the combined energy efficiency and accuracy of biological synapses.6, 23 Three-terminal synaptic transistors that switch the channel conductance by reversible ionic doping of the channel layer have been suggested as a new path toward development of energyefficient neuromorphic devices.12, 15, 24-26 In all three-terminal devices, an electric field applied to the gate electrolyte can modulate the concentration of ionic defects in the channel of electricallyswitchable materials, so they show potential as non-volatile and multi-bit transistors for braininspiring analog computation.27-29 However, all devices, in particular those based on organic materials and ionic liquids, have inherent limits to stability at the operating temperatures of semiconductor devices (~ 100 °C). Moreover, relatively large energy consumption (i.e., large gate voltage and long time for switching) is required in three-terminal devices that use simple widebandgap oxides (WO3 or ZnO) as a channel layer due to the fact that conductance modulation in these oxides is not sensitive to the electron doping supplied by atomic defects (e.g., protons (H+), lithium ions).30 Here, we report all-solid-state three-terminal artificial synapses that exploit H+-doped 4 ACS Paragon Plus Environment

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metal-insulator transition (MIT) in a correlated oxide NdNiO3 (NNO) channel. The MIT is induced by gate voltage pulse that drives a proton pump from H+-containing solid-state porous silica electrolyte. Gate bias strongly injects H+ into the NNO channel with facile H+ transport with high ionic mobility from the electrolyte; this H+ intercalation in the correlated materials induces nonvolatile multi-level analog states as a consequence of H+-induced MIT, accompanied by significant modulation of the out-of-plane lattice parameters. By using this correlated transistor operated by a proton pump, we successfully achieved synaptic characteristics, such as long-term potentiation and depression, with nonvolatile and distinct multilevel conductance switching by a low voltage pulse ( 50 mV), with low energy requirement (~ 1 pJ), as well as thermally robust operation ( 100 °C). These excellent characteristics are attributed to responsive post-synaptic conductance modulation at low amplitude and duration of pre-synaptic voltage pulse, which is possibly due to the extreme sensitivity of electrical properties induced by H+ in correlated materials.

Results and Discussion We designed a three-terminal correlated synaptic transistor (Figs. 1b, c) to emulate the change of synaptic weight in biological neural systems (Fig. 1a). Prior to the fabrication of threeterminal transistors, high-quality 10-nm-thick correlated NNO epitaxial films as post-synaptic channels were grown on (001)-oriented SrTiO3 (STO) or LaAlO3 (LAO) substrate by pulsed laser deposition (Fig. S1a). The NNO films were grown coherently on both substrates (aSTO = 3.91 Å, aLAO = 3.79 Å) as confirmed by the reciprocal space mapping (Figs. 1d, e); the NNO film on STO was subjected to ~ + 2.3 % tensile stress, and the NNO film on LAO was subjected to ~ – 0.5 % compressive strain, to accommodate lattice mismatch between films and substrates.21, 5 ACS Paragon Plus Environment

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Temperature-dependent resistivity of both NNO films clearly showed metal-insulator transition at temperature TMIT below room-temperature (NNO on STO, TMIT ~ 220 K, NNO on LAO. TMIT ~ 150 K); these results confirm that NNO is a correlated material at the phase boundary between metal and insulator due to strong correlation in d orbitals (Fig. S1b).31-33 Then, three-terminal devices with 300-nm-thick porous silica pre-synaptic gate (i.e., H+stimulated synaptic transistors) were fabricated using photolithography (Fig. S2).34 Porous silica absorbs vapor water from the ambient due to the capillary effect of the nanopores, so a pre-synaptic potential Vpre (i.e., gate voltage) from the gate electrode electrolyzes water to H+ and OH- and simultaneously transports those ions in the film (Fig. 1b)34: Vpre drives directional H+ movement by H+ hopping between hydroxyl groups on the surface of silica. Artificial synaptic functions can be mimicked in our three-terminal synaptic transistors, because analog conductance switching by H+ migration into the correlated channel (Fig. 1b) emulates the change of synaptic weight in biological neural systems (Fig. 1a). The Vpre pulses across the porous silica solid-state H+ conductor gradually influence the channel conductance G in NNO between source and drain electrodes. Therefore, G of the NNO channel indicates the synaptic weight of the connection between pre-synaptic and post-synaptic neurons to mimic synaptic plasticity in biological synapse. Due to the sensitive and non-volatile response of G in NNO by H+ doping,21, 25 each synaptic weight (i.e., G) can be modulated by Vpre from gate electrodes to yield multi-bit and non-volatile switching. To confirm reversible injection and extraction of H+ in the NNO channel by Vpre, the chemical composition in localized areas (33.3 μm × 33.3 μm, below the gate electrodes) was characterized in the channel before and after positive Vpre and subsequent negative Vpre (Figs. 1e, 6 ACS Paragon Plus Environment

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f, Fig. S3) by using depth profiling of dynamic secondary ion mass spectroscopy (D-SIMS). After application of positive Vpre, the intensity of the H signal in the NNO layer increased by an order of magnitude (broken line in Fig. 1e); this result confirms that H+ in the porous silica reservoir are indeed intercalated into NNO channel when positive Vpre is applied. When negative Vpre was applied to induce extraction of H+, the increased H signal returned to that before the application of positive Vpre (dotted line in Fig. 1e). In contrast, application of Vpre did not cause any noticeable change in oxygen signal, which excludes oxygen vacancies as the origin of metal-to-insulator transition induced by Vpre (Fig. S3).8 The influence of gate-induced H+ injection on the NNO channel current Ipost (i.e., channel current) was explored at constant post-synaptic potential (i.e., source-drain voltage, Vpost = 0.5 V) after initial application of pre-synaptic voltage pulse trains (Vpre = + 2.0 V) for 10 min, followed by Vpre pulses with opposite polarity (Vpre = – 2.0 V) for 10 min (Fig. 2a). The Ipost modulation by Vpre was reversible, non-volatile and monotonic in NNO channels grown on LAO or STO substrates: the ratio Ipost to initial Ipost,0 (Ipost/Ipost,0) gradually decreased by more than six orders of magnitude under positive Vpre; upon application of a positive Vpre, H+ flow from the presynaptic gate into the postsynaptic channel through the solid-state H+ electrolyte; this process protonates the NNO while electrons flow through the source. As a result, the electron configuration of Ni ions in NNO changes from Ni3+ (t2g6eg1) to a strongly correlated Ni2+ (t2g6eg2) during electron doping by H incorporation,21,

25, 35

so the electrons become strongly localized and the electronic

conductivity of the NNO decreases significantly. As soon as Vpre was switched to the opposite polarity (– 2 V), the Ipost reversibly increased to the initial state, which indicates that removal of H+ from the channels returned the NNO channel to the original metallic phase.



Despite Vpre-induced change of Ipost by six orders of magnitude in both NNO channels by H+ injection, the transition kinetics of NNO channels were different on the two substrates: On STO, Ipost/Ipost,0 decreased rapidly, but on LAO, Ipost/Ipost,0 decreased in two steps (i.e., initial 10-2 decrease to ~ 50 s, then subsequent saturation until 300 s, followed by 10-4 decrease of Ipost/Ipost,0). The origin of abnormal saturation the compressive-strained NNO channel at intermediate H+ incorporation is not understood, but similar resistance saturation has been observed in NNO and SmNiO3 films during thermally-induced protonation.21,

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This abnormal behavior might be

attributed to two different bonding sites of H+ with different binding energy in NNO lattice. The biaxial-strain-dependent post-synaptic current modulation in NNO channel can be further seen in the measurement of Ipost/Ipost,0 after alternating application of positive and negative presynaptic pulse for 120 s with increasing magnitude of voltage bias (from | Vpre | = 1 V to 3 V) (Fig. 2b). The “threshold” voltage for Ipost/Ipost,0 < 10-4 in NNO/STO (Vth ~ 1.5 V) was lower than in NNO/LAO (Vth ~ 2.2. V); this difference further confirms that tensile strain facilitates H+ incorporation and H+-induced metal-to-insulator transition in NNO under the application of positive Vpre. The faster H+-induced Ipost modulation in tensile-strained NNO film (i.e., on STO) than in compressive-strained NNO films (i.e., on LAO) may occur because tensile strain increases bulk H+ conductivity toward the out-of-plane direction,36 and increases the exchange kinetic constant at the silica/NNO interface with reduced Ni-O orbital interaction.37 Therefore, these decreases in limiting factors in the bulk and at the interface accelerate H+ kinetics in tensilestrained NNO channel, and thereby reduce the switching energy that is required to modulate channel G more efficiently. The Ipost modulation by Vpre was further explored in the tensile-strained NNO channel (i.e., 8 ACS Paragon Plus Environment

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on STO) by applying Vpre sweeps with increasing sweep widths from |Vpre| ≤ 0.6 V to |Vpre| ≤ 1.2 V at a sweep rate of 10 mV/s at constant Vpost = − 0.5 V. The transfer curves (Fig. 2c) show that Ipost/Ipost,0 could be reversibly switched between low and high conductance states. The curves also showed a clockwise hysteresis loop (i.e., decrease of Ipost under positive Vpre, and increase of Ipost under negative Vpre: initially, G changed to low under positive Vpre, but to high under negative Vpre. Interestingly, the modulation of Ipost and hysteresis of the transfer curve widened as the sweep width increased, but Ipost/Ipost,0 eventually saturated at 10-6 with |VG| ≤ 1.2 V of sweep width. Increased H+ injection with increase in the electric field leads to sufficient protonation in the entire NNO channel along the thickness direction due to the diffusion-limited conductance modulation by gate voltage. Due to the reversible response of H+ depending on the polarity of gate bias, the H+ tends to move toward the porous silica/NNO interface under the positive Vpre, or to depart from it under negative Vpre. The reduction of the Ni valence states by H+ injection (Ni3+ to Ni2+) is accompanied by lattice expansion due to the increased Ni-O bond length along the out-of-plane direction induced by the increased Ni ionic radius.35 To further explore the underlying mechanism of this reversible switching induced by H+ gating, structural lattice deformation was detected using spatially resolved synchrotron x-ray micro-diffraction mappings with a focused x-ray beam with a size of 3 μm × 15 μm (vertical × horizontal) in the entire channel of three-terminal correlated synapse transistors (Fig. 1c) after application of Vpre with different polarity. Upon application of Vpre along the porous silica that contained H+, the local intensity of the Bragg diffraction for H-NNO (qz = 2.89 Å-1, Fig. 3a, Fig. S4) and NNO (qz = 3.27 Å-1, Fig. 3b, Fig. S4) were laterally scanned to detect changes in the out-of-plane lattice parameter in the NNO channel. After application of Vpre = + 2.0 V for 5 min to the gate electrode to maximize hydrogen incorporation, the peaks at qz = 9 ACS Paragon Plus Environment


2.89 Å-1 appeared (yellow signal in Fig. 3a) at the expense of a reduction of peak intensity at qz = 3.27 Å-1 (reduced signal in Fig. 3b) over the entire area of channel underneath gate electrodes; this structural modulation represents the evolution of insulating H-NNO phases under positive Vpre. After the polarity of Vpre was switched to − 2.0 V for 5 min, only qz = 3.27 Å-1 peaks (yellow signals in Fig. 3d) appeared; qz = 2.89 Å-1 peaks did not occur (no signal in Fig. 3c) in the entire channel and electrode areas, which represents reversible recovery of metallic NNO phase by application of negative Vpre. This reversible change indicates that H+ injected by Vpre induced the phase transition between metallic NNO and insulating H-NNO with structural modulation over the entire area of the gate electrodes. The reversible incorporation of H+ into the entire area leads to less cycle-to-cycle variation in our 3-terminal devices, which is responsible for improving the accuracy in neuromorphic devices. Based on our characterization, we hypothesize an operation principle for the reversible Ipost modulation that was induced by Vpre in our three-terminal H+ synapse transistors. Application of positive Vpre drives H+ from porous silica H+ conductor and electrons from the source electrode, and injects them into the NNO channel by electric-field-driven coupled ionic-electronic diffusion (i.e., H+ injection coupling with electron supply). Moreover, Vpre higher than 1.23 V electrolyzes water into H+ and OH− in the silica, and thus silica can be continuous source of electroactive H+. Sufficient H+ injection across the porous silica/NNO interfaces is facilitated by the facile electrochemical reaction of multivalent oxide (i.e., Ni2+/Ni3+ in our study) with H+ by charge transfer under an electric field. Moreover, the H+ can enter the interstitial sites of NNO lattice by subsequent diffusion into the bulk channel. The electrons that are transferred from H+ interstitials change the electron occupancy of d electrons in Ni (Ni3+  Ni2+); this change results in an emergence of insulating H-NNO phase, and significant decrease of Ipost. Since the electrolyte can 10 ACS Paragon Plus Environment

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block electronic charge transport, so the non-volatile state of G can be maintained after the application of Vpre. When negative Vpre is applied to induce reversal, H+ are removed gradually from the silica/NNO interfaces by the deprotonation reaction (HxNNO → NNO + xH+ + xe-); this process explains why Ipost modulation can be reversed by controlling the H+ injection/extraction in correlated oxides. The ionic modulation of G resembles the transmission process in biological synapses, which can be emulated by the nonvolatile gradual modulation of Ipost with multilevel nonvolatile states of G in our correlated H+ transistors. In particular, these transistors can be applicable to emulate LTP and LTD in synapses that are the basic building blocks for neuromorphic computing. To demonstrate the multi-level states that are required for analog computation, the correlated H+ transistors were operated by sending voltage pulse trains to the gate electrode. For example, Ipost was measured right after the consecutive application of positive Vpre pulse trains (+ 0.7 V) with duration of 5 s for LTD, and application of negative Vpre (– 1.0 V) for 5 s for LTP at room temperature (Fig. 4a). LTD was emulated by continuous decrease of G from 400 μS to 300 μS in eight distinct nonvolatile states with incremental change (Fig. 4b). Subsequently, by switching the polarity of the Vpre pulse, G increased incrementally in eight distinct nonvolatile states from 300 μS to its original value (~ 400 μS) as a demonstration of LTP (Fig. 4b). More importantly, both NNO and porous silica exhibit more thermal stability than materials made of organic or polymer materials, so this device that is made entirely of inorganic materials can operate without any stability and/or reliability issues at device operating temperatures up to 100 °C. Indeed, G gradually changed from 350 μS to 500 μS during application of Vpre pulse (+ 0.7 V during LTD; – 1.0 V during LTP) with eight distinct nonvolatile states at 100 °C (Fig. 4c). Even at high temperature, our devices store information in their multiple post11 ACS Paragon Plus Environment


synaptic states of G (i.e., the modulation of synaptic weight), which are programmed by the application of Vpre pulses. Almost symmetric switching can be achieved in both potentiation and depression process, which is advantageous for accurate neuromorphic computing.18 Interestingly, modulation in G by Vpre pulse at 100 °C is greater than that at room temperature; this difference is attributed to the thermally increased mobility (or diffusivity) of the H+ in the NNO lattice as temperature increases.35 In biological synapses, the synaptic weight is modulated by adjusting the number or frequency of stimuli. Likewise, the post-synaptic state (i.e., synaptic weight) in electronic synapse is programmed by varying the amplitude or the duration of the Vpre pulse.12, 15 When Vpre pulses with different amplitudes were applied for 2 s at 100 °C in our three-terminal devices, the change ΔGpost in G was linearly proportional to the pulse amplitude at |Vpre| < 200 mV, and quadratically proportional to the pulse amplitude at |Vpre| > 200 mV (Fig. 4d). The minimum Vpre pulse amplitude to achieve measurable ΔGpost (~ 0.36 μS) was 50 mV; this leads to significantly lower voltage amplitude of Ipre for synaptic weight transfer to post-synaptic current than other two-terminal artificial synapses.12 Vpre pulse duration can also be used to modulate the degree of synaptic weight in post-synaptic channels. ΔGpost increased roughly linearly as pulse duration increased (Fig. 4e). In particular, synaptic weight can be modulated by using very short pulse down to 1 ms with 4-V pulse amplitude in our artificial synapse for neuromorphic applications (Fig. S5a), which is short enough to mimic biological synapses6 and comparable to the switching rate in organic electrochemical transistor.38 Our designed three-terminal artificial synaptic transistor is advantageous for neuromorphic application compared to two-terminal artificial synapse in many respects. First, the barrier for non12 ACS Paragon Plus Environment

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volatility is separated from the barrier for switching states, allowing for small Vpre due to a low energy barrier for ion transfer between solid-state electrolyte and the conductance channel while maintaining non-volatility.12, 22 Second, by exploiting the reversible injection and extraction of H+ (i.e., the smallest element), resistance switching can reversibly occur without significant modification of crystal lattice framework or structural transformation,24, 35, 39 such as filament formation or phase transformation that are necessary in many memristive devices. Injection and extraction of H+ from the lattices with high ionic conductivity is reversible without breaking the lattice framework,24, 34, 35, 39 so pulse-to-pulse conductance fluctuation is negligible and “write” noise is low; this consistent response improves the accuracy of Vpre-modulated synaptic weight update in neuromorphic systems. Finally, the H+ electrolytes (porous silica) and synaptic channel (NNO) both have high H+ conductivity and thermal stability at device-operating temperature. For example, ReNiO3 (Re = rare earth) channel showed high H+ conductivity (~10-2.8 S/cm at 300 K) with low activation energy (~ 0.3 eV),35, 40 which also facilitates the responsive ∆Gpost modulation at small Vpre pulse amplitude and duration. More importantly, three-terminal transistor synapses use much less energy than twoterminal synapses. In the three-terminal transistor geometry, the energy consumption per synaptic event can be obtained by calculating dE = Vpre x Ipre x dt and integrating over time , where Vpre, Ipre, dt are pre-synaptic voltage, pre-synaptic current, the duration time of pulse voltage, respectively6, 12; Vpre, Ipre, and dt should be minimized to reduce the energy consumption. First, Ipre is much smaller in a three-terminal synapse than in a two-terminal synapse due to lower electronic leakage current through gate electrolytes (Fig. S5b).12,

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Furthermore, because H+ migration

occurs uniformly over the entire region of the gate electrode, Ipre can be minimized by reducing the area of the gate electrode, whereas the pulse amplitude and the pulse length remain constant.12 13 ACS Paragon Plus Environment


Based on the minimum Vpre (~ 50 mV at 100 °C) in our device, the minimum energy consumption of our device was estimated to be 1.8 pJ at 100 °C (in gate area of 200 μm × 20 μm ), which is comparable to two-terminal electronic synapses that have much smaller device size than this (Fig. 4f).6 Due to the high-temperature stability of our all-inorganic electrochemical synapse (> 150 °C, Fig. S6), energy consumption was further reduced by simply raising the operating temperature to increase the speed of H+ migration. Compared to a biological synapse (~ 10 fJ), our artificial synapse consumes more energy, but it could be further reduced by downscaling the gate area in scalable solid-state transistors (i.e., by reducing Ipre). Extrapolation of the line suggests that programming energy of 10 fJ could be achieved in an artificial electronic synapse that has a size of ~ 5 μm × 6 μm. The low energy consumption in our three-terminal artificial synapse is attributed to the responsive ∆Gpost at low Vpre and small dt, as well as the low Ipre. More importantly, the electrical conductance in correlated quantum materials such as NNO are extremely sensitive to Vpre-induced protonation. Due to extremely sensitivity near the phase boundary under doping, in principle, small energy consumption can transform the materials to a different electronic phase; thereby amplifying resistance modulation in correlated materials. For example, electron doping by hydrogens in metallic ReNiO3 suddenly opens its bandgap by 3 eV by strong electron localization and correlation in Ni2+ ions when the compound was doped with one electron per nickel; this gap opening yields dramatic resistance modulation up to 106.25 Likewise, small injection of H+ as an electron donor by Vpre pulses of a low Vpre and small dt can generate heavily amplified output with active gain and thus induce a detectable synaptic weight (∆Gpost) in an NNO channel.


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Conclusion In summary, an all-solid-state three-terminal artificial synapse was achieved by using extremely sensitive metal-insulator transition in correlated oxide NNO channel by a proton pump from the gate electrolyte. Gate-voltage-controlled H+ intercalation induces non-volatile and stable multi-level analog states in the NNO channel, accompanied by significant modulation of the outof-plane lattice parameters. By using this correlated transistor operated by a proton injection/extraction, persistent long-term potentiation and depression were demonstrated with nonvolatile and distinct multilevel analog switching, high energy efficiency and stability to temperatures up to 100 °C. The sensitive response of correlated materials with ionic motion of H+ and thermal stability in these correlated synaptic transistors offers an opportunity to develop energy-efficient and scalable neuromorphic devices.



Methods Device fabrication The 10-nm-thick epitaxial NdNiO3 films were grown on (001)-oriented SrTiO3 and LaAlO3 substrates by pulsed laser deposition with base pressure ~ 10-6 Torr in the growth chamber. A KrF excimer laser (λ = 248 nm) was focused onto a stoichiometric polycrystalline NNO rotating target at fluence ~ 2.2 J/cm2 and repetition rate of 10 Hz. The films were grown in oxygen ambient of 300 mTorr and at growth temperature of 650 °C to optimize the temperature-dependent metal-toinsulator transition of NNO. After growth, the samples were cooled to room temperature for 30 min. To fabricate three-terminal synaptic transistors (Fig. S2) that use the optimized 10-nmthick NNO films, NNO channels were first patterned with channel width of 200 μm and various channel lengths (20 μm ~ 2000 μm) by photolithography (SUSS MicroTec.) and chemical etching with hydrochloric acid. Then, 50-nm-thick Pt electrodes as source and drain contacts were deposited by radio-frequency (RF) magnetron sputtering with RF power of 40 W, Ar pressure of 10 mTorr and base pressure of ~ 10-7 Torr. The thickness of Pt electrodes was determined using X-ray reflectormeter. After that, 300-nm-thick porous sol-gel silica films were coated as described elsewhere.41 Porous sol-gel silica was prepared by mixing tetraethyl orthosilicate, ethanol, water and phosphoric acid (85 wt%) in molar ratio 1:18:5.55:0.02. Then, the mixture was stirred at room temperature for 1 h, then placed in an oven at 60 °C for 2 h to accelerate the polymerization of Si-O-Si chains, followed by spin-coating of the solution on the sample at 3000 rpm for 30 s, and baking at 120 °C for 30 min. The coating process was repeated twice to avoid gate leakage current through the porous silica layer. Thereafter, 30-nm-thick Pt electrodes for gate contact were 16 ACS Paragon Plus Environment

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deposited using RF magnetron sputtering with base pressure of ~ ~ 10-7 Torr and patterned using a lift-off process. Finally, to expose Ohmic contact for the source and drain, porous silica layers right above the Ohmic contact were patterned using photolithography, then etched for 45 s using a buffered oxide etchant.

Electrical Measurement The electrical characteristics of the three-terminal NNO devices were measured using semiconductor device analyzer (B1500A, Agilent) with source measurement unit in a temperaturevariable probe station under ambient conditions. The amplitude of each voltage was selected based on the purpose of each characterization. The temperatures for measurement were varied from room temperature to 100 °C. During the application of variable gate voltage (i.e., presynaptic voltage Vpre), the source-drain current (i.e., post-synaptic current Ipost) was measured by applying read voltage Vpost = 500 mV between source and drain. The channel conductance G was calculated as Vpost/Ipost. The transfer curves were obtained by applying Vpre sweeps with extending widths from |Vpre| ≤ 0.6 V to |Vpre| ≤ 1.2 V at a sweep rate of 10 mV/s at constant Vpost = − 0.5 V. For the measurement of Fig. 2a, Vpre pulse (gate pulse) with + 2.0 V of pulse amplitude was applied during 5 seconds. After the application of Vpre pulse, the channel current was measured during the Vpost application of + 0.5 V (source-drain voltage). This process was repeated to 120 times. As a reverse process, subsequently, Vpre pulse with - 2.0 V of pulse amplitude was applied with 5 seconds of pulse width. And then, the channel current was measured with the application of + 0.5 V of Vpost. This reversal process was also iterated to 120 times. For Fig. 4, the measurements were carried out by monitoring the conductance before and after applying Vpre with 2 s pulse length. And then, as a reverse application of Vpre, negative Vpre pulse was applied to recover the conductance to its 17 ACS Paragon Plus Environment


original equilibrium state.

D-SIMS For Dynamic Secondary Ion Mass Spectrometer (D-SIMS) analysis, a device was fabricated using 100-nm-thick NNO film grown on STO substrate. The SIMS measurements were performed using a Dynamic Secondary Ion Mass Spectrometer (IMS-4FE7, Caneca, France). The samples were bombarded with a beam of 6.0 kV Cs+ ions at –3.0 kV, so impact energy 9.0 kV was focused on an area of 150 m × 150 μm; SIMS data were taken in a region of 20 m x 20 μm within this area. The depth profiles of H, O were obtained by analyzing 1H and 18O, respectively.

Synchrotron X-ray diffraction The reciprocal space mapping of NNO thin films on STO and LAO substrates (Fig. 1d and 1e) were obtained using 3D X-ray scattering beamline in PAL. The in-situ X-ray diffraction in 3D X-ray scattering beamline in PAL was used to monitor the structural expansion of the 10nm-thick NNO thin film on LAO substrate decorated by Pt nanoparticles at the surface of the film as a function of exposure time to forming gas (5 % H2/95 % Ar) atmosphere at room temperature (Fig. S4). Spatially-resolved mapping on out-of-plane lattice parameter of post-synaptic NNO channel was monitored using 9C coherent X-ray scattering beamline in PAL after the application of the + 2 V and – 2 V of presynaptic potentials for 5 min. The X-rays with a photon energy of 8 keV were focused on a spot with 3 μm × 15 μm (vertical × horizontal) by using a Fresnel zone plate. The diffracted X-rays from the sample were acquired using a gated pixel array detector 18 ACS Paragon Plus Environment

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(Pilatus 100 K, Dectris Ltd.).



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Reference 1.

Sze, V.;

Chen, Y. H.;

Yang, T. J.; Emer, J. S., Efficient Processing of Deep Neural

Networks: A Tutorial and Survey. Proc. IEEE 2017, 105 (12), 2295-2329. 2.

Merolla, P. A.;

Arthur, J. V.;

Akopyan, F.;

Jackson, B. L.;

Esser, S. K.;

Appuswamy, R.;

Alvarez-Icaza, R.;

Imam, N.;

Guo, C.;

Taba, B.;

Cassidy, A. S.;

Nakamura, Y.;

Amir, A.;

Sawada, J.;

Brezzo, B.;

Flickner, M. D.;

Vo, I.;

Risk, W. P.;

Manohar, R.; Modha, D. S., A Million Spiking-Neuron Integrated Circuit with a Scalable Communication Network and Interface. Science 2014, 345 (6197), 668-673. 3.

Bean, B. P., The Action Potential in Mammalian Central Neurons. Nat. Rev. Neurosci.

2007, 8 (6), 451-465. 4.

Pereda, A. E., Electrical Synapses and Their Functional Interactions with Chemical

Synapses. Nat. Rev. Neurosci. 2014, 15 (4), 250-263. 5.

Jo, S. H.;

Chang, T.;

Ebong, I.;

Bhadviya, B. B.;

Mazumder, P.; Lu, W., Nanoscale

Memristor Device as Synapse in Neuromorphic Systems. Nano Lett. 2010, 10 (4), 1297-1301. 6.

Kuzum, D.;

Yu, S.; Wong, H. S., Synaptic Electronics: Materials, Devices and

Applications. Nanotechnology 2013, 24 (38), 382001. 7.

Hwang, S. K.;

Choi, J. R.;

Bae, I.;

Hwang, I.;

Cho, S. M.;

Huh, J.; Park, C.,

High-Temperature Operating Non-Volatile Memory of Printable Single-Wall Carbon Nanotubes Self-Assembled with a Conjugate Block Copolymer. Small 2013, 9 (6), 831. 8.

Shi, J.;

Ha, S. D.;

Zhou, Y.;

Schoofs, F.; Ramanathan, S., A Correlated Nickelate

Synaptic Transistor. Nat. Commun. 2013, 4, 2676. 9.

Yu, S. M.;

Gao, B.;

Fang, Z.;

Yu, H. Y.;

Kang, J. F.; Wong, H. S. P., A Low

Energy Oxide-Based Electronic Synaptic Device for Neuromorphic Visual Systems with 20 ACS Paragon Plus Environment

Page 21 of 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Tolerance to Device Variation. Adv. Mater. 2013, 25 (12), 1774-1779. 10.

Haensch, W.;

Gokmen, T.; Puri, R., The Next Generation of Deep Learning Hardware:

Analog Computing. Proc. IEEE 2018, 107 (1), 108-122. 11.

Partzsch, J.; Schuffny, R., Analyzing the Scaling of Connectivity in Neuromorphic

Hardware and in Models of Neural Networks. IEEE Trans. Neural Netw. 2011, 22 (6), 919-935. 12.

van de Burgt, Y.;

Agarwal, S.;

Lubberman, E.;

Marinella, M. J.;

Fuller, E. J.;

Keene, S. T.;

Faria, G. C.;

Alec Talin, A.; Salleo, A., A Non-Volatile Organic

Electrochemical Device as a Low-Voltage Artificial Synapse for Neuromorphic Computing. Nat. Mater. 2017, 16 (4), 414-418. 13.

Ohno, T.;

Hasegawa, T.;

Tsuruoka, T.;

Terabe, K.;

Gimzewski, J. K.; Aono, M.,

Short-Term Plasticity and Long-Term Potentiation Mimicked in Single Inorganic Synapses. Nat. Mater. 2011, 10 (8), 591-595. 14.

Strukov, D. B.;

Snider, G. S.;

Stewart, D. R.; Williams, R. S., The Missing Memristor

Found. Nature 2008, 453 (7191), 80-83. 15.

Fuller, E. J.;

Gedrim, R. B.;

El Gabaly, F.;

James, C. D.;

Leonard, F.;

Agarwal, S.;

Plimpton, S. J.;

Jacobs-

Marinella, M. J.; Talin, A. A., Li-Ion Synaptic Transistor for Low

Power Analog Computing. Adv. Mater. 2017, 29 (4), 1604310. 16.

Kuzum, D.;

Jeyasingh, R. G.;

Lee, B.; Wong, H. S., Nanoelectronic Programmable

Synapses Based on Phase Change Materials for Brain-Inspired Computing. Nano Lett. 2012, 12 (5), 2179-2186. 17.

Terai, M.;

Sakotsubo, Y.;

Kotsuji, S.; Hada, H., Resistance Controllability of

Ta2O5/TiO2 Stack ReRAM for Low-Voltage and Multilevel Operation. Ieee Electr Device L 2010, 31 (3), 204-206. 21 ACS Paragon Plus Environment


18.

Burr, G. W.;

Shenoy, R. S.;

Shelby, R. M.;

Narayanan, P.;

Sidler, S.;

Virwani, K.;

Page 22 of 33

di Nolfo, C.;

Giacometti, E. U.;

Jang, J.;

Boybat, I.;

Kurdi, B. N.; Hwang, H.,

Experimental Demonstration and Tolerancing of a Large-Scale Neural Network (165 000 Synapses) Using Phase-Change Memory as the Synaptic Weight Element. Ieee T Electron Dev 2015, 62 (11), 3498-3507. 19.

Boybat, I.; Le Gallo, M.;

Rajendran, B.;

Leblebici, Y.;

Nandakumar, S. R.;

Moraitis, T.;

Parnell, T.; Tuma, T.;

Sebastian, A.; Eleftheriou, E., Neuromorphic Computing with

Multi-Memristive Synapses. Nat. Commun. 2018, 9 (1), 2514. 20.

Wong, H. S. P.;

Raoux, S.;

Kim, S.;

Liang, J. L.; Reifenberg, J. P.;

Rajendran, B.;

Asheghi, M.; Goodson, K. E., Phase Change Memory. Proc. IEEE 2010, 98 (12), 2201-2227. 21.

Oh, C.;

Heo, S.;

Jang, H. M.; Son, J., Correlated Memory Resistor in Epitaxial

NdNiO3 Heterostructures with Asymmetrical Proton Concentration. Appl. Phys. Lett. 2016, 108 (12), 122106. 22.

Nishitani, Y.;

Kaneko, Y.;

Ueda, M.;

Morie, T.; Fujii, E., Three-Terminal

Ferroelectric Synapse Device with Concurrent Learning Function for Artificial Neural Networks. J Appl Phys 2012, 111 (12), 124108. 23.

Strachan, J. P.;

Torrezan, A. C.;

Medeiros-Ribeiro, G.; Williams, R. S., Measuring the

Switching Dynamics and Energy Efficiency of Tantalum Oxide Memristors. Nanotechnology 2011, 22 (50), 505402. 24.

Lu, N.;

Zhang, P.;

Zhang, Q.;

Zhang, D.;

Duan, Z.; Li, Z.;

Yang, W.;

Gu, L.;

Qiao, R.;

Wang, M.;

Nan, C. W.;

Wu, J.;

He, Q.;

Yang, S.;

Li, H. B.;

Yan, M.;

Wang, Y.;

Arenholz, E.;

Guo, J.; Zhou, S.;

Tokura, Y.; Yu, P., Electric-Field Control of Tri-

State Phase Transformation with a Selective Dual-Ion Switch. Nature 2017, 546 (7656), 124-128. 22 ACS Paragon Plus Environment

Page 23 of 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


25.

Shi, J.;

Zhou, Y.; Ramanathan, S., Colossal Resistance Switching and Band Gap

Modulation in a Perovskite Nickelate by Electron Doping. Nat. Commun. 2014, 5, 4860. 26.

Gkoupidenis, P.;

Schaefer, N.;

Garlan, B.; Malliaras, G. G., Neuromorphic Functions

in PEDOT:PSS Organic Electrochemical Transistors. Adv. Mater. 2015, 27 (44), 7176-7180. 27.

Rivnay, J.;

Inal, S.;

Salleo, A.;

Owens, R. M.;

Berggren, M.; Malliaras, G. G.,

Organic Electrochemical Transistors. Nat. Rev. Mater. 2018, 3 (2), 17086. 28.

Rivnay, J.;

Leleux, P.;

A.;

Khodagholy, D.;

Ferro, M.;

Ramuz, M.;

Sessolo, M.;

Strakosas, X.;

Williamson, A.;

Owens, R. M.;

Koutsouras, D.

Benar, C.;

Badier, J. M.;

Bernard, C.; Malliaras, G. G., High-performance Transistors for Bioelectronics through Tuning of Channel Thickness. Sci. Adv. 2015, 1 (4), e1400251. 29.

Friedlein, J. T.;

McLeod, R. R.; Rivnay, J., Device Physics of Organic Electrochemical

Transistors. Org. Electron. 2018, 63, 398-414. 30.

Yang, J. T.;

Ge, C.;

Du, J. Y.;

Huang, H. Y.;

He, M.;

Wang, C.;

Lu, H. B.;

Yang, G. Z.; Jin, K. J., Artificial Synapses Emulated by an Electrolyte-Gated Tungsten-Oxide Transistor. Adv. Mater. 2018, 30 (34), 1801548. 31.

Son, J.;

Jalan, B.;

Kajdos, A. P.;

Balents, L.; Allen, S. J.; Stemmer, S., Probing the

Metal-Insulator Transition of NdNiO3 by Electrostatic Doping. Appl. Phys. Lett. 2011, 99 (19), 192107. 32.

Scherwitzl, R.;

Zubko, P.;

Lezama, I. G.; Ono, S.;

Morpurgo, A. F.; Catalan, G.;

Triscone, J. M., Electric-Field Control of the Metal-Insulator Transition in Ultrathin NdNiO3 Films. Adv. Mater. 2010, 22 (48), 5517-5520. 33.

Heo, S.;

Oh, C.;

Eom, M. J.;

Kim, J. S.;

Ryu, J.;

Son, J.; Jang, H. M., Modulation

of Metal-Insulator Transitions by Field-Controlled Strain in NdNiO3/SrTiO3/PMN-PT (001) 23 ACS Paragon Plus Environment


Page 24 of 33

Heterostructures. Sci Rep-Uk 2016, 6, 22228. 34.

Jo, M.;

Lee, H. J.;

Oh, C.;

Yoon, H.; Jo, J. Y.; Son, J., Gate-Induced Massive and

Reversible Phase Transition of VO2 Channels Using Solid-State Proton Electrolytes. Adv Funct Mater 2018, 28 (39), 1802003. 35.

Zhou, Y.;

Guan, X.; Zhou, H.;

J.;

Tsuchiya, M.;

Ramadoss, K.;

Adam, S.;

Liu, H.;

Lee, S.; Shi,

Fong, D. D.; Ramanathan, S., Strongly Correlated Perovskite Fuel Cells.

Nature 2016, 534 (7606), 231-234. 36.

Fluri, A.;

Marcolongo, A.;

Roddatis, V.;

Wokaun, A.;

Pergolesi, D.;

Marzari, N.;

Lippert, T., Enhanced Proton Conductivity in Y-Doped BaZrO3 via Strain Engineering. Adv. Sci. 2017, 4 (12), 1700467. 37. M.;

Chen, J.; Shi, J.;

Zhou, Y.;

Middey, S.;

Jiang, J.;

Chen, N.;

Chen, L.;

Shi, X.;

Döbeli,

Chakhalian, J.; Ramanathan, S., Self-Limited Kinetics of Electron Doping in

Correlated Oxides. Appl. Phys. Lett. 2015, 107, 031905. 38.

Rivnay, J.;

Ramuz, M.;

Leleux, P.;

Hama, A.;

Huerta, M.; Owens, R. M., Organic

electrochemical transistors for cell-based impedance sensing. Appl. Phys. Lett. 2015, 106 (4), 043301. 39.

Yoon, H.;

Choi, M.;

Lim, T. W.;

Kwon, H.;

Ihm, K.;

Kim, J. K.;

Choi, S. Y.;

Son, J., Reversible Phase Modulation and Hydrogen Storage in Multivalent VO2 Epitaxial Thin Films. Nat. Mater. 2016, 15 (10), 1113-1119. 40.

Zuo, F.;

Barbour, A.; S.;

Panda, P.;

Wilkins, S.;

Comin, R.;

Kotiuga, M.; Narayanan, B.;

Rabe, K. M.;

Li, J.;

Kang, M.;

Cherukara, M.;

Mazzoli, C.;

Zhang, Z.;

Zhou, H.;

Sankaranarayanan,

Roy, K.; Ramanathan, S., Habituation Based Synaptic Plasticity

and Organismic Learning in a Quantum Perovskite. Nat. Commun. 2017, 8 (1), 240. 24 ACS Paragon Plus Environment

Page 25 of 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


41.

Shao, F.;

Yang, Y.;

Zhu, L. Q.;

Feng, P.; Wan, Q., Oxide-Based Synaptic

Transistors Gated by Sol-Gel Silica Electrolytes. ACS Appl. Mater. Interfaces. 2016, 8 (5), 30503055.



Acknowledgement We acknowledge support for this work by Samsung Research Funding & Incubation Center of Samsung Electronics under Project Number SRFC-TA1703-09, and by the Nuclear Energy R&D Program (2017M2A2A6A01020116) and the Creative Materials Discovery Program (2018M3D1A1058997) through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT.

Author contributions J. S. and C. O. conceived the idea and designed the study; C. O. and M. J. performed the film growth and processing, C. O. carried out x-ray diffraction, device fabrication and electrical measurement under the supervision of J. S.; J. S. and C. O. wrote the manuscript and all authors commented on it.

Supporting Information Supporting Information is available free of charge on the ACS Publications website.

XRD pattern and temperature-dependent resistivity curves of NdNiO3 films on SrTiO3 and LaAlO3 substrates; Schematics of device fabrication process; D-SIMS depth profile in NdNiO3, synchrotron XRD while protonating NdNiO3; channel conductance change by different pulse length; gate current measurement. (PDF) 26 ACS Paragon Plus Environment

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Competing financial interests The authors declare no competing financial interests.



Figure 1 | Device architecture and proton gating of strongly correlated NdNiO3 synaptic transistor. a. Schematic of biological synapse. b. Schematic of strongly-correlated NdNiO3 (NNO) synaptic transistor, where analog conductance switching by migration of H+ into the correlated channel emulates the change of synaptic weight in biological neural systems. c. Plane view of synaptic transistors with gate, source, drain electrodes taken by optical microscopy. Reciprocal space mapping around (103)pc plane of NNO thin films grown on d. SrTiO3 and e. LaAlO3 substrates; maps indicate that both NNO films were coherently grown on both substrates. f. Dynamic SIMS (D-SIMS) depth profile of hydrogen (1H) before and after positive Vpre, and subsequent negative Vpre along the gate area. After application of positive Vpre, the intensity of H in the NNO layer increased by an order of magnitude, which confirms that H+ in the porous silica reservoir are intercalated into NNO channel. When the polarity of Vpre was reversed to induce extraction of H+, the H signal returned to that before the application of positive Vpre. 28 ACS Paragon Plus Environment

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Figure 2 | The influence of gate bias (Vpre)-induced H+ injection/extraction on the NNO channel current Ipost. a. Strain-dependent gate-induced H+ kinetics of NNO channels:

Ipost/Ipost,0

decreased rapidly in tensile-strained NNO films on STO substrates, but Ipost/Ipost,0 decreased in two steps in compressive-strained NNO films on LAO substrates. b. Ipost/Ipost,0 after alternating application of positive and negative Vpre for 120 s with increasing magnitude of voltage bias (from |VG| = 1 V to 3 V). c. Transfer curves of the NNO synaptic transistor by applying Vpre sweep with extending sweep widths from |Vpre| ≤ 0.6 V to |Vpre| ≤ 1.2 V with sweep rate of 10 mV/s at constant Vpost = − 0.5 V. Ipost/Ipost,0 could be reversibly switched between low and high conductance states with clockwise hysteresis loop.



Figure 3 | Vpre-induced lattice deformation by proton gating on the NNO channel. Local intensity of Bragg diffraction a. of hydrogenated NNO (HNNO) (q = 2.89 Å-1) and b. NNO (q = 3.27 Å-1) after initial application of Vpre = + 2.0 V, and that c. of hydrogenated NNO (HNNO) (q = 2.89 Å-1) and d. NNO (q = 3.27 Å-1) after subsequent application of Vpre = − 2.0 V. X-ray signal was scanned by using spatially-resolved synchrotron x-ray micro-diffraction mappings with focused x-ray beam with a size of 3 μm × 15 μm (vertical x horizontal) in the entire channel of three-terminal NNO synapse transistors.


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Figure 4 | Synaptic behavior for the emulation of biological synapse in our correlated proton transistors with high temperature stability. a. Alternating long-term potentiation (LTP) and long-term depression (LTD) in synapses b. at room temperature and c. at 100 °C a. under the consecutive application of positive Vpre pulse trains (= + 0.7 V) with the pulse duration of 5 s for LTD and application of negative Vpre pulse (= – 1.0 V) for 5 s for LTP. LTD and LTP were emulated by continuous change of conductance, which shows eight distinct nonvolatile states. The post-synaptic state (i.e., synaptic weight) in electronic synapse is programmed by varying d. the amplitude or e. the duration of the Vpre pulse. f. The estimated energy consumption of our synaptic transistors as a function of device area operated at 100 °C. By following the extrapolated line, the



programming energy compared to biological synapse (< 10 fJ) can be achieved in several micron size electronic synapse (< 5 μm × 6 μm).


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TOC graphic


All solid-state synaptic transistor with high temperature stability using

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