Alloyed 2D Metal–Semiconductor Heterojunctions: Origin of Interface

Aug 23, 2016 - (26, 27) Figure 3a,b shows the threshold voltage shifts with increasing stress durations and the hot-carrier lifetimes with increasing ...
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Letter pubs.acs.org/NanoLett

Alloyed 2D Metal−Semiconductor Heterojunctions: Origin of Interface States Reduction and Schottky Barrier Lowering Yonghun Kim,† Ah Ra Kim,† Jin Ho Yang,‡ Kyoung Eun Chang,‡ Jung-Dae Kwon,† Sun Young Choi,† Jucheol Park,§ Kang Eun Lee,∥ Dong-Ho Kim,† Sung Mook Choi,⊥ Kyu Hwan Lee,⊥ Byoung Hun Lee,‡ Myung Gwan Hahm,*,# and Byungjin Cho*,† †

Department of Advanced Functional Thin Films, Surface Technology Division, ∥Composites Research Division, and Electrochemistry Department, Surface Technology Division, Korea Institute of Materials Science (KIMS), 797 Changwondaero, Sungsan-Gu, Changwon, Gyeongnam 51508, Republic of Korea ‡ School of Materials Science and Engineering, Gwangju Institute of Science and Technology (GIST), 261 Cheomdan-gwangiro, Buk-Gu, Gwangju 61005, Republic of Korea § Structure Analysis Group, Gyeongbuk Science and Technology Promotion Center, Future Strategy Research Institute, 17 Cheomdangieop 1-ro, Sangdong-myeon, Gumi, Gyeongbuk 39171, Republic of Korea # Department of Materials Science and Engineering, Inha University, 100 Inharo, Nam-Gu, Incheon 22212, Republic of Korea ⊥

S Supporting Information *

ABSTRACT: The long-term stability and superior device reliability through the use of delicately designed metal contacts with two-dimensional (2D) atomic-scale semiconductors are considered one of the critical issues related to practical 2D-based electronic components. Here, we investigate the origin of the improved contact properties of alloyed 2D metal−semiconductor heterojunctions. 2D WSe2-based transistors with mixed transition layers containing van der Waals (M−vdW, NbSe2/WxNb1−xSe2/WSe2) junctions realize atomically sharp interfaces, exhibiting long hot-carrier lifetimes of approximately 75,296 s (78 times longer than that of metal−semiconductor, Pd/WSe2 junctions). Such dramatic lifetime enhancement in M−vdWjunctioned devices is attributed to the synergistic effects arising from the significant reduction in the number of defects and the Schottky barrier lowering at the interface. Formation of a controllable mixed-composition alloyed layer on the 2D active channel would be a breakthrough approach to maximize the electrical reliability of 2D nanomaterial-based electronic applications. KEYWORDS: Junction interface, 2D WSe2 field-effect transistor, hot-carrier-induced degradation, interface trap density, Schottky barrier lowering nately, there is a flurry of work to reduce the contact resistance: phase engineering,13,14 chemical doping,15−17 Fermi-level depinning,18−20 and the use of 1D edge contacts.21,22 However, the aforementioned approaches lack fabrication-process compatibility and junction stability. Recently, our group proposed a novel device architecture introducing an alloyed transition WxNb1−xSe2 layer between the WSe2 semiconducting channel and the NbSe2 metallic electrode; this resulted in highperformance atomic-layered 2D FET devices with relatively lower contact resistances.23 It was believed that the synergistic combination of Schottky barrier lowering and enhanced tunneling efficiency, at the alloyed 2D metal−semiconductor heterojunction, contributed to improving the charge-transport behavior. Nevertheless, it is critical to elucidate the origin of the

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ecently, two-dimensional (2D) transition-metal dichalcogenides (TMDs) such as MoS2, WS2, and WSe2 with atomic-scale flatness have emerged as strong candidates for the future semiconducting materials owing to their high mobility, excellent scalability, and high degrees of mechanical flexibility.1−4 However, one of the most challenging impediments for the high-performance field-effect transistors (FETs) utilizing 2D nanomaterials is the high contact resistance at the interface between the 2D semiconductor and any bulk metal used as an electrical contact; this drastically diminishes the current drivability.5−7 The 2D metal−semiconductor interface, which is dissimilar to that of conventional 3D bulk material systems, involves new physics that is beyond the simple consideration of work function (e.g., metallization of TMDs and abnormal Fermi-level pinning).8−10 The electrical contacts to the 2D TMD semiconductors should be considered more carefully with respect to important physical parameters such as tunnel barriers, Schottky barriers, and orbital overlaps.8,11,12 Fortu© XXXX American Chemical Society

Received: July 13, 2016 Revised: August 17, 2016

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DOI: 10.1021/acs.nanolett.6b02893 Nano Lett. XXXX, XXX, XXX−XXX

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Figure 1. (a) Schematic of atomic structures with metal Pd−semiconducting WSe2 (MS) junction and mixed layer containing NbSe2/WxNb1−xSe2/ WSe2 van der Waals (M−vdW) junction. (b) Raman spectra recorded from an as-synthesized substantiate the existence of 2D materials including WSe2, WxNb1−xSe2, and NbSe2, which are used for the active channel, transition alloy layer, and metallic electrode, respectively. Cross-sectional HRTEM images obtained at interfaces of (c) MS junction (e) M−vdW junction. Atomic-resolution ADF STEM and EDS recorded from (d) MS junction (f) M−vdW junction.

To analyze the physical interfaces between the different metal contacts and the 2D WSe2 channel, we investigated the Pd/WSe2 (MS) junction and the NbSe2/WxNb1−xSe2/WSe2 (M−vdW) heterojunction in back-gate FET devices. The fabrication processes for the devices with each type of junction are shown in Figure S1 in the Supporting Information (SI). Atomic structures of the two junctions are illustrated in Figure 1a. As shown in Figure 1b, the Raman spectra clearly substantiate that the TMDs (WSe2, WxNb1−xSe2, and NbSe2) are successfully synthesized via the chemical vapor deposition (CVD) technique. The Raman spectra recorded from the surface of WSe2 and NbSe2 clearly feature the in-plane vibrational modes of W−Se and Nb−Se (1E2g: 250.3 and 243.2 cm−1) and the out-of-plane vibrational modes of the Se atoms (A1g: 258.5 and 230.6 cm−1 for WSe2 and NbSe2). In the case of the WxNb1−xSe2 transition alloy layer, however, the substitution of Nb atoms in W sites might induce lattice distortion in the crystal structure due to the difference between the bonding lengths of W−Se and Nb−Se,23 resulting in the band broadening of the Raman peak. Cross-sectional high-resolution transmission electron microscopy (HR-TEM) images were obtained (Figure 1c,e) to scrutinize the junction interfaces (MS and M−vdW). Atomicresolution annular dark-field (ADF) scanning TEM (STEM)/ energy-dispersive X-ray spectroscopy (EDS) analysis was also conducted (Figure 1d,f). As can be observed in Figure 1c, the interface (red dotted lines) of WSe2 and Pd is quite coarse. The absence of dangling bonds and the low chemical inertness of the WSe2 surface might hinder the formation of a conformal Pd film layer on the 2D layered film24,25 (Figure 1d). The

outstanding contact properties of the 2D metal−2D semiconductor Schottky junction systems because the metalinduced gap state (MIGS) or interface trap state could be a significant factor on charge transport in conventional 3D metal contact.12 Even though the theoretical calculations on such physical phenomena such as Fermi level pinning and interface trap have been reported, comprehensive experimental characterizations of the interface properties of 2D-based Schottky junction devices have never been explored. Herein, we thoroughly investigate the interface properties of the Schottky junction with a mixed transition layer containing van der Waals (M−vdW, NbSe2/WxNb1−xSe2/WSe2) and metal−semiconductor (MS, Pd/WSe2) junctions in back-gate FET structures. The M−vdW-junctioned devices show clean and unwrinkled interfaces, resulting in longer lifetimes and more superior electrical stability than the MS-junctioned devices utilizing hot-carrier stress methods. Such robustness to external electrical stress is possibly because of the physically solid interface of the M−vdW-junctioned device. Interface trap densities at each Schottky junction, extracted through the conductance method, were found to be approximately 1.32 × 1013 eV−1cm−2 for the MS junction and 5.02 × 1012 eV−1cm−2 for the M−vdW junction. The characterized energy-band profiles at the interfaces of the junctions unearthed the origin of the enhanced charge transport quantitatively. It also revealed that the M−vdW junction with a physically solid interface enhanced the electrical charge transport, while a large number of defects distributed on the MS junction interface acted as trap sites, deteriorating the FET device performance and reliability. B

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Figure 2. (a) Transfer characteristics (IDS−VGS) as a function of time for MS junction under hot-carrier stress conditions of VGS − VTH = −10 V and VDS = −20 V. The inset displays the log-scale transfer characteristics. (b) Changes in ON-current (ION) and the VTH shift for MS-junctioned device. (c) Transfer characteristics (IDS−VGS) as a function of time for M−vdW junction under hot-carrier stress conditions of VGS − VTH = −10 V and VDS = −20 V. The inset displays the log-scale transfer characteristics. (d) Changes in ON-current (ION) and VTH shift for the M−vdW-junctioned device.

Figure 3. (a) Threshold voltage shifts in the MS and M−vdW-junctioned devices as a function of time under stress conditions of VGS − VTH = −10 V and VDS = −20 V, respectively. (b) Hot-carrier lifetimes extracted from the various stress voltages of VStress = VDS = −10, −15, and −20 V. The dashed black line represents the 10 year lifetime criteria. (c) Conductance versus operating frequency for the MS-junctioned device. The inset shows the frequency dependence of capacitance for the M−vdW-junctioned device. (d) Capacitance density versus angular frequency for different junctions. The maximum peak position denotes the extracted interface trap density.

obtrusive air gaps between the different layers in the M−vdW junction, which indicates an excellent formation of a heterojunction. The composition and thickness of the transition alloy layer were W0.95Nb0.05Se2 and 3.5 nm (Figures S2 and S3 in SI), respectively. To evaluate the stability of the different contacts on the WSe2 semiconducting channel, the hot-carrier-induced degradation in FET devices was investigated using electrical stress

formation of an unstable junction between the Pd metal and the WSe2 layer would seriously inhibit vertical charge transport across the junctions in FET devices. On the other hand, as shown in Figure 1e, the interface of the M−vdW junction (red dotted line) is velvety and clean. W and Se elements primarily constitute the two-layered films of WxNb1−xSe2/WSe2, while Nb atoms slightly doped in the transition alloy layer of WxNb1−xSe2 (Figure 1f). Unlike the MS junction, there are few C

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Figure 4. (a) and (d) Extracted Schottky barrier heights with various gate voltages for MS junction and M−vdW junction, respectively. (b) and (e) 3D images of surface potentials from KPFM measurements. The insets show the statistical distributions of CPD differences from electrode to channel. The schematic energy band diagrams of (c) metal Pd−semiconductor WSe2 channel (f) NbSe2/WxNb1−xSe2/WSe2 van der Waals (M− vdW) junction with Schottky contact.

indicate that the large number of interface trap sites can capture the hot carriers generated at the interface of the Schottky junction, eventually resulting in increased junction degradation. Hot-carrier stress measurements under different stress conditions are also strongly consistent with this result (see Figure S6 in SI). Note that the hot-carrier test is conducted to analyze whether a specific device meets the operation lifetime necessary for practical device applications.26,27 Figure 3a,b shows the threshold voltage shifts with increasing stress durations and the hot-carrier lifetimes with increasing stress voltages for each device, respectively. In Figure 3a, the slope is a strong indicator to distinguish between the main degradation mechanisms and can be divided into three sections: the slope between 0.1 and 0.2 represents the gate oxide charge trapping/detrapping; the slope between 0.5 and 1 indicates the degradation of the drain− channel junction; and the intermediate slope between 0.2 and 0.5 represents the combination of gate oxide and drain− channel interface degradations.28 The slopes of the time exponents in WSe2-based junctions were estimated to be approximately 0.52 for the MS-junctioned device and 0.56 for the M−vdW-junctioned device, as shown in Figure 3a. These values of time exponents indicate that the generated hot carriers primarily deteriorate the drain−channel junction, rather than

tests at room temperature (see Figure S4 in SI for the principle behind the test method). Constant stress voltages (VStress = VGS − VTH = 1/2VDS) were applied to the gate and drain regions of the WSe 2-based transistors. Full IDS −V GS curves were consecutively measured to monitor the ION shifts and the VTH changes as a function of the stress duration. Figure 2a,c shows the IDS−VGS transfer characteristics as a function of time for the MS and the M−vdW-junctioned devices, respectively. For the MS-junctioned device (Figure 2a,b), the ON-current (ION) was gradually decreased, and the threshold voltage (VTH) was shifted in the negative direction during hot-carrier stress. The changes in both parameters (ION and VTH) are summarized in Figure 2b. Specifically, ION was reduced by approximately 16.6% (from 0.18 to 0.14 μA), and the total shift in VTH was approximately 8.0 V. On the contrary, in the case of the M− vdW-junctioned device (Figure 2c,d), ION was decreased by approximately 9.1% (from 1.80 to 1.65 μA), and VTH changed slightly (by approximately 1.4 V). In the case of vdWjunctioned devices (NbSe2/WSe2) without alloy layer, the ΔVTH was measured to be approximately 2.41 V, which is the value between MS and M-vdW-junctioned devices (Figure S5 and Table S1 in SI). Under same external electrical stress conditions, the M−vdW-junctioned device was much more robust than the MS-junctioned device. These observations D

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Schottky barrier can be described by the 2D thermionicemission equation as follows:23

the gate oxide. Figure 3b shows the hot-carrier lifetimes under different voltage stress conditions (VStress = VDS = −10, −15, and −20 V). The hot-carrier lifetime from the extrapolated line curves was estimated to be approximately 962 s for the MSjunctioned device and 75,296 s for the M−vdW-junctioned device. The expected hot carrier lifetime of the M−vdWjunctioned device is 78 times longer than that of the MSjunctioned device. These results indicate that the energetic hot hole carriers created at the drain side of Pd−WSe2 rapidly accelerate the junction damages, which are due to the relatively weak physical bonding of Pd atoms to the WSe2 surface.29 Thus, long-term stability of the M−vdW junction can be realized via the superior interfaces of the 2D heterostructures comprising NbSe2/WxNb1−xSe2/WSe2. To gain more insight into the 2D interface properties, the interface trap densities between the channel and the electrodes (at each junction) are quantitatively and comparatively investigated using the conductance method based on the equivalent parallel conductance model of the metal-oxidesemiconductor (MOS) structure.30 The test method is based on the principle of using a small alternating AC voltage, superimposed on the contact DC voltage, to modulate the interface states. The occupancies of the interface states change such that the interface states can be measured as a parallel conductance Gp as follows:

Gp ω

=

⎡ q ⎛ VDS ⎞⎤ * ST 3/2 exp⎢ − ⎜Φ − ⎟⎥ IDS = A 2D B n ⎠⎦ ⎣ KBT ⎝

where A*2D is the 2D equivalent Richardson constant, S is the contact area, T is the temperature, q is the electron charge, KB is the Boltzmann constant, ΦB is the Schottky barrier height, and n is the ideality factor. Using the 2D thermionic-emission model, the effective Schottky barrier heights for the MS and M−vdW-junctioned devices are plotted with various gate voltages from −60 to 10 V as shown in Figure 4a,d. Below the VFB criteria, the extracted Schottky barrier heights show a tendency to decrease linearly with increase in the absolute gate voltage; however, they are saturated in the large gate-voltage regime (>30 V). Thus, the true Schottky barrier height of each device can be determined at the VFB position (marked with black arrows) as shown in the insets of Figure 4a,d. The effective Schottky barrier heights for the MS and M−vdWjunctioned devices are calculated to be approximately 87.4 and 67.6 meV, respectively. It is clearly validated that the barrier height of the M−vdW-junctioned device is lower than that of the MS-junctioned device. To obtain a spatial image of the surface potential across the channel electrode of the WSe2 FET structure, KPFM mapping was conducted at room temperature (see Figure S9 in SI).33 Even though the true Schottky barrier heights with different junction properties were clearly extracted, the band offsets at the metal−semiconductor interface were still unknown. Figure 4b,e demonstrates the 3D images of the contact potential difference (CPD) in the MS and M−vdW-junctioned devices, respectively. The black dashed lines in Figure 4b,e indicate the CPD line profiles from the source to the drain across the WSe2 channel (length of 10 μm). The CPD value of the M−vdW junction is smaller than that of the MS junction because the band offset of the valence band between the WSe2 channel and the W1Nb1−xSe2 transition layer is relatively small. The statistical distributions of CPD for each device also show similar trends, as displayed in the insets of Figure 4b,e. The average CPD value of the MS-junctioned device was found to be approximately 57 mV, while that of the M−vdW-junctioned was approximately 37 mV. Thus, the insertion of an alloyed W1Nb1−xSe2 transition layer into the WSe2 channel reduced the band offset at the metal−semiconductor interface considerably. Even if tunneling efficiency originating from van der Waals coupling of each 2D layers might be low, the WxNb1−xSe2 alloy could function as a supporting layer for Fermi-level depinning as well as reduction of tunneling barrier.12 Based on the experimental observations (Schottky barrier extraction from temperature-variable current and band offset from KPFM study), the energy-band diagrams of each junction device are presented in Figure 4c,f. In the MS-junctioned device, a relatively large Schottky barrier height was observed because of the Fermi-level pinning induced by the large number of interface traps even though a Pd metal electrode with a large work function (approximately 5.1 eV) was used to match the Fermi levels between Pd and WSe2. In contrast, the alloyed WxNb1−xSe2 transition-layer contact reduced the Schottky barrier height because of the atomically clean interface with just a few dangling bonds. Additionally, the quantummechanical tunneling efficiency of the M−vdW junction was enhanced since the Nb-doped WSe2 transition layer consid-

qωτitDit 1 + (ωτit)2

(1)

where ω is the angular frequency (ω = 2πf), Gp is the parallel conductance, and Dit is the interface trap density. Finally, the interface trap density can be obtained from Dit =

2.5 q

(2)

Gp

( ). ω

Figure 3c shows the capacitance density as a function of the operating frequency, and the interface trap density of each junction device is calculated as shown in Figure 3d (see Figure S7 in SI for more details on the experimental methods used). Using the aforementioned eq 1, the interface trap densities extracted at the maximum peak position are found to be approximately 1.32 × 1013 for the MS-junctioned device and 5.02 × 1012 (eV−1 cm−2) for the M−vdW-junctioned device. A large number of dangling bonds at the Pd surface of the MS junction act as trap states to capture the mobile carriers from/ toward the WSe2 channel, while theoretically, fewer trap states are distributed at the M−vdW junction interface due to the absence of dangling bonds.31 Next, the temperature-variable IDS−VBG and the Kelvin probe force microscopy (KPFM) measurements were conducted to investigate the energy-band profiles of the WSe2-based FETs with different contact junctions. Figure 4a,d shows the effective Schottky barrier heights under different gate voltages in the MS and M−vdW-junctioned devices, respectively. In the Schottky barrier-FET (SB-FET) structure, there are two main charge transport mechanisms: (1) thermionic emission current and (2) thermally assisted tunneling.7,32 The thermionic emission current (with a strongly temperature-dependent drain current) is dominant below the flat-band (VFB) voltage region, while thermally assisted tunneling (with drain current exhibiting negligible temperature dependence) becomes dominant beyond the flat-band voltage region (see Figure S8 in SI). Thus, the true Schottky barrier height can be extracted at the flat-band voltage point where the built-in potential is canceled out by applying a gate voltage. The drain current through the E

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(7) Das, S.; Chen, H.-Y.; Penumatcha, A. V.; Appenzeller, J. Nano Lett. 2013, 13 (1), 100−105. (8) Kang, J.; Liu, W.; Sarkar, D.; Jena, D.; Banerjee, K. Phys. Rev. X 2014, 4 (3), 31005. (9) McDonnell, S.; Smyth, C. M.; Hinkle, C. L. ACS Appl. Mater. Interfaces 2016, 8 (12), 8289−8294. (10) McDonnell, S.; Smyth, C.; Hinkle, C. L.; Wallace, R. M. ACS Appl. Mater. Interfaces 2016, 8 (12), 8289−8294. (11) Guo, Y.; Liu, D.; Robertson, J. ACS Appl. Mater. Interfaces 2015, 7 (46), 25709−25715. (12) Liu, Y.; Stradins, P.; Wei, S.-H. Sci. Adv. 2016, 2 (4), e1600069. (13) Kappera, R.; Voiry, D.; Yalcin, S. E.; Branch, B.; Gupta, G.; Mohite, A. D.; Chhowalla, M. Nat. Mater. 2014, 13 (12), 1128−1134. (14) Cho, S.; Kim, S.; Kim, J. H.; Zhao, J.; Seok, J.; Keum, D. H.; Baik, J.; Choe, D.-H.; Chang, K. J.; Suenaga, K.; Kim, S. W.; Lee, Y. H.; Yang, H. Science 2015, 349 (6248), 625−628. (15) Yang, L.; Majumdar, K.; Liu, H.; Du, Y.; Wu, H.; Hatzistergos, M.; Hung, P. Y.; Tieckelmann, R.; Tsai, W.; Hobbs, C.; Ye, P. D. Nano Lett. 2014, 14 (11), 6275−6280. (16) Sim, D. M.; Kim, M.; Yim, S.; Choi, M.-J.; Choi, J.; Yoo, S.; Jung, Y. S. ACS Nano 2015, 9 (12), 12115−12123. (17) Khalil, H. M. W.; Khan, M. F.; Eom, J.; Noh, H. ACS Appl. Mater. Interfaces 2015, 7 (42), 23589−23596. (18) Kim, Y.; Park, W.; Yang, J. H.; Cho, C.; Lee, S. K.; Lee, B. H. Phys. Status Solidi RRL 2016, 10 (8), 634−638. (19) Park, W.; Kim, Y.; Jung, U.; Yang, J. H.; Cho, C.; Kim, Y. J.; Hasan, S. M. N.; Kim, H. G.; Lee, H. B. R.; Lee, B. H. Adv. Electron. Mater. 2016, 2, 1500278. (20) Lee, S.; Tang, A.; Aloni, S.; Philip Wong, H.-S. Nano Lett. 2016, 16 (1), 276−281. (21) Wang, L.; Meric, I.; Huang, P. Y.; Gao, Q.; Gao, Y.; Tran, H.; Taniguchi, T.; Watanabe, K.; Campos, L. M.; Muller, D. A.; Guo, J.; Kim, P.; Hone, J.; Shepard, K. L.; Dean, C. R. Science 2013, 342 (6158), 614−617. (22) Cui, X.; Lee, G.-H.; Kim, Y. D.; Arefe, G.; Huang, P. Y.; Lee, C.H.; Chenet, D. A.; Zhang, X.; Wang, L.; Ye, F.; Pizzocchero, F.; Jessen, B. S.; Watanabe, K.; Taniguchi, T.; Muller, D. A.; Low, T.; Kim, P.; Hone, J. Nat. Nanotechnol. 2015, 10 (6), 534−540. (23) Kim, A. R.; Kim, Y.; Nam, J.; Chung, H.-S.; Kim, D. J.; Kwon, J.D.; Park, S. W.; Park, J.; Choi, S. Y.; Lee, B. H.; Park, J. H.; Lee, K. H.; Kim, D.-H.; Choi, S. M.; Ajayan, P. M.; Hahm, M. G.; Cho, B. Nano Lett. 2016, 16 (3), 1890−1895. (24) Cheng, L.; Qin, X.; Lucero, A. T.; Azcatl, A.; Huang, J.; Wallace, R. M.; Cho, K.; Kim, J. ACS Appl. Mater. Interfaces 2014, 6 (15), 11834−11838. (25) Son, S.; Yu, S.; Choi, M.; Kim, D.; Choi, C. Appl. Phys. Lett. 2015, 106 (2), 021601. (26) Cho, M.; Hellings, G.; Veloso, A.; Simoen, E.; Roussel, P.; Kaczer, B.; Arimura, H.; Fang, W.; Franco, J.; Matagne, P.; Collaert, N.; Linten, D.; Thean, A. Proceedings of the 2015 IEEE International Electron Devices Meeting (IEDM), Washington, D.C., December 7−9, 2015; IEEE: New York, 2015; pp 14.5.1−14.5.4. (27) Chen, C. C.; Cha, S.; Liu, T.; Milor, L. Proceedings of the IEEE International Reliability Physics Symposium, June 1−5, Waikoloa, Hawaii, IEEE: New York, 2014; pp CA.8.1−CA.8.9. (28) Cho, M.; Arimura, H.; Lee, J. W.; Kaczer, B.; Veloso, A.; Boccardi, G.; Ragnarsson, L. A.; Kauerauf, T.; Horiguchi, N.; Groeseneken, G. IEEE Trans. Device Mater. Reliab. 2014, 14 (1), 408−412. (29) Kim, Y.; Kang, S. C.; Lee, S. K.; Jung, U.; Kim, S. M.; Lee, B. H. IEEE Electron Device Lett. 2016, 37 (4), 366−368. (30) Kanayama, K.; Nagashio, K. Sci. Rep. 2015, 5, 15789. (31) Chuang, H.-J.; Chamlagain, B.; Koehler, M.; Perera, M. M.; Yan, J.; Mandrus, D.; Tománek, D.; Zhou, Z. Nano Lett. 2016, 16 (3), 1896−1902. (32) Appenzeller, J.; Radosavljević, M.; Knoch, J.; Avouris, P. Phys. Rev. Lett. 2004, 92 (4), 48301. (33) Melitz, W.; Shen, J.; Kummel, A. C.; Lee, S. Surf. Sci. Rep. 2011, 66 (1), 1−27.

erably decreased the tunneling width. Thus, the introduction of an M−vdW alloyed interface between the 2D heterolayers might be an innovative strategy for reducing the Schottky barrier height and increasing the charge injection/tunneling efficiency across the 2D metal−semiconductor heterojunction devices. In summary, we systemically investigated the origin of the superior device reliability of alloyed 2D metal−semiconductor heterojunctions. The M−vdW-junctioned device with a mixed transition layer of WxNb1−xSe2 showed a longer hot-carrier lifetime than the MS-junctioned device (Pd/WSe2), utilizing hot-carrier stress methodology. The enhanced junction reliability of WSe2-based FETs was preferentially attributed to the combined effect of interface trap reduction and Schottky barrier lowering originating from the atomically sharp interfaces and a few dangling bonds. The energy-band diagrams proposed from KPFM and the temperature-variable electrical measurements validated the improvements in charge injection and tunneling efficiency of the M−vdW junction. The electrical reliability characterization proposed here also can be applied to other 2D assembly architectures for rational 2D-based device designs.

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ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.6b02893. Additional figures (PDF)

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AUTHOR INFORMATION

Corresponding Authors

*E-mail: [email protected]. *E-mail: [email protected]. Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS This study was supported by the Fundamental Research Program (PNK4580 and 4890) of the Korean Institute of Materials Science (KIMS). M.G.H. and B.C. are grateful for the support of the Basic Science Research Program of the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT, and Future Planning (NRF2014R1A1A1006214 and NRF-2014R1A1A1036139).

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REFERENCES

(1) Radisavljevic, B.; Radenovic, A.; Brivio, J.; Giacometti, V.; Kis, A. Nat. Nanotechnol. 2011, 6 (3), 147−150. (2) Chen, M. C.; Li, K. S.; Li, L. J.; Lu, A. Y.; Li, M. Y.; Chang, Y. H.; Lin, C. H.; Chen, Y. J.; Hou, Y. F.; Chen, C. C.; Wu, B. W.; Wu, C. S.; Yang, I.; Lee, Y. J.; Shieh, J. M.; Yeh, W. K.; Shih, J. H.; Su, P. C.; Sachid, A. B.; Wang, T.; Yang, F. L.; Hu, C. Proceedings of the 2015 IEEE International Electron Devices Meeting (IEDM), Washington, D.C., December 7−9, 2015, IEEE: New York, 2015; pp 32.2.1−32.2.4. (3) Bertolazzi, S.; Brivio, J.; Kis, A. ACS Nano 2011, 5 (12), 9703− 9709. (4) Akinwande, D.; Petrone, N.; Hone, J. Nat. Commun. 2014, 5, 5678. (5) Allain, A.; Kang, J.; Banerjee, K.; Kis, A. Nat. Mater. 2015, 14 (12), 1195−1205. (6) Xu, Y.; Cheng, C.; Du, S.; Yang, J.; Yu, B.; Luo, J.; Yin, W.; Li, E.; Dong, S.; Ye, P.; Duan, X. ACS Nano 2016, 10 (5), 4895−4919. F

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