Ambipolar Quantum-Dot-Based Low-Voltage ... - ACS Publications

Subscriber access provided by UNIVERSITY OF THE SUNSHINE COAST

Article

Ambipolar quantum dot-based low-voltage nonvolatile memory with double-floating-gates Heng Zhang, Yating Zhang, Yu Yu, Xiaoxian Song, Haiting Zhang, Mingxuan Cao, Yongli Che, Haitao Dai, Junbo Yang, and Jianquan Yao ACS Photonics, Just Accepted Manuscript • DOI: 10.1021/acsphotonics.7b00416 • Publication Date (Web): 26 Jul 2017 Downloaded from http://pubs.acs.org on July 29, 2017

Just Accepted “Just Accepted” manuscripts have been peer-reviewed and accepted for publication. They are posted online prior to technical editing, formatting for publication and author proofing. The American Chemical Society provides “Just Accepted” as a free service to the research community to expedite the dissemination of scientific material as soon as possible after acceptance. “Just Accepted” manuscripts appear in full in PDF format accompanied by an HTML abstract. “Just Accepted” manuscripts have been fully peer reviewed, but should not be considered the official version of record. They are accessible to all readers and citable by the Digital Object Identifier (DOI®). “Just Accepted” is an optional service offered to authors. Therefore, the “Just Accepted” Web site may not include all articles that will be published in the journal. After a manuscript is technically edited and formatted, it will be removed from the “Just Accepted” Web site and published as an ASAP article. Note that technical editing may introduce minor changes to the manuscript text and/or graphics which could affect content, and all legal disclaimers and ethical guidelines that apply to the journal pertain. ACS cannot be held responsible for errors or consequences arising from the use of information contained in these “Just Accepted” manuscripts.

ACS Photonics is published by the American Chemical Society. 1155 Sixteenth Street N.W., Washington, DC 20036 Published by American Chemical Society. Copyright © American Chemical Society. However, no copyright claim is made to original U.S. Government works, or works produced by employees of any Commonwealth realm Crown government in the course of their duties.

Page 1 of 21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Photonics

Ambipolar quantum dot-based low-voltage nonvolatile memory with double-floating-gates †

Heng Zhang, Yating Zhang, Yongli Che, †

†

†，*

Yu Yu,

†

†

†

Xiaoxian Song, Haiting Zhang, Mingxuan Cao,

Haitao Dai, ‡ Junbo Yang, § Jianquan Yao

†

†

Key Laboratory of Opto-Electronics Information Technology (Tianjin University), Ministry of

Education, School of Precision Instruments and Opto-Electronics Engineering, Tianjin University, Tianjin 300072, China; ‡

Tianjin Key Laboratory of Low Dimensional Materials Physics and Preparing Technology,

School of Science, Tianjin University，Tianjin, 300072，China; §

Center of Material Science, National University of Defense Technology，Changsha，410073,

China. KEYWORDS: quantum dot; double floating gate; graphene oxide; memory

ABSTRACT: Considerable research efforts have been devoted to promoting the memory performance, especially the memory window and retention time. In this work, we develop an innovative field effect transistor (FET) memory with graphene oxide (GO)/gold nanoparticles (Au NPs) as double-floating-gates (DFG) and PbS quantum dots (QDs) as semiconductor layer. QDs can provide both electrons and holes in the channel which offers a chance for the floating

ACS Paragon Plus Environment

1

ACS Photonics

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 2 of 21

gates to trap both of them to achieve bidirectional threshold voltage shifts after programming and erasing operations. Due to the DFG structure with covering GO sheets on the Au NPs monolayer, the enhanced memory window (~2.72 V at programming /erasing voltage of ±10 V) can be attributed to more charge carriers being trapped into the floating gates. More importantly, because of the different energy level between GO and Au NPs, the DFG construction brings about an energy barrier which prevents the trapped charges leaking back to the channel so that the retention capability is significantly improved. The outstanding memory performance will give the QDs-based DFG memory a great potential to have its own place in the flash memory market.

Field-effect-transistor (FET) memories with a floating-gate architecture have attracted tremendous consideration among the many possible memory configurations for the ultimate goal of flash memories due to its single-transistor realization, nondestructive read-out, and compatibility with complementary metal oxide-semiconductor (CMOS) devices.1-4 Instead of the traditional continuous floating gates, discrete nanoparticles embedded into the gate dielectric have been brought up to avoid severe charge leakage resulting from the local defects in tunneling dielectric, and then to implement the down scale of the memory device.5-10 However, poor retention capability has always been the largest drawback for the NPs floating-gate memory because of the thin tunneling dielectric. Although increasing the thickness of the tunneling dielectric have positive effect on retention time, the soaring power consumption and dramatic drop in the program/erase (P/E) speed is utterly unacceptable.11 To solve this problem, doublefloating-gates memory (DFGM) turns out to be a potential alternative approach to achieve better retention properties as well as storage performance.12-15 By combining two different layers of NPs as double floating gates, the potential barrier arising between the upper and lower floating


2

Page 3 of 21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Photonics

gates will keep the trapped charge carriers from leaking back to the channel so that the retention capability is improved.12,16-20 But most DFGMs fabricated by deposition or synthesis could not necessarily form NP pairs in the vertical direction, namely the upper and lower floating gates fail to align to produce the energy barrier.20 In consequence, the original intention of DFG structure cannot be achieved to improve retention capability. What’s more, the poor interface between NPs and tunneling dielectric critically affected the memory performance including the electrical behaviors. But Han et al. constructed a DFGM which successfully settled the interface issue by using graphene as the upper floating gate covering Au NPs.14 As the star member in twodimensional material, graphene has a flattened surface and a large area to improve the interface quality. Yet the lack of trapping states makes graphene inappropriate for floating gate to trap enough charges. And another shortcoming is that the Fermi level of graphene is so close to the metallic work function that makes graphene not the best candidate to improve the retention ability. Here, we present a new architecture for low-voltage flash memory device based on solutionprocessed layer-by-layer (LBL) assembled GO sheets / gold nanoparticles as upper and lower floating gates and PbS QDs as semiconductor layer. As an alternative to graphene, Graphene oxide, a chemically oxidized sheet of graphene, shows advantages as floating gate material due to its plenty of charge trapping sites like oxygen groups and defects.21-23 And GO has a paperlike surface that could improve the interfacial contact between floating gates and tunneling layer. Another reason why GO is much better for upper floating gate rather than graphene is that GO is nearly an insulating material which could effectively stop the injected charges in the deep states of GO and the lower floating gate from leaking back to the channel. So it is very possible to greatly increase the charge-retention capability. PbS QDs as ambipolar active material is utilized


3

ACS Photonics

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 4 of 21

to provide both electrons and holes in the channel, thus leading to bidirectional shift of threshold voltage (Vth) to expand memory window. In fact, the normally opening state of ambipolar FETs may offer enough charges in the channel without additional gate voltage, and the injected charges can overwrite the opposite trapped charges, which gives an opportunity to lower both operating and programming voltages.24 In comparison with constructive effect of DFGM, single floating gate memory (SFGM) with Au NPs as storage layer was carried out to confirm the function of double floating gates. The use of double floating gates and PbS QDs in the memory device successfully lowered the programming and operating voltages. Meanwhile, the DFGM exhibits good memory characteristics, especially in wide memory window and promoted retention capability. Due to the good memory performance and low power consumption, QDsbased DFGM has a great potential to achieve a wide range of application.

Figure 1. Schematic diagram depicting the basic fabrication process of GO/Au NPs doublefloating-gates memory device. Bottom-gate top-contact double-floating-gate memory based on ambipolar semiconductor PbS QDs was fabricated by LBL assembling two different storage layer of GO and Au NPs. The


4

Page 5 of 21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Photonics

fabrication process is described detailedly in Figure 1. A heavily doped n-type silicon wafer (n+ Si) was used as the gate electrode, on which a 300 nm-thick SiO2 was thermally grown as control dielectric. Then the substrate was cleaned by ultrasonic treatment in propanol, acetone and deionized water for 10 min in sequence. After that, it was immersed into a solution of 3aminopropyltrimethoxysilane (APTMS) (0.1 ml of APTMS in 1 ml methanol) to form a positively charged self-assembled monolayer and then was rinsed with methanol. The substrate was subsequently transferred into the negatively charged Au NPs solution by citrate reduced method to fabricate an Au NPs monolayer as the lower floating gate. And then a well dispersed solution of GO in deionized water was spin-coated on the surface of Au NPs as the upper floating gate. After the construction of double floating gates, 15 nm of PMMA (3 mg/ml in ethyl acetate) tunneling organic dielectric layer was spin-coated at 6000 rpm for 60 s and then annealing at 60 ℃ for 2 h . The dielectric layer was confirmed to be uniform and smooth by step profiler. Source and drain electrode were deposited by thermally evaporation through a shadow mask, by which the channel length (L) and width (W) were defined as 0.1 mm and 2.5 mm, respectively. Finally, three layers of PbS QDs synthesized by wet chemical method were deposited as the semiconductor layer from toluene solution. The details of the preparation and deposition of PbS QDs are referred in Supporting Information (SI).


5

ACS Photonics

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 6 of 21

Figure 2. (a) The absorbance of PbS QDs (inset: the TEM of PbS QDs). (b) Tapping-mode AFM image of GO on the Si substrate (inset: height profile of GO). (c) SEM image of self-assembled Au NPs monolayer. (d) Tapping-mode AFM image of GO on the Au NP monolayer. Figure 2a shows the absorbance of PbS QDs whose absorption peak is located in 1310 nm. As we can see from the inset of Figure 2a, the transmission electron microscope (TEM) image of PbS QDs displays uniform size distribution of 5.2 nm. Figure 2b exhibits the atomic force micrograph (AFM) of monolayer GO. We can observe that the effective thickness of GO is about 1 nm which is consistent with reported GO thickness previously.25,26 A scanning electron microscopy (SEM) image of the Au NPs is shown in Figure 2c. The adsorbed Au NPs by dipping


6

Page 7 of 21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Photonics

the decorated substrate into an Au colloidal solution for 12 h is found to be uniform in size and no obvious aggregation due to the electrostatic repulsion between the neighboring Au NPs. Figure 2d depicts the AFM image of large-area GO covering Au NPs monolayer. To avoid overlapping of multilayer GO, only one drop of GO dispersion solution with the concentration of 0.4 mg/ml is spin-coated to obtain a well dispersed GO surface. In the electrical measurements, a bias voltage (VDS) was applied by using a KeithleyTM 2400 to the drain and source (i.e., ground connection) electrodes; the channel current (IDS) which flows from the drain to the source electrode was also measured by the KeithleyTM 2400. An HP6030A was used to supply gate voltage (VGS) electrically connected the gate electrode and the ground. The measurement was performed at room temperature in ambient environment.


7

ACS Photonics

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 8 of 21

Figure 3. The output characteristics of the SFGM (a) and DFGM (b). The transfer characteristics of the SFGM (c) and DFGM (d). In the electrical measurement, Figure 3a and 3b present the n-type output characteristics (IDS-VDS) of SFGM and DFGM, from which the rapid increase of IDS with VDS at a fixed VGS is observed. Even at a low gate voltage, a huge increase of IDS indicates that both holes and electrons can transport in the channel.24 Comparing to the SFGM, the IDS of DFGM is a little lower at the same VDS and VGS which could be inferred that the introduction of GO sheets trapping more charge carriers in the double floating gates shields the control effect of gate voltage.27 Figure 3c and 3d shows the transfer characteristics of SFGM and DFGM, respectively. Different from the unipolar FET memory, the threshold voltage Vth of bipolar FET device is defined as the gate voltage at which the IDS changes from electrons inversed to holes transport. In our measurement, the Vth (initial) of the SFGM and DFGM devices are 0.37 V and 1.27 V. The much more positive value of Vth for DFGM implies an increase in the turn-on voltage which can be ascribed to the addition of GO sheets. The shielding effect of more trapped charges and the build-in electrical field formed by the energy level difference between GO and Au NPs offsets part of the implied gate voltage. So, the threshold voltage must be increased to change the type of channel carriers. Meanwhile, the carrier mobility in the linear regime can be extracted from the equation of

=

,

(1)

where L and W are the channel length and width, Cox is the gate capacitance per area. In our electrical measurement, the DFGM shows a little higher electron mobility (µ = 0.0280 cm2V-1s-1) than that of SFGM (µ = 0.0268 cm2V-1s-1), that is, the charge carriers move a little faster in the


8

Page 9 of 21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Photonics

channel of the DFGM. Actually, the Au NPs will causes the interruption of the tunneling dielectric layer, especially when the layer gets further thinner till the thickness could be compared with the diameter of Au NPs. At this point, the paper-like GO film will act as a buffer layer to decrease the surface roughness of the pristine Au NPs charge trapping layer as well as the semiconductor layer, consequently enhancing the electrical performance of the DFGM.14

Figure 4. Transfer characteristics of the SFGM (a) and the DFGM (b) after P/E voltage of ±10 V at VDS of 2 V. (c) Memory hysteresis behavior of the DFGM at the VDS of 1.6 V, 2 V, 2.6 V. (solid line: programing state; dashed line: erasing state) (d) Memory hysteresis behavior of the DFGM as a function of the bias.


9

ACS Photonics

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 10 of 21

The most essential requirement for a flash memory is the memory window (∆Vth) which is defined as the shift of threshold voltage when a device is undergone programming and erasing processes. Figure 4a and 4b show the initial, programming and erasing transfer curves of SFGM and DFGM by recording the IDS at the fixed bias voltage of 2 V before and after applying a ±10 V at the gate for 1 s. The positive and negative Vth shifts of transfer curves versus initial state for both memory devices demonstrate that not only electrons but also holes transport in the channel and both can be trapped into the charge storage layer. To be clear, positive Vth shift means that the Vth of programed state changes with respect to that of initial state, while the negative Vth shift means that the Vth of erased state changes with respect to that of initial state. From the transfer characteristics in Figure 4, the Vth of programming and erasing state of SFGM are 1.14 V and 0.04 V, respectively, while these values of DFGM are 2.40 V and 0.38 V, respectively. The great enhancement of the memory window for DFGM is a convincing proof that GO as the upper floating gate can be a complementary trapping layer to trap more charge carriers. Besides, both increasing positive and negative Vth shifts (1.13 V and 0.89 V) comparing to the SFGM (0.77 V and 0.33 V) suggest that GO can trap electrons and holes at the same time. But only negative Vth shift is prominent, demonstrating that holes are much easier to be trapped into GO. It could be speculated that there are more occupied states in the deep trapping states of GO which makes it more effective to trap holes rather than electrons.13 As our knowledge, GO has already been utilized as charge trapping material for a long time due to its lots of trapping sites such as epoxy and hydroxyl groups and many defective edge structure that could bear carbonyl and ketone groups.3,28,29 The greater transfer curve shift could be achieved at a low programming (10 V) and operating voltage (5 V) owing to the PbS QDs that supplies more carriers in the channel and double floating gates that have more trapping sites to capture more charges.


10

Page 11 of 21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Photonics

The effect of bias voltage on the memory window for DFGM is presented in Figure 4c. Three typical hysteresis transfer characteristics are recorded at different VDS of 1.6 V, 2 V, 2.6 V under fixed P/E voltages of ±10 V. As bias voltage increases, the programed Vth increases from 2.07 V to 2.82 V, erased Vth changes from 0.28 V to 0.68 V. So the memory window expands generally from 1.79 V to 2.14 V. It indicates that the memory size of DFGM depends strongly on the magnitude of bias voltage at certain P/E operations. To deeply confirm the influence of VDS to ∆Vth, more bias voltages are taken from 0 V to 4 V in Figure 4d, accordingly the ∆Vth raises from 0 V to 2.72 V. The charge trapping density is also calculated to confirm the memory effect from the equation of

∆ =

∆

(2)

where is the specific capacitance of the SiO2 dielectric, is the element charge, and ΔVth is the memory window. The amount of charges is 1.95×1011 cm-2 when applying the VP/E of 10 V at VDS = 4 V. The enlarged memory window ensures that more carriers in the channel could be trapped in the floating gates as the bias voltage increases. PbS QDs happens to be the ambipolar semiconductor that could be separated into electrons and holes in the electric field which offers more charges at the same gate and drain voltages in contrast with conventional unipolar active materials.30


11

ACS Photonics

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 12 of 21

Figure 5. Data retention characteristics of SFGM (a) and DFGM (b) as function of the retention time. Energy band diagram in zero-gate-voltage configuration of SFGM (c) and DFGM (d). Electrons are represented by the solid black sphere. The solid arrows represent the flow of charge carriers. (LUMO: lowest unoccupied molecular orbit, EF: fermi energy level, VL: vacuum level) Another important figure of merit for a flash memory is the data retention capability that is becoming the main technical factor of impeding the commercial application. Retention time refers to the potential lifetime of nonvolatile storage. In order to trap more carriers and reduce the programming voltage, the tunneling layer has to be thinner and thinner, which undoubtedly results in the degradation of charge retention capability. Figure 5a and 5c shows the retention


12

Page 13 of 21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Photonics

characteristics of SFGM and DFGM measured by applying a gate voltage of ±10 V for 1 s at the first place and then recording the ∆Vth change every a certain period. From Figure 5a, the programed and erased states of SFGM all degraded badly. Up to 105 s, SFGM lost almost half of trapped charges. Under a normal retention state (VGS = 0 V), direct tunneling is the most likely charge loss mechanism since the existence of PMMA and low electric field across the tunneling layer. After repeated charge tunneling forth and back, PMMA can be damaged because of nanoscale thickness and uneven interface caused by Au NPs. So, a serious charge loss occurred when the injected charges is leaking back through PMMA in Figure 5b. Though there is a little losses during 100 s, DFGM shows a better retention capability as a whole, which confirms that GO plays a crucial role in the improvement of retention ability as the upper floating gate. The 100 s losses are attributed to the leakage of charges trapped in the trapping sites close to the tunneling dielectric.4 The charge process simulation of double-floating-gates memory reported by Yu et al. gives a hint that charge carriers may be trapped into the lower floating gate first that is Au NPs in this condition right through the upper floating gate of GO.31 GO works as the supplementary trapping sites when Au NPs have enough charges trapped. In the double floating gates structure memory in Figure 5d, GO can be considered as insulting analog which has its lowest unoccupied molecular orbit (LUMO) near ~3.6 eV and highest occupied molecular orbit (HOMO) as ~5.6 eV while the work function of Au NPs is around 5.1 eV. So the huge energy barrier height ∆E, which refers to energy difference between LUMO of GO and the Fermi energy of Au NPs, needs to be overcome for the injected charges in the Au NPs to tunnel back to the channel. But in the SFGM in Figure 5b, the energy difference between the Fermi energy of Au NPs and LUMO of PbS QDs (≈ 4.31 eV) is much smaller for the stored charges to overcome. Therefore, the retention property of floating gate memory is significantly improved by


13

ACS Photonics

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 14 of 21

inserting GO as upper floating gate which gives the possibility to further reduce the thickness of tunneling dielectric layer to achieve a greater memory window without sacrificing retention ability.

Figure 6. (a) Flat band diagram of GO/Au NPs double-floating-gates memory. Schematic energy band diagram and charge flow of GO/Au NPs double-floating-gates memory under programming (b) and erasing (c) operations. Figure 6 summarizes schematically the mechanism of programming and erasing operations for the QDs-based double-floating-gates memory. In the ambipolar trapping system, both kinds of charge carriers could be trapped to achieve better memory properties. Figure 6a presents the relative flat band diagram of the DFGM without any electrical contact. When a large positive


14

Page 15 of 21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Photonics

VGS is applied for programming in Figure 6b, the electrons apart from electron-hole pairs can be injected into floating gates from the LUMO of PbS QDs through the tunneling layer of PMMA. Extrapolating from the simulation reported before and our experimental results, it is very possible that the Au NPs would be the first choice for storing the tunneling electrons, which could also be understood from the relative energy level. A build-in electric field generated by the trapped electrons leads to a positive transfer curve shift. When the VGS is large enough, many injected electrons are trapped into the GO in addition to the Au NPs so a large memory window can be achieved. After the VGS is removed, the electrons can be confined stably to the potential well created not only by tunneling dielectric layer of PMMA but also by the potential barrier between GO and Au NPs. As a result, the retention characteristic is improved. In Figure 6c, a large negative VGS is applied for erasing process, a part of trapped electrons can migrate out from floating gates back to the channel. While the dominant process during erasing part is that holes transferred from the HOMO of PbS QDs are injected into the floating gates to compensate with electrons and then redundant holes transform the trapping states from electron trapping to hole trapping. Thus, the transfer curve can move further to the left than the initial curve. Therefore, the threshold voltage can be shifted on both sides by programming and erasing gate pulse. This suggests that a larger memory window can be realized by storing electrons and holes. To sum up, we present a PbS QDs-based double-floating-gates memory device by using the GO and Au NPs as upper and lower floating gates. Instead of only one kind of charge carriers, PbS QDs provide both electrons and holes in the channel that could be injected into the floating gates according to the gate voltage. So the QDs-based memory could realize the comparable memory window at much lower operating voltage. In addition, the dependence of memory window on the drain voltage is observed. The introduction of GO covering the Au NPs arrays


15

ACS Photonics

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 16 of 21

brings extra trapping sites to enhance the memory window as well. More importantly, the energy barrier between GO and Au NPs prevents the trapped charges from leaking back to the channel, which significantly improves the retention capability. The successful solution to enhance memory window and improve retention time gives a chance that the tunneling layer could be much thinner, so the programming voltage can be further lower. The nonvolatile memory device is constructed with low-temperature all solution processed method, including the semiconductor layer, tunneling dielectric, Au NPs and GO. Consequently, there is a great potential for the QDsbased double-floating-gates memory device to achieve a wide application in the field of commercial flash memory. ASSOCIATED CONTENT Supporting Information. The synthesis of PbS QDs. AUTHOR INFORMATION Corresponding Author *E-mail:[email protected] Notes The authors declare no competing financial interest. ACKNOWLEDGMENT This work was supported by the National Natural Science Foundation of China (Nos. 61675147 and 61605141). REFERENCES (1) Gong Gu, M. G. K., James E. Doty, and Arthur H. Firester, Electron traps and hysteresis in


16

Page 17 of 21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Photonics

pentacene-based organic thin-film transistors. Appl Phys Lett 2005, 87, 164. (2) Zhengchun Liu, F., Xue,Yi, Su Lvov, Y. M. Varahramyan, K., Memory effect of a polymer thin-film transistor with self-assembled gold nanoparticles in the gate dielectric. IEEE Transactions On Nanotechnology 2006, 5, 379-384. (3) Shuai Wang, J. P., Daniel S. H. Chan, Byung Jin Cho, and Kian Ping Loh, Wide memory window in graphene oxide charge storage nodes. Appl Phys Lett 2010, 96, 143109-143109-3. (4) Augustin J. Hong, E. B. S., Hyung Suk Yu, Matthew J. Allen, Jiyoung Kim, Jesse D. Fowler Jonathan K. Wassei, Youngju Park, Yong Wang, Jin Zou, Richard B. Kaner, Bruce H. Weiller, and Kang L. Wang, Graphene Flash Memory. Acs Nano 2011, 5, 7812-7. (5) S. M. Wang, C. W. L., and P. K. L. Chan, Nonvolatile organic transistor-memory devices using various thicknesses of silver nanoparticle layers. Appl Phys Lett 2010, 97, 99. (6) W. L. Leong, P. S. L., and S. G. Mhaisalkar, Charging phenomena in pentacene-gold nanoparticle memory device. Appl Phys Lett 2007, 90, 2997. (7) Christophe Novembre, D. G., Kamal Lmimouni, Christian Gamrat, and Dominique Vuillaume, Gold nanoparticle-pentacene memory transistors. Appl Phys Lett 2008, 92, 94. (8) Mohammed F. Mabrook, C. P., Dan Kolb, Dagou A. Zeze, Michael C. Petty, Memory effects in hybrid silicon-metallic nanoparticle-organic thin film structures. Organic Electronics 2008, 9, 816-820. (9) By Kang-Jun Baeg, Y.-Y. N., Henning Sirringhaus, and Dong-Yu Kim, Controllable Shifts in Threshold Voltage of Top-Gate Polymer Field-Effect Transistors for Applications in Organic Nano Floating Gate Memory. Adv Funct Mater 2010, 20, 224-230. (10) Su-Ting Han , Y. Z., Zong-Xiang Xu , Long-Biao Huang , Xiong-Bo Yang , and V. A. L. Roy Microcontact printing of ultrahigh density gold nanoparticle monolayer for flexible flash memories. Adv Mater 2012, 24, 3556-61. (11) J.S.Lee, J. C., C Lee, l Kim, J Park , Y.M. Kim, H Shin, J Lee, F Caruso, Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties. Nat Nanotechnol 2007, 2, 790-5. (12) Muraoka, T. T. a. K., Numerical approach for retention characteristics of double floatinggate memories. Appl Phys Lett 2010, 49, 345-370. (13) Xu Gao, X.-J. S., Chang-Hai Liu, Qi-Jun Sun, Jie Liu, and Sui-Dong Wang, Organic fieldeffect transistor nonvolatile memories based on hybrid nano-floating-gate. Appl Phys Lett 2013,


17

ACS Photonics

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 18 of 21

102, 023303. (14) Su-Ting Han , Y. Z., Chundong Wang , Lifang He , Wenjun Zhang , and V. A. L. Roy Layer-by-layer-assembled reduced graphene oxide/gold nanoparticle hybrid double-floating-gate structure for low-voltage flexible flash memory. Adv Mater 2013, 25, 872-877. (15) Hsuan-Chun Chang , C. L., Cheng-Liang Liu , and Wen-Chang Chen, Single-crystal C60 needle/CuPc nanoparticle double floating-gate for low-voltage organic transistors based nonvolatile memory devices. Adv Mater 2015, 27, 27–33. (16) Han, K. I. P., Yong Min Kim, Sung Choi, Suk-Ho Kim, Kyung Joong Park, Il Han Park, Byung-Gook, Enhancement of Memory Performance Using Doubly Stacked Si-Nanocrystal Floating Gates Prepared by Ion Beam Sputtering in UHV. Ieee T Electron Dev 2007, 54, 359362. (17) Dong Uk Lee, M. S. L., Jae-Hoon Kim, Eun Kyu Kim, Hyun-Mo Koo, Won-Ju Cho, and Won Mok Kim, Floating gated silicon-on-insulator nonvolatile memory devices with Au nanoparticles embedded in SiO 1.3 N insulators by digital sputtering method. Appl Phys Lett 2007, 90, 093514. (18) Seong-Wan Ryu, Y.-K. C., Chan Bin Mo, Soon Hyung Hong, Pan Kwi Park, and Sang-Won Kang, A thickness modulation effect of HfO2 interfacial layer between double-stacked Ag nanocrystals for nonvolatile memory device applications. J Appl Phys 2007, 101, 026109. (19) Theodoropoulou , A. G. N., Multilevel charge storage in Si nanocrystals arranged in double-dot-layers within SiO2. Microelectronic Engineering 2008, 85, 2362-2365. (20) Xiaohui Tang, C. K., Aurélien Lecavelier des Etangs-Levallois,Zhenkun Chen,Emmanuel Dubois,Erich Kasper,Alim Karmous,Nicolas Reckinger,Denis Flandre,Laurent A. Francis,JeanPierre Colinge,Jean-Pierre Raskin, Energy-band engineering for improved charge retention in fully self-aligned double floating-gate single-electron memories. Nano Lett 2011, 11, 4520-4526. (21) I.Karteri, K., Ahmed A. Al-Ghamdi , F. Yakuphanoglu, The electrical characteristics of thin film transistors with graphene oxide and organic insulators. Synthetic Metals 2014, 318,241-245. (22) Homod S. Alaabdlqader, A. S., Paul Sayers, Mohammed F. Mabrook, Graphene oxidebased non-volatile organic field effect memory transistors. IET Circuits, Devices & Systems 2014, 9, 67-71. (23) Tae-Wook Kima, N. C., Yan Gaob, Sukang Bae , Sanghyun Lee , Hong Ma, Hongzheng Chen, Alex K.-Y. Jen Low operational voltage and high performance organic field effect memory


18

Page 19 of 21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Photonics

transistor with solution processed graphene oxide charge storage media. Organic Electronics 2014, 15, 2775-2782. (24) Yunlong Guo, J. Z., Gui Yu, Jian Zheng, Lei Zhang, Yan Zhao, Yugeng Wen, Yunqi Liu Lowering programmed voltage of organic memory transistors based on polymer gate electrets through heterojunction fabrication. Organic Electronics 2012, 13, 1969-1974. (25) Sasha Stankovich , D. A. D., Richard D. Piner , Kevin A. Kohlhaas , Alfred Kleinhammes , Yuanyuan Jia , Yue Wu , SonBinh T. Nguyen , Rodney S. Ruoff Synthesis of graphene-based nanosheets via chemical reduction of exfoliated graphite oxide. Carbon 2007, 45, 1558-1565. (26) Laura J. Cote, F. K., and Jiaxing Huang, Langmuir-Blodgett Assembly of Graphite Oxide SingleLayers. J Am Chem Soc 2009. (27) Yongli Che, Y. Z., Xiaolong Cao, Xiaoxian Song, Mingxuan Cao, Haitao Dai, Junbo Yang, Guizhong Zhang and Jianquan Yao, Low operating voltage ambipolar graphene oxide-floatinggate memory devices based on quantum dots. J. Mater. Chem. C 2016, 4, 1420-1424. (28) Guo Liang Li, G. L., Min Li, Dong Wan, K. G. Neoh, and E. T. Kang, Organo- and WaterDispersible Graphene Oxide-Polymer Nanosheets for Organic Electronic Memory and Gold Nanocomposites. the Journal of Physical Chemistry C 2010, 114, 12742-12748. (29) Hu Young Jeong, J. Y. K., Jeong Won Kim, Jin Ok Hwang, Ji-Eun Kim, Jeong Yong Lee, Tae Hyun Yoon, Byung Jin Cho, Sang Ouk Kim, Rodney S. Ruoff, and Sung-Yool Choi, Graphene oxide thin films for flexible nonvolatile memory applications. Nano Lett 2010, 10, 4381-6. (30) Zhou, Y.; Han, S. T.; Sonar, P.; Roy, V. A., Nonvolatile multilevel data storage memory device from controlled ambipolar charge trapping mechanism. Sci Rep 2013, 3, 2319. (31) L. W. Yu, K. J. C., H. L. Ding, J. Xu, K. Liu, W. Li, X. Wang, and X. F. Huang, Modeling and simulation for the enhancement of electron storage in a stacked multilayer nanocrystallite silicon floating gate memory. J Appl Phys 2007, 102, 014501.


19

ACS Photonics

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 20 of 21

TOC Graphic


20

Page 21 of 21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Photonics

a Table of Contents (TOC) Graphic 88x34mm (300 x 300 DPI)


Ambipolar Quantum-Dot-Based Low-Voltage ... - ACS Publications

Recommend Documents