LETTER pubs.acs.org/NanoLett
Hybrid Si Nanowire/Amorphous Silicon FETs for Large-Area Image Sensor Arrays William S. Wong,*,† Sourobh Raychaudhuri, Rene Lujan, Sanjiv Sambandan,‡ and Robert A. Street Palo Alto Research Center, Palo Alto, California 94304, United States ABSTRACT: Silicon nanowire (SiNW) field-effect transistors (FETs) were fabricated from nanowire mats mechanically transferred from a donor growth wafer. Top- and bottom-gate FET structures were fabricated using a doped a-Si:H thin film as the source/drain (s/d) contact. With a graded doping profile for the a-Si:H s/d contacts, the off-current for the hybrid nanowire/ thin-film devices was found to decrease by 3 orders of magnitude. Devices with the graded contacts had on/off ratios of ∼105, fieldeffect mobility of ∼50 cm2/(V s), and subthreshold swing of 2.5 V/decade. A 2 in. diagonal 160 180 pixel image sensor array was fabricated by integrating the SiNW backplane with an a-Si:H p-i-n photodiode. KEYWORDS: Silicon nanowire field-effect devices, large-area electronics, image sensor array, doped a-Si:H, graded doping, a-Si:H photodiodes
T
he potential for using nanoscale materials in high-performance electronics has spurred the recent advancements in nanowire-based devices where sensors,1 photovoltaics,2 batteries,3 and complementary metaloxidesemiconductor (CMOS) circuits4 are just a few target areas. Large-area electronics (LAE) combines many of these technologies into an integrated system in applications such as electronic readers, flat-panel displays, and medical imagers.5 Flexible electronics is an emerging technology based, in many ways, on LAE where additional constraints include low-cost, lightweight, and a mechanically compliant form factor.68 Nanofabrication and nanowire-based devices may offer new solutions and advantages for surpassing the aggressive requirements of flexible electronics where the current research activity is dominated by thin-film materials and devices. While the potential for these nanomaterials is high, many issues still require attention before large-scale commercial applications can be realized. Some of these issues are rather fundamental, such as integration and assembly, electrical contacts, and controlled doping. As the scaling for monolithic integration of Si-based transistors requires smaller and smaller devices, nanoscale materials are an attractive alternative to top-down miniaturization. Reports have shown that Si nanowires can potentially be used in CMOS applications and as field-effect transistors (FETs) on flex.9,10 In contrast to CMOS operation, large-area electronics used in displays and image sensors typically operate under higher voltage conditions. In many cases, the switching voltage of the media defines the gate and source/drain (s/d) voltage requirements. For displays to provide adequate contrast, the data voltage is typically >10 V with a gate voltage swing of 1520 V. In this paper, we describe the currentvoltage characteristics of nanowire FETs under these operating conditions. Top- and bottom-gate FET arrays were fabricated using a r 2011 American Chemical Society
combination of layer transfer for the nanowire assembly and doped amorphous silicon thin films for the s/d contacts. A topgate structure was used to allow the SiNW channel region to be surrounded by the gate dielectric and electrode, providing a more uniform electric field around the nanowire structure.11 The fabrication of the nanowire-FET devices followed a conventional a-Si:H thin-film process using plasma-enhanced chemical vapor deposition (PECVD) for the thin-film materials, sputtering for the metals, and conventional photolithography for the pattern definition. A prototype a-Si:H p-i-n sensor array was then fabricated using this hybrid nanowire/thin film fabrication scheme to demonstrate the feasibility of using SiNWs for largearea backplane applications with conventional thin-film sensor materials. Si nanowires were first grown by chemical-vapor deposition (CVD) using the vaporliquidsolid (VLS) process with a sputtered 5 nm Au film as the seed layer on a 4 in. Si Æ100æ substrate. The VLS process was carried out at 450 C for 40 min with a reactor pressure of 500 Torr and a Si partial pressure of 4.1 Torr. The as-grown nanowires have nominal diameters of ∼90 nm and lengths of about 100 μm. The as-grown SiNWs were then transferred onto the process wafer consisting of a 100 nm thick thermal oxide on a lightly p-doped Si wafer using a mechanical sliding technique. The sliding process transfers and aligns the nanowires from the growth substrate onto the process wafer.12 Figure 1 shows the steps for fabricating the SiNW FETs by this transfer method. The transferred SiNWs were then coated with 50 nm of silicon dioxide and a subsequent layer of silicon nitride by PECVD to Received: January 11, 2011 Revised: May 4, 2011 Published: May 17, 2011 2214
dx.doi.org/10.1021/nl200114h | Nano Lett. 2011, 11, 2214–2218
Nano Letters
LETTER
Figure 3. IV characteristic of a hybrid thin-film/SiNW FET device. Solid lines are calculated curve fits to the measured data (symbols).
Figure 1. Schematic of the SiNW transfer process and device fabrication. (a, b) First the SiNWs are transferred from the growth substrate to the process wafer. (c) The doped s/d contacts are deposited and defined followed by (d) island etching of the active nanowire area. (e) The final step is deposition of the gate dielectric and the top gate electrode.
Figure 4. Off-current as a function of applied source/drain voltage for a typical FET with nongraded doped s/d contacts.
and a plan view scanning electron microscopy (SEM) image is shown in Figure 2b of a finished device. The gradual-channel approximation was used to model the measured currentvoltage (IV) device data where the current in the linear regime, (VG VT) < Vds, is " # W Vds2 Ids ¼ μC ðVG VT ÞVds ð1Þ L 2 while in the saturation regime, (VG VT) > Vds, the current is " # W ðVG VT Þ2 Ids ¼ μC ð2Þ L 2
Figure 2. (a) Cross-sectional schematic of the SiNW FET device. (b) Plan-view SEM micrograph of a finished hybrid FET.
form a top-gate dielectric. Via openings for the source and drain region were then patterned and a 50 nm thick doped a-Si:H film (having a dopant concentration of approximately 3 1018cm3) was then deposited over the openings followed by a 100 nm thick Cr/Mo contact metal. The sourcedrain and top-gate electrode was then patterned to complete the FET structure. This device structure allowed for characterization of both a common bottom gate FET (using the Si substrate as the gate electrode having a thermally grown silicon dioxide gate dielectric) and a patterned top-gate FET using the PECVD deposited gate dielectric. Figure 2a shows a cross-sectional schematic of the final device structure
The parameters in eqs 1 and 2 are as follows: μ, the field-effect mobility; C, the gate capacitance, and VT, VG, and Vds, being the threshold voltage, gate voltage, and s/d voltage, respectively. SEM imaging was used to determine the geometry of the fabricated devices. The channel width (W) was estimated by counting the number of nanowires that spanned the s/d contacts and multiplying the number of wires across the width by the diameter of the nanowire. The channel length (L) was determined by the photolithographic patterning. The density of nanowires that bridged the s/d contact across the channel region (along the channel width) was approximately one nanowire every 2 μm with the nanowire length varying between 5 and 10 μm and a diameter of approximately 100 nm. The density of bridged wires substantially dropped for devices having channel lengths greater than 10 μm. Fitting of the device data with the above equations showed the SiNW FETs behaved very much like a conventional thin-film device when measured in both the top- and bottom-gate configuration. Figure 3 shows a typical currentvoltage (IV) output characteristic for a SiNW FET 2215
dx.doi.org/10.1021/nl200114h |Nano Lett. 2011, 11, 2214–2218
Nano Letters
Figure 5. IV characteristics of a FET with a graded doped a-Si:H s/d contact for top and bottom-gated devices.
having an effective channel width of 2 μm (approximately 20 nanowires bridged across the s/d contacts having a 50 μm width) and a channel length of 8 μm. In the linear and saturation regimes, the measured threshold voltages were between 5 and 10 V and the calculated field-effect mobility ranged from 40 to 50 cm2/(V s) with a subthreshold swing of ∼2.5 V/decade. For small Vds ( 5 V. The same devices measured in the bottom-gate geometry resulted in on/off ratios of 105. Figure 5 shows the IV characteristics for a bottom-gate (solid lines and symbols) and top gate (dashed line) FET using this graded doping approach. The slightly higher off-current in the top-gate geometry may be explained by differences in the quality between the PECVD deposited gate dielectric and the thermal oxide used in the bottom-gate devices. The PECVD dielectric is expected to be of lower quality compared to the thermally grown oxide on Si, resulting in higher gate leakage. There was no measurable improvement in terms of the field-effect mobility or the threshold voltage for the devices with the graded contacts. In the second approach, the top-gate dielectric thickness was varied, thus varying the electric field across overlap between the
LETTER
Figure 6. Comparison of on/off ratios for bottom-gate devices with graded doping (solid symbols), nongraded doping (open symbols), thick (square) and thin (triangle) silicon nitride gate dielectric, and bottom-gate devices with graded doping (cross).
Figure 7. Optical micrograph of a portion of the nanowire FET array.
bottom s/d metal and the top-gate electrode, to determine its effect on the off-current. In this approach, the s/d contact doping was constant and the off current was measured as a function of dielectric thickness. Figure 6 shows the onoff ratio as a function of s/d voltage for different dielectric thicknesses. The highest on/ off ratios were found for devices with the thicker silicon-nitride layers. These values were similar to devices that had the graded nþ contacts (solid symbols) with the bottom-gate geometry (cross symbol). Combining the graded doping with the thicker dielectric layer resulted in the highest on/off ratios, suggesting the increased off current was due mainly to tunneling injection caused by high electric fields. A 160 180 pixel SiNW backplane array (with 300 μm pitch) was fabricated using the patterned top-gate geometry FET. After the FET processing, an oxinitride encapsulation layer was deposited over the SiNW top electrodes followed by patterning and etching of via openings to provide access to the gate and pixel pad contacts. Figure 7 is an optical micrograph showing a few pixels from the array. A large channel width was used to increase the probability of capturing a nanowire that spanned the channel region. The SEM characterization showed a high number of nanowires across the channel area indicating the TFT dimensions could be made smaller in future pixel designs. Qualitative array characterization of the pixel yield was performed prior to the sensor integration by using a pixel-charge measurement technique.17 This technique maps the charge signal, due to capacitive coupling in the pixel circuit, for each pixel in the 2216
dx.doi.org/10.1021/nl200114h |Nano Lett. 2011, 11, 2214–2218
Nano Letters
LETTER
15 and 6 V, respectively, a gate pulse length of 20 μs, and a frame time of 0.25 s. The image has had a gain and offset correction, and partial correction for bad lines. The image shows that the majority of the 36000 pixel TFTs respond, but there are also many defects as discussed above. High TFT leakage current was also the origin of some defects as explained earlier. A smaller TFT width and more controlled nanowire deposition should greatly improve the array performance. The SiNW device results, along with the efficacy of the graded doping of the SiNW FET s/d contacts demonstrate the potential for integrating nanowire FETs with thin-film materials and processing for applications in large-area electronics. Combining the graded doping of the thin film s/d contacts with improved process integration of the hybrid nanowire/thin-film devices will help to guide the development and incorporation of nanowirebased large-area flexible electronics.
’ AUTHOR INFORMATION Figure 8. Cross-sectional schematic of the backplane and sensor structure.
Corresponding Author
*E-mail:
[email protected]. Present Addresses †
Department of Electrical and Computer Engineering, University of Waterloo, 200 University Ave. West, Waterloo, ON N2L 3G1, Canada. ‡ Department of Instrumentation and Applied Physics, Indian Institute of Science, Bangalore-560 012, Karnataka, India.
Figure 9. (a) Part of a charge map of SiNW FET array before photodiode integration. White dots are pixel defects. (b) Light image capture from a SiNW FET backplane and a-Si:H p-i-n photodiode array.
array; any leakage of charge due to processing defects, shorts, film quality, or interlayer shunts will contribute to a variation in pixelto-pixel readings. Figure 8 shows a cross-sectional schematic of the array, and Figure 9a is a charge map of part of the SiNW array revealing a mixture of working (low-contrast pixels) and poorly performing (high-contrast pixels) SiNW FETs along with busline defects (high-contrast lines) and crossover shorts (dark lines) within the array. One reason for the relatively high number of pixel defects is due to local variations in the density of nanowires across the array. The local variation originates from the mechanical nature of the transfer process that may leave openings in the nanowire mat. This process nonuniformity contributes to the charge injection differences of the pixel FET and appears as a contrast difference from pixel-to-pixel. While the number of defects is relatively high, the test identifies specific areas for optimization, such as improved applied nanowire uniformity and pressure distribution during the growth and transfer process for future development of these hybrid devices. To demonstrate the viability of SiNW backplanes for largearea applications, an a-Si:H p-i-n diode stack was deposited onto the backplane to create an image sensor array. The process for integrating the p-i-n photodiode is similar to that reported in ref 18. These thin-film photodiodes have an external quantum efficiency of approximately 65%. Figure 9b shows a projected light image captured by the a-Si:H photodiode/SiNW array. The image was acquired with gate-on and gate-off voltages of
’ ACKNOWLEDGMENT The authors thank T. N. Ng of PARC for useful discussions in the FET device modeling. ’ REFERENCES (1) Cui, Y.; Wei, Q.; Park, H.; Lieber, C. M. Nanowire nanosensors for highly sensitive and selective detection of biological and chemical species. Science 2001, 293, 1289. (2) Kelzenberg, M. D.; Turner-Evans, D. B.; Kayes, B. M.; Filler, M. A.; Putnam, M. C.; Lewis, N. S.; Atwater, H. A. Photovoltaic measurements in single-nanowire silicon solar cells. Nano Lett. 2008, 8, 710. (3) Chan, C. K.; Peng, H. L.; Liu, G.; McIlwrath, K.; Zhang, X. F.; Huggins, R. A.; Cui, Y. High-performance lithium battery anodes using silicon nanowires. Nat. Nanotechnol. 2008, 3, 31. (4) Friedman, R. S.; McAlpine, M. C.; Ricketts, D. S.; Ham, D.; Lieber, C. M. High-speed integrated nanowire circuits. Nature 2005, 434, 1085. (5) Reuss, R. H.; Chalamala, B. R.; Moussessian, A.; Kane, M. G.; Kumar, A.; Zhang, D. C.; Rogers, J. A.; Hatalis, M.; Temple, D.; Moddel, G.; Eliasson, B. J.; Estes, M. J.; Kunze, J.; Handy, E. S.; Harmon, E. S.; Salzman, D. B.; Woodall, J. M.; Alam, M. A.; Murthy, J. Y.; Jacobsen, S. C.; Olivier, M.; Markus, D.; Campbell, P. M.; Snow, E. Macroelectronics: perspectives on technology and applications. Proc. IEEE 2005, 93, 1239. (6) Wong, W. S.; Lujan, R.; Daniel, J. H.; Limb, S. Digital lithography for large-area electronics on flexible substrates. J. Non-Cryst. Solids 2006, 352, 1981. (7) Sarma, K. R.; Chanlet, C.; Dodd, S.; Roush, J.; Schmidt, J.; Srdanov, G.; Stevenson, M.; Wessel, R.; Innocenzo, J.; Yu, G.; O’Regan, M.; MacDonald, W. A.; Eveson, R.; Long, K.; Gleskova, H.; Wagner, S.; Sturm, J. C. Active matrix OLED using 150C a-Si TFT backplane built on flexible plastic substrate. Proc. SPIE 2003, 5080, 180. (8) Lacour, S. P.; Jones, J.; Wagner, S.; Li, T.; Suo, Z. Stretchable interconnects for elastic electronic surfaces. Proc. IEEE 2005, 93, 1459. 2217
dx.doi.org/10.1021/nl200114h |Nano Lett. 2011, 11, 2214–2218
Nano Letters
LETTER
(9) Cohen, G. M.; Rooks, M. J.; Chu, J. O.; Laux, S. E.; Solomon, P. M.; Ott, J. A.; Miller, R. J.; Haensch, W. Nanowire metal-oxide semiconductor field-effect transistor with doped epitaxial contacts for source and drain. Appl. Phys. Lett. 2007, 233110. (10) Duan, X.; Niu, C.; Sahi, V.; Chen, J.; Parce, J. W.; Empedocles, S.; Goldman, J. L. High-performance thin-film transistors using semiconductor nanowires and nanoribbons. Nature 2003, 425, 274. (11) Wunnicke, O. Gate capacitance of back-gated nanowire fieldeffect transistors. Appl. Phys. Lett. 2006, 89, 083102. (12) Javey, A.; Nam, S.; Friedman, R. S.; Yan, H.; Lieber, C. M. Layer-by-layer assembly of nanowires for three-dimensional, multifunctional electronics. Nano Lett. 2007, 7, 773. (13) Street, R. A.; Wong, W. S.; Lujan, R. Low-temperature amorphous silicon p-i-n photodiodes. Phys. Status Solidi B 2009, 246, 1854. (14) Fossum, J. G.; Ortiz-Conde, A; Shichijo, H.; Banerjee, S. K. Anomalous leakage current in LPCVD polycrystalline. IEEE Trans. Electron Devices 1985, ED-32, 1878. (15) Madan, S.; Antoniadis, D. A. Leakage current mechanisms in hydrogen-passivted fine-grain polycrystalline silicon on insulator MOSFETs. IEEE Trans. Electron Devices 1986, ED-33, 1518. (16) Street, R. Hydrogenated Amorphous Silicon; Cambridge University Press: Cambridge and New York, 1991. (17) Sambandan, S.; Apte, R. B.; Wong, W. S.; Lujan, R.; Young, M.; Russo, B.; Ready, S.; Street, R. A. Defect identification in large-are electronic backplanes. J. Disp. Technol. 2009, 5, 27. (18) Ng, T. N.; Lujan, R. A.; Sambandan, S.; Street, R. A.; Limb, S.; Wong, W. S. Low temperature a-Si:H photodiodes and flexible image sensor arrays patterned by digital lithography. Appl. Phys. Lett. 2007, 91, 063505.
2218
dx.doi.org/10.1021/nl200114h |Nano Lett. 2011, 11, 2214–2218
