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Amorphous Strontium Titanate Film as Gate Dielectric for Higher Performance and Low Voltage Operation of Transparent and Flexible Organic Field Effect Transistor Sarita Yadav and Subhasis Ghosh* School of Physical Sciences, Jawaharlal Nehru University, New Delhi 110067, India ABSTRACT: We report that the pervoskite material, strontium titanate (STO) can be used as a gate dielectric layer of flexible and low voltage organic field effect transistor (OFET). The crystallinity, dielectric constant, and surface morphology of STO films can be controlled by the engineering of the growth condition. Under optimized growth condition, amorphous films of STO show a much better gate dielectric compared to other gate dielectrics used to date, with very small leakage current density for flexible and low voltage (3) order less in magnitude with respect to e-beam evaporated Ta2O5 and ZrO2.21,22 The breakdown field in STO devices is larger than 0.4 MV/cm. Capacitance−frequency (C−f)
Figure 3. AFM topographic images of ultrathin (1 nm) film of (a),(b) pentacene (2 × 2 μm2) grown at 40 °C and (c),(d) CuPc (1 × 1 μm2) grown at 100 °C substrate temperature. The left panel shows the surface morphology on the SiO2 substrate and the right, the amorphous STO substrate.
films of pentacene and CuPc on SiO2 and amorphous STO substrates. The surface morphology of the pentacene thin film (1 nm) on an amorphous STO substrate shows that the interconnectivity within sub monolayers is larger than that on the SiO2 substrate, and in the case of the CuPc surface morphology, it shows strongly interconnected grains on the amorphous STO compared to that on the SiO2 substrate. The coverage and grain boundaries between coalescing islands
Figure 2. (a) J−V and (b) C−f characteristics in logarithmic scale of Au/STO/n+2-Si Au/STO/ITO-Glass and Au/STO/ITO-PET devices. STO films were grown at substrate temperatures of 50 and 600 °C. C
DOI: 10.1021/acsami.6b02847 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
Research Article
ACS Applied Materials & Interfaces determine the percolation pathways in the initial layer of organic film on the dielectric surface. The large coverage and interconnectivity between grains of the initial layers of the organic molecules on the amorphous STO substrate is more than that on the SiO2 substrate, resulting in high percolation on the STO dielectric which enhances the charge transport properties.26 The full coverage and strong interconnectivity between grains of initial layers of organic molecules also reduces the number of electrical trap states at the organic/gate dielectric interface. These trap states exist due to the voids or non interconnectivity between grains.14 The lower number of trap states and large percolation paths at the interface of organic and amorphous STO dielectrics reduce the subthreshold swing (S) and threshold voltage and increases the charge carrier mobility. The transistor characteristic of pentacene and CuPc OFETs with SiO2, amorphous STO, and polycrystalline STO gate dielectric are shown in Figures 4 and 5, respectively. The
Figure 5. Output and transfer characteristics of CuPc OFETs with (a), (b) SiO2, (c),(d) amorphous STO and (e),(f) polycrystalline STO gate dielectrics. The amorphous and polycrystalline films of STO were grown at substrate temperature 50 and 600 °C on heavily doped Si substrate, respectively. For OFETs with SiO2 and STO gate dielectrics, the transfer characteristics were measured at VDS = −1 V and −0.2 V, respectively, and solid lines are the fitting of IDS1/2 vs VGS data.
The OFETs in which STO gate dielectric were grown at 50 °C have very small S ≈ 0.3 V/dec and Vth ≈ −1 V. A high saturation current (15 μA) at VGS = −5 V has been observed in pentacene OFETs with amorphous STO gate dielectric and high VGS ≈ −35 V is required to obtain similar current in OFETs with SiO2 gate dielectric. Pentacene OFETs with amorphous STO gate dielectric have large charge carrier mobility (1.3 cm2/(V s)) compared to that (0.2 cm2/(V s)) with SiO2 gate dielectric. Pentacene OFETs with polycrystalline gate dielectric films (Figure 4e and f) of STO (600 °C) have a large Vth (−3.2 V) and S (0.9 V/dec) compared to that with amorphous STO gate dielectric. Higher surface roughness of polycrystalline dielectric films form trap states and less contact area at organic/dielectric interface. As we have discussed before, the large number of trap states at the organic/gate dielectric interface increases the Vth and the large barriers due to traps are faced by charge carriers, while flowing from source to drain resulting a reduction in drain current. Similar behavior has been observed in CuPc OFETs with SiO2 and polycrystalline STO gate dielectric. CuPc OFETs with amorphous STO gate dielectric layer have excellent transistor characteristics with Vth of −1.0 V, on/off ratio of 105, carrier mobility of 5.9 × 10−2 cm2/(V s) and low S (∼0.6 V/dec). To our knowledge, these are the highest charge carrier mobilities and on/off ratios reported for low voltage CuPc OFETs.2,27 The CuPc OFETs with SiO2 and polycrystalline STO gate dielectric layers have similar Vth (∼2.4 V) and carrier mobilities (1.2 × 10−2 cm2/(V s)). We have also fabricated OFET of n-type material F16CuPc, transfer and output characteristics of F16CuPc OFET are shown
Figure 4. Output and transfer characteristics of pentacene OFETs with (a),(b) SiO2, (c),(d) amorphous STO and (e),(f) polycrystalline STO gate dielectrics. The amorphous and polycrystalline films of STO were grown at substrate temperature 50 and 600 °C on heavily doped Si substrate, respectively. For OFETs with SiO2 and STO gate dielectrics, the transfer characteristics were measured at VDS = −1 V and −0.2 V, respectively, and solid lines are the fitting of IDS1/2 vs VGS data.
operating voltage of OFETs with STO gate dielectric is reduced by ten times compared to OEFTs with SiO2 gate dielectric. The surface roughness of SiO2 and amorphous STO gate dielectric films are almost equal but, as discussed before, the initial growth of organic molecules on STO have more interconnected grains and full coverage. Pentacene OFETs with SiO2 gate dielectrics have high S (3.3 V/dec) and larger Vth ≈ −1.8 V compared to transistors with amorphous STO gate dielectric. D
DOI: 10.1021/acsami.6b02847 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
Research Article
ACS Applied Materials & Interfaces
surface roughness of polycrystalline films forms traps at the interface of organic and gate dielectric which increases the threshold voltage and leakage current. The above results show that the low driving OFETs with amorphous STO gate dielectric have better device performance compared to that with polycrystalline STO. The low processing temperature required for amorphous STO layer facilitates the use of STO as gate dielectric on flexible substrate for the fabrication of flexible OFETs. Further we have fabricated the OFETs on the transparent ITO coated glass and PET substrates. Amorphous film of STOs were grown at 50 °C on ITO-coated glass and PET substrate using sputtering, and then pentacene was deposited on the substrate in the thermal evaporation system. The surface morphology of pentacene on these substrates is similar to that on the STO/Si substrate. The output and transfer characteristics of the pentacene transistor on an ITO coated flexible PET and glass substrate with an amorphous STO dielectric layer has been shown in Figure 7 which also shows the photograph of the device on the flexible (PET) and glass substrate. Pentacene transistors on the flexible substrate show a near zero turn-on voltage and low Vth of −1.1 V and exhibit excellent transistor behavior below −5 V with carrier mobility of 1.1 cm2/(V s). Pentacene OFET with glass substrate also shows a very high mobility of 2.0 cm2/(V s) and Vth of −1.5 V. Subthreshold swing of pentacene transistors on glass and PET substrates are 0.6 V/dec and 0.7 V/dec, respectively, determined from transfer characteristic. Table 2 shows the comparison of transistor parameters of pentacene and CuPc OFETs with different polymer and oxide gate dielectrics. Table 2 reveals that the mobility, threshold voltage and on/off ratio of pentacene and CuPc OFETs with STO gate dielectric are comparable to others reported values with advantage of very low processing temperature of STO.
in Figure 6. Similar behavior has been observed in CuPc and F16CuPc OFETs with amorphous and polycrystalline STO gate
Figure 6. Output and transfer characteristics of F16CuPc OFETs with (a),(b) amorphous and (c),(d) polycrystalline STO gate dielectric.
dielectric. F16CuPc OFETs with SiO223 and STO gate dielectrics have a similar carrier mobility but a huge reduction in Vth has been observed in OFETs with amorphous STO gate dielectric. The Vth of F16CuPc transistor with amorphous STO gate dielectric is 0.1 V, whereas with SiO2 gate dielectric that is very high. Thus, in OFETs, the transfer characteristics are hugely influenced by the interface trap states, which lead to the degradation of the subthreshold slope. The device parameters of OFETs are summarized in Table 1. The maximum interface trap density can be obtained from S using the following relation:28
4. CONCLUSIONS We have shown that the operating voltage of organic transistors can be reduced by using STO as gate dielectric, and the interface trap density can be reduced by engineering the organic/gate dielectric interface. We have observed that the low surface roughness of amorphous STO films form a better organic/dielectric interface with fewer traps, enhancing the transfer characteristics of OFETs. Transistor performances are reduced with polycrystalline STO gate dielectric due to higher surface roughness of dielectric films. The low processing temperature and transparency of amorphous STO films give opportunity to use as gate dielectric layer for flexible and transparent devices. Pentacene OFETs on flexible and glass substrates have high charge carrier mobility and on/off ratio with low subthreshold slope. Highest charge carrier mobility has been observed in low operating voltage CuPc OFET.
⎡ ⎤C S NT = ⎢ − 1⎥ OX ⎣ ln 10kBT /q ⎦ q
where q is the elementary charge, and kB is the Boltzmann constant. Interface trap density calculated for OFETs with amorphous and polycrystalline STO dielectric has been given in Table 1. The interface trap density of pentacene transistors with amorphous STO is 6.9 × 1011 cm−2eV−1 which is one order less than that with polycrystalline STO and SiO2 gate dielectric. CuPc and F16CuPc based transistors have four and five times less interface trap density with amorphous STO gate dielectric compared to that with polycrystalline STO, respectively. Therefore, it is clear that there are substantial improvements in performance of OFETs with amorphous STO gate dielectric layer which forms a better interface between organic and dielectric facilitating efficient charge carrier transport. The large
Table 1. Device Parameters of Pentacene and CuPc OFETs with SiO2 and STO Gate Dielectric organic molecule pentacene (TG= 40 °C)
CuPc (TG = 100 °C)
gate dielectric SiO2 STO STO SiO2 STO STO
(TG = 50 °C) (TG = 600 °C) (TG = 50 °C) (TG = 600 °C)
μ (cm2/(V s)) 0.2 1.3 1.9 1.2 5.9 1.2
× × × ×
10−2 10−2 10−2 10−2 E
Vth (V) −1.8 −1.0 −3.2 −2.4 −1.0 −2.3
S (V/dec.) 3.3 0.3 0.9 3.8 0.6 1.1
Ion/Ioff 5
10 106 102 104 104 104
NT (cm−2eV−1) 3.4 5.2 3.6 4.0 1.3 4.4
× × × × × ×
1012 1011 1012 1012 1012 1012
DOI: 10.1021/acsami.6b02847 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
Research Article
ACS Applied Materials & Interfaces
Figure 7. Photographic images and transistor characteristics of pentacene transistors on the (a) flexible and (b) glass substrates. The transfer characteristics were measured at VDS = −0.2 V.
Table 2. Device Parameters of Pentacene and CuPc OFETs with Different Gate Dielectrics organic molecules pentacene
CuPc
substrate Si Si Si Si Si (current work) PET PET PEN PET (current work) ITO/glass (current work) Si ITO/glass Si (current work)
gate dielectric
TG of gate dielectric (°C)
HfLaO/PVP HfO2/SAM cyanoethylated pillulan BaSrTiO3 (BST) STO BaSrTiO3nanoparticles sol−gel silica BST STO STO PTS (SAM layer) PMMA-GMA STO
300 550 200 50 100 100 50 50
■
Hence STO has the potential for use as a gate dielectric for low voltage operating, flexible, and transparent organic electronics.
■
μ (cm2/(V s))
50
0.34 0.8 2.16 0.289 1.3 1−2 3.5 0.252 1.1 2.0 3.5 × 10−2 1.2 × 10−3 5.9 × 10−2
Vth (V) −0.5 −0.99 −1.18 −1.0 −0.8−2.0 −1.16 −1.1 −1.5 −0.2 −1.0
Ion/Ioff 2 107 2.4 104 106 103 105 104 105 105 1.5 2 105
ref. no.
× 10
5
× 103
29 30 31 32 33 34
× 103 × 103
2 27
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AUTHOR INFORMATION
Corresponding Author
*E-mail:
[email protected] (S.G.). Notes
The authors declare no competing financial interest.
■
ACKNOWLEDGMENTS S.Y. thanks CSIR, India for the financial support. This work was partly supported by DST, Govt. of India. F
DOI: 10.1021/acsami.6b02847 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
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ACS Applied Materials & Interfaces
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DOI: 10.1021/acsami.6b02847 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX
