Atomic-Scale, All Epitaxial In-Plane Gated Donor Quantum Dot in Silicon

Jan 2, 2009 - We anticipate our experiments will open the door for controlled scaling of silicon devices toward the single donor limit. The use of hyd...
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NANO LETTERS

Atomic-Scale, All Epitaxial In-Plane Gated Donor Quantum Dot in Silicon

2009 Vol. 9, No. 2 707-710

A. Fuhrer,*,† M. Fu¨chsle,‡ T. C. G. Reusch,‡ B. Weber,‡ and M. Y. Simmons‡ School of Physics, Centre for Quantum Computer Technology, School of Physics, UniVersity of New South Wales, Sydney, New South Wales 2052, Australia Received October 21, 2008; Revised Manuscript Received December 18, 2008

ABSTRACT Nanoscale control of doping profiles in semiconductor devices is becoming of critical importance as channel length and pitch in metal oxide semiconductor field effect transistors (MOSFETs) continue to shrink toward a few nanometers.1,2 Scanning tunneling microscope (STM) directed self-assembly of dopants is currently the only proven method for fabricating atomically precise electronic devices in silicon. To date this technology has realized individual components of a complete device with a major obstacle being the ability to electrically gate devices. Here we demonstrate a fully functional multiterminal quantum dot device with integrated donor based in-plane gates epitaxially assembled on a single atomic plane of a silicon (001) surface. We show that such in-plane regions of highly doped silicon can be used to gate nanostructures resulting in highly stable Coulomb blockade (CB) oscillations in a donor-based quantum dot. In particular, we compare the use of these all epitaxial in-plane gates with conventional surface gates and find superior stability of the former. These results show that in the absence of the randomizing influences of interface and surface defects the electronic stability of dots in silicon can be comparable or better than that of quantum dots defined in other material systems. We anticipate our experiments will open the door for controlled scaling of silicon devices toward the single donor limit.

The use of hydrogen resist lithography for atomic-scale device fabrication is currently pursued by several groups for either dopant-based,3-5 nanotube,6 or molecular electronic7 devices. In addition to developing atomically abrupt dopant profiles for continued silicon miniaturization,8 the concept of patterning of donors in silicon by STM was proposed over 10 years ago for the realization of atomically precise architectures for applications in single electronics and quantum computing circuits.4,9 Since then significant advances have been made in the scientific development of sub 30 nm donor-based nanostructures for electronic transport measurements.3,10,11 However, to date the technique has only been used to study individual components of a complete device architecture such as donor nanowires and tunnel junctions with dimensions of a few nanometers. One of the main obstacles to the broader application of this technology has been the ability to controllably gate these nanostructures. Here, we demonstrate the use of highly doped epitaxial silicon gates STM-patterned in the same plane as a quantum dot device with nm position accuracy and extremely high electronic stability. Device fabrication was performed on an Omicron variable temperature ultrahigh vacuum (UHV) scanning tunneling microscope (STM) system with phosphine and hydrogen microdosing systems and a silicon sublimation (SUSI) cell * To whom correspondence should be addressed. E-mail: [email protected]. † School of Physics. ‡ Centre for Quantum Computer Technology, School of Physics. 10.1021/nl803196f CCC: $40.75 Published on Web 01/02/2009

 2009 American Chemical Society

attached to it. The surface of an n-type 1-10 Ωcm silicon sample with etched registration markers was prepared for lithography by flashing to 1100 °C with direct current heating. The Si(001) surface is terminated with hydrogen, introduced through a cracker source at a pressure of 5 × 10-7 mbar for 6 min while heating the sample at 340 °C. This hydrogen resist is then selectively removed with the STM tip by applying a sample bias Vsmpl ) 4-8 V and using a feedback current I0 ) 1-3 nA. At a sufficiently high current density, the covalent bonds between the hydrogen and the surface Si atoms are broken and dangling bonds are created where the STM tip is scanned.12 Subsequent room temperature saturation dosing with PH3 at a pressure P ) 5 × 10-9 mbar for 5 min and thermal incorporation of the phosphorus into the Si surface at T ) 350 °C for 1 min leads to a highly conductive phosphorus doped δ-layer (Nph ≈ 1 2 × 1014 cm-2) at the surface in the areas where the hydrogen was desorbed by the STM tip. Figure 1a shows a composite filled state STM image (Vsmpl ) -1.8 V, I0 ) 0.1 nA) taken immediately after patterning the quantum dot structure in the hydrogen terminated silicon surface by selective hydrogen desorption with the STM. All of the active device area lie on a single monatomic terrace and appear bright in the STM-images due to a change in the electronic structure at a dangling bond site compared to the hydrogen-terminated areas. The dot in the center is connected by two 8 nm wide tunnel gaps to the source and drain terminals which have a minimum width of 4 nm (∼5 silicon

blue. An array of 50 nm deep holes with a diameter of about 100 nm that are drilled into the donor patches using reactive ion etching help to form low resistance ohmic contacts. Before evaporating the aluminum contacts, we dip-etch the device in hydrofluoric acid to remove the native oxide. The sample is then annealed at 350 °C for 15 min and wire bonded to a chip carrier. All measurements were performed in a dilution refrigerator at a base temperature of T ≈ 80 mK unless stated otherwise. In order to suppress the superconductivity of the aluminum contacts at low temperature, we typically apply a magnetic field B ) 100 mT.

Figure 1. (a) Composite STM image of the device (bright regions) directly after performing STM lithography on a single atomic terrace on the Si(001)/H surface. The insets with the green borders magnify the 4 nm wide leads (5 dimers wide) and the 8 nm tunnel barriers connecting the dot to source and drain. Three in-plane gates (PG, T1, T2) are used to tune the electron number on the quantum dot. (b) SEM image of the device taken after measurements showing the aluminum ohmic contacts (blue shading) aligned ex situ to the donor leads. The table on the right shows how each of the nine leads is connected to the donor contact patches.

dimer rows; see close-up STM images). Three additional areas T1, T2, and PG were patterned for use as in-plane gates to tune the electron number on the dot by applying corresponding gate voltages, VT1, VT2, VPG. All five terminals of the dot are extended out with STM patterning to 3 µm long contact patches leading away from the device. After phosphine dosing and activation of the donors by thermal incorporation, the device is encapsulated by growing a 25 nm thick epitaxial silicon layer over the entire structure. The use of donor based in-plane gate electrodes allows us to fully fabricate the electronically active device area in situ in the UHV environment completely avoiding defect prone interfaces or metallic gate electrodes near the device. A low thermal budget (T < 250 °C) for all the processes leads to minimal diffusion of phosphorus in the silicon and preservation of the STM patterned geometry on the subnanometer scale.3,13 After encapsulation the device is removed from the UHV environment and electron-beam lithography (EBL) is used to align two aluminum ohmic contacts to each of the donor patches as shown in the scanning electron microscope (SEM) image in Figure 1b where the contacts are shaded in 708

As is the advantage of knowing exactly where the dopants are patterned with the STM, electrical characterization of the device is fully consistent with expectations from the geometry of the STM-patterned donor δ-layer. The contact resistance to the donor layer is estimated to be ≈10 kΩ per contact from the current versus voltage (I/V) measurements along each phosphorus donor contact patch (see Figure 2a). Contact combinations across gaps in the patterned donor structure show insulating behavior for small applied bias voltages. Figure 2b shows I/V traces for each of the in-plane gates where we measure the current Ileak flowing from the gate to any of the other terminals. None of the gates show leakage for |Vgate| < 0.25 V. It is interesting to note that the I/V trace for the plunger gate seems to be more symmetric than those of gates T1 and T2 where large positive voltages can be applied to the gates before leakage occurs. This may reflect the fact that the two narrow gate leads T1 and T2 get partially depleted for very positive voltages VT1 or VT2 and thus exhibit larger positive breakdown voltages. For negative VT1 or VT2 the breakdown is governed only by the gap size which is 35 nm for T1 and PG but a few nm smaller in the case of T2. In the case of the three in-plane gates current only flows in the field emission regime when the applied bias has sufficiently narrowed the barrier induced by the intrinsic region in the gap between donor patches. In comparison an I/V trace through the dot (orange curve) shows only a small nonlinear region. Here, the much smaller gaps between dot and source/drain contacts (of the order of twice the Bohr radius aB ≈ 3 nm) were designed to act as tunnel barriers even at small VSD. By applying a fixed bias voltage VSD ) 360 µV clear CB-oscillations are observed in the source-drain current ISD as a function of VPG in the range with no gate-leakage (see Figure 2c). The CB-peak spacing ∆VPG ) 12.5 mV is approximately constant over the entire gate range; however, the peak heights vary strongly. The inset to Figure 2c shows a more careful measurement of two CB-peaks together with a fit to the classical peak shape.14 In our device CB peak conductance is low, which limits us to VSD > 20 µV. At base temperature (T ≈ 100 mK), the broadening due to VSD would thus be considerably larger than the thermal broadening kBT ≈ 10 µeV. However, at this elevated bath temperature T ) 1.1 K we find that classical CB peak fits yield an electron temperature Te ) 1.2 ( 0.1 K that agrees well with that of the cryostat. We estimate the EC ) e2/CΣ ) 3.3 ( 0.2 meV from measurements of the differential dot conductance as a function of VPG and VSD such as the one shown in Figure Nano Lett., Vol. 9, No. 2, 2009

Figure 2. (a) I/V curves between pairs of aluminum electrodes making contact to the same phosphorus donor patch below. The blue shaded numbers correspond to the numbering in Figure 1b. From this we estimate contact resistances of about 10kΩ. (b) Leakage current from each of the gate electrodes to all other contacts as a function of the applied gate voltage. In comparison, the orange I/V curve is a measurement across the device including the two 8 nm wide tunnel junctions of the dot. (c) CB oscillation in the current through the dot as a function of the applied voltage VPG on the plunger gate at VSD ) 360 µV. The inset shows a more careful measurement of two CB peaks at lower source-drain bias VSD ) 20 µV where the red line indicates a fit to theory in the classical CB regime. (d) Colormap showing the differential conductance as a function of VSD and VPG. In order to more clearly resolve the modulation of the current at large VSD, we have subtracted a smooth background obtained by convoluting each I/V trace with a Gaussian (fwhm ) 1.6 mV).

2d. The mutual capacitances extracted from this and the CB peak spacing as a function each gate voltage Cgate ) e/∆Vgate are CPG ) 13.2 aF, CT1 ) 7.2 aF, CT2 ) 7.2 aF, CSource ) CDrain ) 9.7 aF, which are consistent with a sum capacitance CΣ ) 48.5 aF. In addition, we find good agreement with capacitance values calculated using a numerical 3D capacitance solver15 taking the STM-pattern geometry as an input. This gives us further confirmation that the lateral donor pattern remains intact during device encapsulation. From the electron density of a saturation dosed Si/P δ layer and the dot area, we calculate an upper limit for the electron number Ne < 4000. While this estimate does not take into account lateral quantum confinement effects, we expect our dot to be in the classical regime, where many quantum levels contribute to the conductance of a single CB-peak. However, the presence of the resonances in Figure 2d indicates a Nano Lett., Vol. 9, No. 2, 2009

Figure 3. (a) CB peak maximum conductance, GMAX at VSD ) 20 µV as a function of temperature for four different CB peaks shown as red, yellow, black, and orange dots. (b) CB oscillations as a function of the two gate voltages VT1 and VT2 at VSD ) 100 µV. Over most of the gate range the peaks show a perfect 45° slope experimentally confirming the near identical geometric arrangement of these two gates relative to the dot and highlighting the stability of the in-plane gates. (c) Up- and down-sweep with a homogeneous metallic surface gate fabricated on top of the encapsulated device showing clear hysteresis and switching effects.

strongly modulated density of states at the Fermi level either in the source/drain leads or on the dot. Resonances are also found at small VSD as a modulation of the CB peak height (see, e.g., Figure 2c] as a function of magnetic field and gate asymmetry.16 These resonances disappear with increasing temperature, suggesting that transport through the dot has a coherent component. In Figure 3a, we plot the CB peak maximum conductance, GMAX, as a function of temperature for four different CB peak positions (as indicated by the orange, yellow, red, and black dots in Figure 3a). In the temperature range below 2 K, the evolution of GMAX varies strongly, and we find peaks that are completely suppressed at T ) 100 mK (yellow dots in Figure 3a) while others have conductances GMAX ≈ 0.3 × 10-3e2/h (black dots in Figure 3a). CB peaks that show a large GMAX at base temperature become smaller as the temperature increases, while in regions with a very low conductance GMAX increases. Such behavior is typical for quantum dots where a number of quantum states have a large overlap with the source and drain contacts while others are localized more in the inner body of the dot.17 As the temperature is increased further, the CB valley conductance remains largely unaffected since EC . kBT ≈ 430 µeV, but we find a strong increase of the CB peak height. This is in contrast to the expected behavior for both the classical or the quantum limit of CB and is a result of the shallow potential profile produced by the narrow, 8 nm in-plane tunnel barriers, the transmission of which is expected to be strongly energy dependent.18 Single electron transistors and quantum dots in the CB regime have in the past been used as electrometers with 709

sensitivities down to a fraction of a single charge.19 This property also makes quantum dots highly susceptible to interface traps and charged defects in the crystal, which may change their charge state as a function of an applied gate voltage or magnetic field. Tuning the in-plane gates in our quantum dot leads to extremely stable CB-oscillations as is further highlighted in a measurement of the dot conductance as a function of both VT1 and VT2 (see Figure 3b) spanning about half of the available gate range for each of the gates. The CB-peaks move at a 45° slope indicating that the two gates T1 and T2 have the same coupling to the dot as expected from the symmetry of the dot geometry. Upon thermal cycling dot characteristics such as EC, gate capacitance and observation of resonances remain the same to within 10% of the quoted values; however, Coulomb peak positions are shifted by a change in the offset charge configuration from cooldown to cooldown. This highly stable behavior is not observed if we add an additional metallic top-gate (TG) electrode on-top of the silicon surface 25 nm above the donor layer and tune the CB-oscillations using this gate. Figure 3c shows up- and down-sweep of the corresponding gate voltage VTG exhibiting both considerably more noise and hysteretic behavior. Because of the strong capacitive coupling of the top gate to the dot, the CB period ∆VTG ≈ 2.5 mV is much smaller than that of the in-plane gates. We also find that noise and hysteresis effects increase significantly (and often irreversibly for a specific cool-down) when increasing the VTG range.16 We attribute this to charge traps that get activated if the electric field between the device and the top-gate exceeds a certain value (in our case ≈ 2 MeV/m). Complete epitaxial fabrication of a donor device with aligned in-plane gates in a UHV environment therefore has significant advantages over conventional metallic gate electrodes, both in terms of alignment precision, local control of the electrostatic potential and by avoiding the deleterious effects that impurities and charge traps near interfaces may have on electronic device stability.

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Acknowledgment. A.F. acknowledges support through a Vice Chancellor New South Global Fellowship. M.Y.S. acknowledges a Federation Fellowship. Supporting Information Available: An SEM image of the sample with top gate and two additional figures detailing origin and stability of the Coulomb blockade resonances. This material is available free of charge via the Internet at http:// pubs.acs.org. References (1) The 2006 International Roadmap for Semiconductors (ITRS, 2006);http:// www.itrs.net/Links/2006Update/2006UpdateFinal.htm (accessed September 2007). (2) Peercy, P. S. Nature 2000, 406, 1023. (3) Ruess, F. J.; Oberbeck, L.; Simmons, M. Y.; Goh, K. E. J.; Hamilton, A. R.; Hallam, T.; Schofield, S. R.; Curson, N. J.; Clark, R. G Nano Lett. 2004, 4, 1969. (4) Tucker, J. R.; Shen, T. Solid-State Electron. 1998, 42, 1061. (5) Wada, Y. Surf. Sci. 1997, 386, 265. (6) Albrecht, P.; Lyding, J. Nanotechnology 2007, 18, 125302. (7) Zikovsky, J.; Dogel, S. A.; Haider, A. B.; DiLabio, G. A.; Wolkow, R. A. J. Phys. Chem. A 2007, 111, 12257. (8) Zhirnov, V. V.; Cavin, R. J.; Herr, D. J. C.; Wooldridge, T. A. IEEE Trans. Semicond. Manuf. 2002, 15, 157. (9) Kane, B. E. Nature 1998, 393, 133. (10) Ruess, F. J.; Micolich, A.; Pok, W.; Goh, K. E. J.; Hamilton, A. R.; Simmons, M. Y. Appl. Phys. Lett. 2008, 92, 052101. (11) Pok, W.; Reusch, T. C. G.; Scappucci, G.; Ruess, F. J.; Hamilton, A. R.; Simmons, M. Y. IEEE Trans. Nanotechnol. 2007, 6, 213. (12) Shen, T. C.; Wang, C.; Abeln, G. C.; Tucker, J. R.; Lyding, J. W.; Avouris, P.; Walkup, R. E. Science 1995, 268, 1590. (13) Schofield, S. R.; Curson, N. J.; Simmons, M. Y.; Rueβ, F. J.; Hallam, T.; Oberbeck, L.; Clark, R. G. Phys. ReV. Lett. 2003, 91, 136104. (14) Kouwenhoven, L.; Marcus, C.; McEuen, P.; Tarucha, S.; Westervelt, R.; Wingreen, N. Electron Transport in Quantum Dots. NATO ASI Conference Proceedings; Kouewnhoven, L. P., Schön, G., Sohn, L. L., Eds.; Kluwer: Dordrecht, 1997; pp 105-214. (15) Nabors, K.; White, J. IEEE Trans. Comput.-Aided Des. 1991, 10, 1447. (16) see Supporting Information. (17) Lindemann, S.; Ihn, T.; Bieri, S.; Heinzel, T.; Ensslin, K.; Hackenbroich, G.; Maranowski, K.; Gossard, A. Phys. ReV. B 2002, 66, 161312. (18) Ruess, F. J.; Pok, W.; Goh, K. E. J.; Hamilton, A. R.; Simmons, M. Y. Phys. ReV. B 2007, 75, 121303. (19) Yoo, M. J.; Fulton, T. A.; Hess, H. F.; Willett, R. L.; Dunkelberger, L. N.; Chichester, R. J.; Pfeiffer, L. N.; West, K. W. Science 1997, 276, 579.

NL803196F

Nano Lett., Vol. 9, No. 2, 2009