Chitosan-Based Polysaccharide-Gated Flexible Indium Tin Oxide

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Surfaces, Interfaces, and Applications

Chitosan-based Polysaccharide Gated Flexible IndiumTin-Oxide Synaptic Transistor with Learning Abilities Fei Yu, Li Qiang Zhu, Wan Tian Gao, Yang Ming Fu, Hui Xiao, Jian Tao, and Ju Mei Zhou ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.8b03274 • Publication Date (Web): 24 Apr 2018 Downloaded from http://pubs.acs.org on April 24, 2018

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ACS Applied Materials & Interfaces

Chitosan-based Polysaccharide Gated Flexible Indium-Tin-Oxide Synaptic Transistor with Learning Abilities Fei Yu1, 2, 4, Li Qiang Zhu1, 4, *, Wan Tian Gao1, 3, 4, Yang Ming Fu1, 4, Hui Xiao1, 4, Jian Tao1, 4, Ju Mei Zhou5 1) Key Laboratory of Graphene Technologies and Applications of Zhejiang Province, Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201, Zhejiang, People’s Republic of China 2) Nano Science and Technology Institute, University of Science and Technology of China, Suzhou 215123, People’s Republic of China 3) School of Material Science & Engineering, Shanghai University, Shanghai 200444, Peoples Republic of China 4) University of Chinese Academy of Sciences, Beijing 100049, Peoples Republic of China 5) Faculty of Maritime and Transportation, Ningbo University, Ningbo 315211, Zhejiang, People’s Republic of China

ABSTRACT: Recently, surrounding friendly electronic devices are attracting increasing interests. “Green” artificial synapses with learning abilities are also interesting for neuromorphic platforms. Here, solution processed chitosan-based polysaccharide electrolyte gated indium tin oxide (ITO) synaptic transistors are fabricated on PET substrate. Good transistor performances against mechanical stress are observed. Short-term synaptic plasticities are mimicked on the proposed ITO 1

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synaptic transistor. When applying pre-synaptic and post-synaptic spikes on gate electrode and drain electrode respectively, spiking timing dependent plasticity function is mimicked on the synaptic transistor. Transitions from sensory memory (SM) to short-term memory (STM) and from STM to long-term memory (LTM) are also mimicked, demonstrating a “multistore model” brain memory. Furthermore, the flexible ITO synaptic transistor can be dissolved in deionized water easily, indicating potential “green” neuromorphic platform applications.

Keywords: Electrical double layer, Flexible Device, Artificial synapse, Spike timing dependent plasticity (STDP), Learning abilities.

1. Introduction Human brain is a highly paralleled and dynamically changed neural network. There are ~1011 neurons and ~1015 synapses.1 In 1950’s, John McCarthy proposed a term “artificial intelligence (AI)” which aims to simulate human brain.2 Recently, it has attracted increasing attentions, especially after the success in “AlphaGo”. However, it should be noted that von Neumann configurations are always used to establish AI. Thus, computation module and storage unit are always separated,3 resulting in the limitations of parallel computation and high power consumption. Therefore, it is a great challenge to build artificial neural network through von Neumann configurations. In nervous system, a synapse is a key structure for a neuron to pass an electrical or chemical signal to another. It is a basic unit for brain cognitive behavior.4 Therefore, mimicking biological synaptic responses on solid-state devices is of interest to achieve AI and neuromorphic systems at hardware level. Recently, two-terminal resistive switching devices have been proposed to emulate biological 2


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synapses, including memristor, atomic switch and phase change memory, etc.5-8 Field-effect transistors (FETs) have also been proposed for artificial synapse applications,

including

nanoparticle

organic

memory

field-effect

transistor,

ion/electron hybrid synaptic transistors, ferroelectric synaptic transistors, etc.9-12 Up to date, various biological synaptic functions have been mimicked on two-terminal and three-terminal

artificial

synapses,

such

as

“learning-experience”

function,

excitatory/inhibitory postsynaptic current (EPSC/IPSC), paired-pulse facilitation (PPF), spike rate dependent plasticity (SRDP), etc.12-16 Nonvolatile changes in analogous resistances underline synaptic responses for resistive switching devices. Due to simple sandwich structure of resistive switching devices, three-dimensional electronic synapses for neuromorphic computation platforms have been reported.17 Recently, pattern recognition and sparse decoding functions were also realized on resistive switching synapse arrays.18,

19

While for FETs based artificial synapses,

channel conductance can be read out with drain bias. Signal transmission and conductance modulation can occur synchronously. Moreover, it is easier to realize dendrite synaptic integration on transistor with multi-gate structures.20 It should be noted here that complicate structures are always needed for synaptic transistors due to the inherent limitations for conventional gate dielectrics.9, 12 Ion gating by using ionic liquid and ionic gel based electrolytes enables realization of new concept devices with new functions.21,

22

In electrolyte gated

transistors (EGTs), an electric-double-layer (EDL) is always observed at electrolyte/electrode interface due to the accumulation of ions under external field. Because of the strong electrostatic modulation, the EGTs can operate at a low voltage (0), the strength of neuron connections increases, 11



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resulting in long-term potentiation (LTP). When post-synaptic spikes lead pre-synaptic spikes (∆tpost-pre 0

if

∆t post− pre < 0

(2)

A+, A－, τ+ and τ－ are estimated to be ~26.8%, ~35.8%, ~207.8 ms and ~183.5 ms, respectively. The results indicate that biological STDP behavior has been mimicked on the proposed ITO synaptic transistor successfully.47

Figure 5. (a) Schematic diagram for testing STDP behaviors. 15 pairs of pre-synaptic and post-synaptic spikes of (3.0 V, 20 ms) were applied on ITO synaptic transistor. (b) ξ as a function of ∆tpost-pre, where ξ=(WSTDP-W0)/W0. ξ values are fitted with STDP

12


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learning function. (c) EPSC responses on pre-synaptic spikes (1.0 V, 10 ms) with different spike numbers. Vds is fixed at 0.5V. (d) EPSC responses on pre-synaptic spikes with different spike amplitudes ranged from 2V to 5V. The EPSC responses demonstrate transition from STM to LTM.

In psychology, there are two forms of memory, i.e., short-term memory (STM) and long-term memory (LTM). In 1968, a “multistore model” is proposed for the memory behavior by Atkinson and Shiffrin.49 The model describes three categories of memory, i.e., sensory memory (SM), STM and LTM. The memory level can be strengthened by repeated spikes. In another word, with suitable spikes, SM can be transferred to STM and STM can be transferred to LTM. In our case, such behaviors were mimicked on the ITO synaptic transistor. Figure 5(c) illustrates EPSC responses triggered with repeated pre-synaptic spikes (1.0 V, 10 ms). Vds is fixed at 0.5V. Firstly, four pre-synaptic spikes with interval time (∆t) of ~1s are applied. It is observed that the peak EPSCs values are ~12µA and the previous spikes have no effects on the followed EPSCs. Moreover, each EPSC current decays back to a resting current of ~2µA in several hundred ms when spike ends. In “multistore model”,49 the memory window for SM is several hundred ms. In this period, the memory level will decay back to its initial level. Thus, the behaviors observed here can be deemed as SM. When pre-synaptic spikes with ∆t of 10ms are applied, there are increased EPSC values due to multi-pulse facilitations. The peak EPSC value increases from ~23µA to ~43µA for spike number increases from 5 to 50. However, EPSC current will decay back to a same resting current of ~2µA when the spikes end. Such process mimics STM behaviors. EPSC responses were also recorded by pre-synaptic spikes with different spike amplitudes, as shown in Figure 5(d). When spike amplitude is 2V, the 13



peak EPSC is ~100µA for 50 spikes and the EPSC current decays back to a resting current of ~2µA when spikes end. When spike amplitude is 3V, the peak EPSC is ~270µA for 50 spikes. Interestingly, the resting current increases to ~20µA when spikes end. When spike amplitude is 5V, the peak EPSC increases to ~340µA for 50 spikes. Moreover, the resting current increases to ~250µA when spikes end. The resting current is ~125 times of that of spikes with amplitude of 2V. The behavior closely resembles the conversion from STM to LTM. The operation mechanisms for the “multistore model” are as follows. When spike amplitude is low, EPSC response is related to the formation of EDL layer at the chitosan/channel interface. When spike amplitude is high, some protons will penetrate into ITO channel layer.35 Thus, electrochemical doping occurs in ITO channel, resulting in an increased channel conductivity, which results in a non-volatile long-term memory. Interestingly, since solution processed chitosan-based polysaccharide electrolyte acts as gate dielectric, the proposed ITO synaptic transistor can find potential applications in “green” neuromorphic platforms. Here, the proposed ITO synaptic transistors were soaked in deionized (DI) water at room temperature. As shown in Figure 6(a), there are transistor arrays on PET substrate. After soaking in DI water, the devices get blurry and vanished with the increased soaking time (as shown in Figure 6(b-d)). When soaking time is 15min, there are no devices on the PET substrate.

14


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Figure 6. Biodegradable ITO synaptic transistors. (a) Fabricated transparent flexible devices. (b)-(d) Decomposition of devices after soaking in deionized water for 1min, 5min, 15min, respectively.

4. Conclusion In summary, solution processed chitosan-based polysaccharide electrolyte gated indium-tin-oxide (ITO) synaptic transistor were fabricated on PET substrate. Good transistor performances against mechanical stress were observed. Short-term synaptic plasticities were mimicked on the proposed ITO synaptic transistor. When applying pre-synaptic and post-synaptic spikes, STDP learning rule was mimicked on the synaptic transistor. Moreover, the ITO synaptic transistor demonstrates a “multistore model” brain memory, i.e., transitions from SM to STM and from STM to LTM. Furthermore, the flexible ITO synaptic transistor can be dissolved in deionized water easily, indicating potential applications in “green” neuromorphic platform.

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AUTHOR INFORMATION

Corresponding Author *E-mail address: [email protected]. ORCID Li Qiang Zhu: 0000-0002-8249-3421 Notes The authors declare no competing financial interest.

ACKNOLEDGEMENTS

This work was supported by Zhejiang Provincial Natural Science Foundation of China (LR18F040002), Ningbo Science and Technology Innovation Team (2016B10005), National Natural Science Foundation of China (11474293, 61604085), Youth Innovation Promotion Association CAS (2014259), Key Research Program of Frontier Sciences, Chinese Academy of Sciences (QYZDB-SSW-JSC047) and CAS Interdisciplinary Innovation Team.

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Chitosan-Based Polysaccharide-Gated Flexible Indium Tin Oxide

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