Deionization of Dopants in Silicon Nanofilms Even with Donor

Jan 7, 2016 - We report the deionization or finite ionization energy of dopants in silicon (Si) nanofilms with dopant concentration (ND) of greater th...
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Deionization of Dopants in Silicon Nanofilms Even with Donor Concentration of Greater than 1019 cm−3 Takahisa Tanaka,† Yuya Kurosawa,‡ Naotoshi Kadotani,‡ Tsunaki Takahashi,† Shunri Oda,‡ and Ken Uchida*,† †

Department of Electronics and Electrical Engineering, Faculty of Science and Technology, Keio University, Hiyoshi, Yokohama 223-8522, Japan ‡ Department of Physical Electronics and Quantum Nanoelectronics Research Center, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan S Supporting Information *

ABSTRACT: Understanding the dopant properties in heavily doped nanoscale semiconductors is essential to design nanoscale devices. We report the deionization or finite ionization energy of dopants in silicon (Si) nanofilms with dopant concentration (ND) of greater than 1019 cm−3, which is in contrast to the zero ionization energy (ED) in bulk Si at the same ND. From the comparison of experimentally observed and theoretically calculated ED, we attribute the deionization to the suppression of metal−insulator transition in highly doped nanoscale semiconductors in addition to the quantum confinement and the dielectric mismatch, which greatly increase ED in low-doped nanoscale semiconductors. Thus, for nanoscale transistors, ND should be higher than that estimated from bulk Si dopant properties in order to reduce their resistivity by the metal−insulator transition. KEYWORDS: Ionization energy, silicon, transistor, phosphorus, nanostructure, metal−insulator transition

S

transport properties7−9 because of the difficulties in realizing Si/SiO2 superlattices. For example, increase in ED has been observed and evaluated in resistivity measurement7 and singleelectron tunneling spectroscopy8,9 in Si nanoscale transistors. These experimental observations and theoretical calculations reveal that in addition to the quantum confinement dielectric confinement plays an important role in matching the observed large ED increase. However, the comparison between the experimental and theoretical data has remained insufficient partly because of the difficulty in accurate experimental evaluation of ED in nanoscale semiconductors. Because of the large surface-to-volume ratio of nanoscale structures, the ED increase is strongly affected by charged substances around nanoscale semiconductors and electric fields at the surfaces. In most cases, Si nanostructures are directly exposed to the outer atmosphere and have a nonuniform surface structure; thus, the electrical properties are greatly modified by the extrinsic effects, which make accurate evaluation of ED extremely hard. Moreover, as studied in bulk semiconductors, ED decreases in more highly doped semiconductors due to conduction-band tailing and formation of impurity bands.17−24 Therefore, in heavily doped nanoscale

hallow impurity doping has been an indispensable technology to control the type and concentrations of carriers in bulk semiconductors and will be a key technology in nanoscale semiconductors. Optical and electronic devices realized using nanoscale semiconductors with critical dimensions of less than 10 nm can potentially offer better properties than their bulk counterparts. They can provide better luminescence efficiency as well as photosensitivity for optical applications,1,2 lower power consumption, and larger scale integration for electronic device applications3−5 and could provide new functionalities for unexplored applications. To accurately control the carrier concentrations in nanoscale devices, the dopant properties in nanoscale semiconductors need to be understood. Thus, the dopant properties have been investigated by a number of researchers. The experimental research efforts6−9 show that ionization energy ED in nanoscale semiconductors should be considerably increased. These experimental observations have been qualitatively confirmed by theoretical calculation in quantum dots, nanowires, and quantum wells of silicon (Si) and III−V semiconductors by effective mass, tight-binding, and first-principle approaches.10−16 To elucidate the present status of understanding ED, more explanations on the experimental endeavor will follow. The increase in ED in III−V semiconductors6 has been clearly demonstrated by optical measurements of superlattices, whereas in Si, it has been mainly evaluated using the electrical © XXXX American Chemical Society

Received: October 30, 2015 Revised: January 5, 2016

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source/drain regions were kept thick to eliminate parasitic resistance. The fabrication processes are described as follows: the implantation of phosphorus ions and high-temperature activation annealing at 1000 °C for 30 min were performed when SOI thickness TSOI was relatively thick (approximately 100 nm) to avoid serious and unrecoverable damages during the ion implantation. The SOI films were then thinned down by repeating both thermal oxidation and thermal-oxide stripping using hydrofluoric acid. By applying the localoxidation-of-Si process, the channel region was more aggressively scaled than the source/drain regions. The detail of the process flow, including the timing of ion implantations, can be found in ref 26. The SOI channels were finally thinned to approximately 10 nm scales. Because of the condensation of phosphorus within the SOI films, which results from the accumulation of phosphorus at the SiO2/Si interfaces during the oxidation process,27,28 ND tended to be high. A crosssectional photograph taken by a transmission electron microscope is shown in Figure 1b. The successful fabrication of a flat, smooth SOI channel with TSOI of 2.2 nm was confirmed. To obtain ED, we reasonably assumed that the electron concentration ne is the same as the ionized impurity concentration ND+. The temperature dependence of electron concentration ne obtained from Hall-effect measurements is often employed. However, ne obtained from Hall-effect measurements is a function of the Hall factor, which depends on the carrier scattering mechanisms that is impossible to be explicitly determined. Therefore, in this work, ne was evaluated using the capacitance−voltage (C−V) characteristics. By integrating the C−V curves, the gate-voltage dependence of ne was obtained. The schematic diagrams of the conductionband profile in a SOI channel are shown in Figure 2. In the

semiconductors the situation is quite complicated. We have competing factors. On one hand, quantum confinement and dielectric mismatch increase ED. On the other hand, heavy doping lowers ED. Thus, the ED increase in nanoscale Si has been investigated mainly using the isolated dopant in lightly doped Si for simplicity. Unfortunately, however, the electrical properties of nanoscale Si are more sensitive to external environment at lighter doping concentrations. Therefore, to fully understand ED in nanoscale semiconductors, two points need to be considered: (1) the increase in ED by quantum confinement and dielectric mismatch should be evaluated in nanoscale semiconductors with fewer ambiguities at the surfaces and (2) the dependence of donor concentration ND on ED in nanoscale semiconductors should be obtained. The objectives of the present study are to provide solid experimental data to overcome the above two difficulties and to build an accurate model of ED in nanoscale semiconductors with a wide range of ND. In this work, ED in nanoscale Si-on-insulator (SOI) fieldeffect transistors (FETs) was evaluated. The SOI channel was surrounded by Si dioxide, which has an excellent interface property with Si. In addition, the surface of the SOI channel was covered with heavily doped poly Si, which can shield the effect of charged substances coming from the outer atmosphere. The carrier concentration at flat-band condition, namely, the condition of zero electric field at the surface of SOI, was utilized to determine ED. In this manner, the ambiguities of nanoscale semiconductors in the evaluation of ED were carefully eliminated. The extracted ED value was compared with the calculated ED value for an isolated donor in nanoscale Si channels. In addition to the quantum confinement and dielectric mismatch, which have been discussed in nanoscale semiconductors, we demonstrated that the metal−insulator transition observed in highly doped semiconductors is greatly suppressed in nanoscale semiconductors. An empirical model to explain the ND dependence on ED in heavily doped nanoscale Si films is proposed. Then, the proposed empirical model was used to estimate the performance of future advanced FETs, namely, fin-type FETs (FinFETs), which utilize nanoscale Si films as channels. In the estimation, numerical simulation of quasi-ballistic transport was adopted. Figure 1a shows the schematic of the SOI FETs fabricated and evaluated in this work. The n+ source and the drain regions were heavily doped with phosphorus, and the channel region was lightly doped with the same dopant. Therefore, the fabricated transistors were junction-less FETs.25 The channel region was recessed to realize nanoscale Si channel, whereas the

Figure 2. Conduction-band edge of the SOI FET at the (left) flat band, (center) accumulation mode, and (right) depletion mode. The black circles and short lines represent the electrons and donor states, respectively. In the flat-band mode, the number of electrons ne corresponds to the number of ionized impurities ND+.

accumulation/depletion mode of the SOI FETs, ne is greater/ lesser than ND+ because the electrons are induced/depleted by the gate voltage. Under these conditions, ED can hardly be determined because ne is not equal to ND+. On the other hand, ne coincides with ND+ under the flat-band condition. Therefore, the temperature dependence of ne under the flat-band condition was employed to obtain ED. In addition to this feature, almost no electric field is present in the channel under the flat-band condition due to the thick buried oxide (BOX) layer and appropriate gate voltage. Therefore, the band profile is uniform for each donor, and ne is equivalent to ND+ regardless of the position in the channel. This condition was difficult to realize in previously employed nanostructures such as bare (i.e., no-gate-electrode) nanowires or nanoscale transistors with a 10 nm scale channel length in which the

Figure 1. (a) Schematic diagram of the SOI FET. To reduce the parasitic resistance, only the channel region was thinned. (b) Crosssectional image of the SOI FET. Each layer corresponds to the gate oxide, SOI, and BOX from above. The scale bars represent a 10 nm length. B

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Figure 3. (a) Temperature dependence of the C−V characteristics of the SOI FET with TSOI = 2.2 nm. (b) Schematic diagram of the determination of EF. EF is determined to satisfy ND+ = ne. (c) Temperature dependence of ne. The experimental ne’s obtained from the C−V characteristics are indicated by symbols. The solid lines represent the calculated data fitted by changing ND and ED.

Figure 4. (a) ND dependence of ED. The red circles represent the obtained ED in SOI FETs. ED’s measured in bulk Si by previous works are also shown as open symbols.18−21 The solid line represents the fitting curve of ED for the bulk Si with Nref = 1 × 1018 cm−3. (b) Schematic diagram of potential fluctuations by phosphorus in the (left) bulk Si and (right) SOI. (c) Sheet carrier concentration NS dependence of mobility μeff in SOI FETs with TSOI = 3.2, 5.2, and 5.8 nm. Red circles represent μeff at the flat band conditions. (d) Comparison of μeff between heavily doped bulk Si and SOI FETs. The solid line represents the ND+ dependence of μeff in bulk Si.30

position-dependent local electric field causes a difference between ne and ND+. The measured C−V characteristics for the SOI FETs with TSOI of 2.2 nm are shown in Figure 3a. From these C−V characteristics, ne was determined by integrating the C−V curves from negative infinity to the flat-band voltage. The flatband voltage of the SOI FETs was determined on the basis of the flat-band capacitance of the SOI channel, which is expressed as SC C FB =

2κSi TSOI

certain ND, ED, and temperature T, ne can be calculated using the two-dimensional (2D) density of states with parabolic effective mass and Fermi energy EF. At each T, EF was chosen to satisfy ne = ND+, which is expressed as ND+

⎡ ⎢ 1 = ND⎢ ⎢ 1 + 0.5 exp − EC − ED − EF kBT ⎣

(

)

⎤ ⎥ ⎥ ⎥ ⎦

(2)

where Ec is the minimum conduction band corresponding to the energy of the lowest subband in an SOI film, as shown in Figure 3b. The experimentally obtained temperature dependence of ne was fitted to the calculated ne by making ND and ED as the fitting parameters. Figure 3c shows experimental ne and the fitting curves at temperatures ranging from 160 to 300 K. Excellent fit to the experimental values for a wide range of temperature can be observed, confirming the validity of the extraction method.

(1)

where κSi is the dielectric constant of Si. This flat-band capacitance is obtained from ref 29 with the assumptions of no electric field in the BOX and symmetric electron distribution in the SOI channel. The detailed derivation of eq 1 is presented in the Supporting Information. ED and ND were determined from the experimental temperature dependence of ne in the following manner. At C

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Figure 5. (a) Position dependence of ED0 of the SOI FETs at TSOI = 4 nm. The lines are for eye guidance. (b) Calculated thickness dependence of ED0 in the (100) and (110) surfaces. Calculations are performed for valleys that correspond to the conduction-band edge. Therefore, two-fold and four-fold degenerated valleys are calculated for the (100) and (110) surfaces, respectively. (c) TSOI dependence of Nref. The red circles represent the results from the comparison between the experimental data in Figure 4a and calculated data in panel b. The solid and dashed lines represent the empirically fitted curve and bulk Nref value, respectively. (d) ND dependence of ED for SOI and bulk Si. For several TSOI thicknesses, the painted regions are separated according to the calculated ED by eqs 3 and 4 and Figure panel b. For clarity of the figure, the selected experimental ED’s at TSOI = 2.2, 3.2, 5.2, and 13.0 nm are shown. Reasonable agreement between the experimental and calculated ED’s can be observed.

impurity band. As a result, ED approaches zero at high donor concentrations. Figure 4b shows the schematic diagram of phosphorus atoms in the bulk Si and the SOI. The phosphorus atoms are shown with a certain width corresponding to their potential fluctuation spreading whose overlaps caused the metal−insulator transition. In the bulk Si, the phosphorus atoms three-dimensionally overlap. On the other hand, the overlaps in the confined direction are limited in the SOI FETs. The suppression of overlapping in each potential fluctuations results in the suppression of the conduction-band tailing and formation of the impurity band. As a result, the metal−insulator transition is suppressed in nanoscale SOI FETs. As discussed in our previous work, reduction of overall potential fluctuation due to effectively less ionized impurities around carriers in nanoscale SOI films causes the mobility enhancement in heavily doped SOI FETs. 26 Figure 4c shows sheet electron concentration dependences of electron mobility in SOI FETs. The mobility at the flat-band condition in SOI FETs is compared with mobility in bulk Si.30 The enhancement of mobility in thin SOI FETs with TSOI ranging from 3 to 6 nm is observed as shown in Figure 4d, which is consistent with the suppression of the metal−insulator transition. The suppression of the metal−insulator transition leads to the increase in observed ED at high doping concentration from 0.3 meV, which is estimated from the bulk Nref, to 20 meV. Therefore, the metal−insulator transition (or degenerate semiconductors) is clearly shown to be more difficult to realize in thinner nanoscale semiconductor films. The effect of the suppressed metal−insulator transition in SOI FETs is represented as the change in Nref as follows. First, the Schrödinger equation for SOI films with and without an ionized phosphorus atom, where the quantum confinement and dielectric mismatch were taken into account, was solved. Si has

The obtained ND and ED are plotted and shown in Figure 4a, where ED’s measured for bulk Si18−21 are also shown. We should note that ED’s for various ND’s in bulk Si can be represented as7,24 ED =

⎡ ⎢1 + ⎣

E D0

2⎤

( ) ⎥⎦ ND Nref

(3)

0

where ED is the ionization energy of an isolated donor. Fitting parameter Nref, where ED is half of ED0, is used to describe the reduction in ED0 by the metal−insulator transition, which is observed in degenerate semiconductors. Nref was set to 1 × 1018 cm−3, which was different from the original value of Nref = 3 × 1018 cm−3 in ref 24, because better fitting to previous experimental reports can be obtained. Figure 4a clearly shows that ED in nanoscale SOI films deviates from the bulk values to the upper side. We considered that this observed increase in ED originated from the increase in the ionization energy of isolated donor ED0. On the basis of the effective mass approximation, ED0, which considers the quantum confinement and dielectric mismatch, was calculated to be approximately 140 meV at TSOI = 2.2 nm. Using eq 3 with ED0 of 140 meV, Nref of 1 × 1018 cm−3, and ND of 2.2 × 1019 cm−3, ED in the SOI FETs was estimated to be approximately 0.3 meV. On the other hand, ED in the present nanoscale SOI film with TSOI of 2.2 nm and ND of 2.2 × 1019 cm−3 was experimentally evaluated to be 20 meV, which was much higher than the value estimated from eq 3. We considered that this discrepancy is due to the difference between the three-dimensional (3D) bulk Si and the 2D Si nanofilms with regard to the metal−insulator transition. As widely known, the overlaps of potential fluctuations by donor atoms cause conduction-band tailing and formation of an D

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Figure 6. (a) Schematic diagrams of the calculated FinFETs. A trigate structure and an infinitely thick BOX layer are assumed. For clarity of the schematic diagram, the gate oxide that covers the Si fin is omitted. Along the transport direction of the FinFET, the size of the Si fin is constant. (b) Calculated ID−VG characteristic with (red lines and open filled circles) and without (black lines and open squares) ED correction. The arrows and ratios indicate the decreased ratio between the ID−VG characteristics with and without ED correction. (c) Z-position dependence of the conductionband edge (blue line) EC and (green line) EQF on the ED correction and activation ratio in the extension regions with and without the ED correction (black and red lines, respectively). The dotted lines separate the drain, extension, channel, and source regions. (d) ND in the extension-region dependence ID with (red line and filled circles) and without (black line and open squares) the ED correction. ED’s with (blue dashed line and filled triangles) and without (blue dashed line and open triangles) correction are also shown. The ratios indicate the decreased ratio between the ID−VG characteristic with and without the ED correction.

employed without incurring serious error in ED0. The calculated ED0 for the (100) and (110) surfaces is shown in Figure 5b. The difference between the (100) and (110) surfaces originated from the difference in the effective masses in the confinement direction. For the (100) surface, the experimental data were compared with the calculated ED0 using Nref as a fitting parameter. The TSOI dependence of Nref is shown in Figure 5c, where empirical model describing the TSOI dependence of Nref is also shown. This empirical model, which successfully depicts the TSOI dependence of Nref, is expressed as

six conduction-band valleys, and this degeneracy is lifted by quantum confinement. Because electrons captured by donors are favorably excited to the lowest energy of the conduction band, the calculations were performed for the lowest energy valleys; two-fold and four-fold valleys are considered for the (100) and (110) surfaces, respectively. The effective mass approximation with transverse electron effective mass mt of 0.19m0 and longitudinal electron effective mass ml of 0.916m0 were employed, where m0 is the rest mass of an electron in vacuum. The Schrödinger equation was solved in the cylindrical coordinate by setting the longitudinal axis as the confinement direction. The effective mass of the polar axis was averaged as 2m1m2/(m1 + m2),31 where m1 and m2 are the effective masses of the two in-plane axes in the rectangular coordinate system. The shape of the Coulomb potential was obtained from ref 32. The effect of the dielectric mismatch is considered as image charges by assuming infinitely thick SiO2. ED0 was determined by the difference in the ground state energy with and without the ionized phosphorus atom. The obtained ED was further corrected by valley-orbit splitting.33 The position dependence of ionized phosphorus for the (100) surface is shown in Figure 5a. The electron-trapping potentials by ionized impurity ions are narrowed by SiO2 potential at the Si/SiO2 interfaces. As a result, ED0, which is the difference between the conductive and the trapped state, is decreased at the positions closer to the Si/ SiO2 interfaces. Such decrease of ED0 is also theoretically studied in bulk Si/SiO2 interface.34 Even with the position dependence of ED0 in the 75% region of the SOI channel, the relative difference of ED0 compared with the value at the center of the SOI films is below 6%. Therefore, the assumption that ionized phosphorus locates at the center of the SOI films was

Nref = 1 × 1018cm−3 +

0.09 3 TSOI

(4)

As TSOI is reduced, Nref increases, as shown in Figure 5c. This tendency qualitatively agrees with the above-discussed suppression of the metal−insulator transition in Si nanofilms. Figure 5d clearly shows that the increase not only in ED0 but also in Nref contributes to the determination of ED in heavily doped nanoscale SOI films. By using this empirical model, the effect of increased ED on drain current ID in nanoscale FinFETs, whose channel direction is [110] and side surface orientation is (110), was estimated. The drain-current versus gate voltage (ID−VG) characteristics were obtained by the self-consistently solving 2D Schrödinger, one-dimensional (1D) Boltzmann transport, and 3D Poisson equations in the framework of the deterministic approach.35−37 The details of the calculations are described in the Supporting Information. Figure 6a shows the schematic structure of the calculated FinFET whose fin height and width are 12 and 4 nm, respectively. Figure 5b shows that the increase in ED0 in a 12 nm thick SOI film (approximately 15 meV) is negligibly small E

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compared with that in a 4 nm thick SOI film (approximately 70 meV). In addition, Figure 4a shows that experimental ED in a 13 nm-thick SOI film is almost the same as that in the bulk Si indicated by the solid line. These data imply that the quantum confinement and the dielectric mismatch in the direction along the Si fin height have a negligible effect on ID. Therefore, the increase in ED in the FinFETs was considered only in one dimension: width direction. The lengths of the source/drain, extension, and channel were 8, 7, and 10 nm in the channel direction, respectively. The material of the gate oxide was SiO2, and its thickness was 0.8 nm. ND in the source/drain regions was 1 × 1020 cm−3, resulting in source/drain ND+ of 3.4 × 1019 cm−3 under equilibrium condition; a drain-to-source voltage V DS of 0 V. N D + in the extension regions under a nonequilibrium condition was calculated from the quasiFermi energy EQF. Figure 6b shows the comparison of the ID−VG characteristics in the FinFET with the proposed ED correction and the conventional bulk ED. The ID−VG characteristic with the conventional bulk ED corresponds to the ideal case, where the phosphorus donors in the FinFET have the same ED and Nref as those in bulk Si. On the other hand, the characteristic with correction corresponds to the case where ED is corrected using ED0 in Figure 5b and Nref in eq 4. As shown in Figure 6b, ID is reduced by the effects of quantum confinement, dielectric mismatch, and suppressed metal−insulator transition. Figure 6c shows the profiles of the conduction-band edge, EQF, and activation ratio of the phosphorus donors in the extension regions. The correction of ED causes approximately 40% drop in the activation ratio. To minimize the activation ratio drop, ND in the extension region should be increased. By employing sufficiently larger ND, ED is closer to zero even in the FinFET, as shown in Figure 6d. ID’s of the conventional bulk, proposed, and corrected ED’s are almost the same at high ND (above 2 × 1019 cm−3). Thus, to reduce the parasitic resistance, employing ND higher than 2 × 1019 cm−3 in the extension regions is important. In summary, ED in heavily doped SOI FETs was evaluated by removing the uncertainties in the potential as well as the electric field at the surface of nanoscale semiconductors. On the basis of the ED evaluation, this work reports the deionization of dopants in Si nanofilms with ND of greater than 1019 cm−3, which contradicts zero ED in bulk Si with the same ND. By comparing the measured ED with the calculated ED, we demonstrated that the suppressions of the metal−insulator transition are important to quantitatively understand the increase in ED in Si nanofilms. By considering the suppressions, we estimated ED in SOI FETs and FinFETs with arbitrary ND using the empirical model. The proposed empirical model was then used to estimate the performance of future FinFETs. The on-current of a FinFET with a 4 nm thick Si film was reduced by 9% due to the increase in ED. To overcome this decrease in the on-current, ND higher than 2 × 1019 cm−3 in the extension regions is required. This estimation indicates that extension doping should be much higher than we have considered for future nanoscale devices to overcome the deionization of impurities caused by the quantum-mechanical effects, dielectric mismatch, and suppression of metal−insulator transition.

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ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.5b04406. The derivation of the flat-band capacitance of SOI channels and the details of calculations of ID−VG characteristics of Fin FETs. (PDF)

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AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS The authors thank Professor N. Sano for fruitful discussions. This work was supported by Grant-in-Aid for JSPS Fellows Grant 14J05405 and Grant-in-Aid for Scientific Research B Grant 15H03997.

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