Device Noise Reduction for Silicon Nanowire Field-Effect-Transistor

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Device noise reduction for silicon nanowire field-effecttransistor based sensors by using a Schottky junction gate Xi Chen, Si Chen, Qitao Hu, Shi-Li Zhang, Paul M Solomon, and Zhen Zhang ACS Sens., Just Accepted Manuscript • DOI: 10.1021/acssensors.8b01394 • Publication Date (Web): 11 Jan 2019 Downloaded from http://pubs.acs.org on January 14, 2019

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Device noise reduction for silicon nanowire field-effect-transistor based sensors by using a Schottky junction gate Xi Chen †, Si Chen †, Qitao Hu †, Shi-Li Zhang †, Paul Solomon*‡, and Zhen Zhang*† Division of Solid-State Electronics, Department of Engineering Sciences, The Ångström Laboratory, Uppsala University, P.O. Box 534, SE-751 21 Uppsala, Sweden. ‡ IBM T. J. Watson Research Center, Yorktown Heights, New York 10598, USA. †

Keywords: Noise reduction, schottky junction gate, silicon nanowire, field-effect transistor, low frequency noise, ion sensor

ABSTRACT: The sensitivity of metal-oxide-semiconductor field-effect transistor (MOSFET) based nanoscale sensors is ultimately limited by noise induced by carrier trapping/detrapping processes at the gate oxide/semiconductor interfaces. We have designed a Schottky junction gated silicon nanowire field-effect transistor (SiNW-SJGFET) sensor, where the Schottky junction replaces the noisy oxide/semiconductor interface. Our sensor exhibits significantly reduced device noise, 2.1×10-9 V2µm2/Hz at 1 Hz, compared to reference devices with the oxide/semiconductor interface operated at both inversion and depletion modes. Further improvement can be anticipated by wrapping the nanowire by such a Schottky junction thereby eliminating all oxide/semiconductor interfaces. Hence, a combination of the low-noise SiNW-SJGFET device with a sensing surface of the Nernstian response limit holds promises for future high signal-to-noise ratio sensor applications.

In the past decades, silicon nanowire (SiNW) field-effect transistors (FETs) have attracted great attention due to their high sensitivity towards chemical and biological species. A large variety of potential applications, such as pH measurement,1–4 chemical sensing,5–7 label-free biosensing,8–12 and gas sensing,13,14 have been demonstrated. In a SiNWFET sensor, the gate surface is functionalized with receptors that selectively bind to targets of interest, leading to a change in surface potential ∆φs and consequently a shift of the threshold voltage (∆VTH) of the SiNWFET. This ∆VTH is then transduced by the SiNWFET to a change in drain-to-source current (∆IDS). ∆VTH represents the original sensing signal and is primarily determined by the surface properties of the sensing layer on gate terminal. Extensive studies have been done to optimize the sensing surface. And high sensing signal close to the Nernstian limit,15 60 mV/dec (analyte concentration change) at room temperature, have been reported in the literature.4, 16–18 Since the lower limit of detection of the SiNWFET sensor is set by its signal-to-noise ratio (SNR) while the original sensing signal can be close to the upper limit, the noise performance of the SiNWFET is therefore a very critical parameter in sensing practice. The noise issue is indeed becoming increasingly prominent as the detections have been pushed into extremely low concentration ranges, even targeting for single charge events.19 Downscaling SiNWFETs, aiming to increase the surface-to-volume ratio for extremely low concentration detections, inevitably leads to increase of the noise intensity dramatically.20,21 For a SiNWFET sensor operating in electrolytes, the noise has mainly three components, i.e., the bulk electrolyte noise, the solid-liquid interface noise, and the SiNWFET intrinsic device noise22 with the latter two being dominant. Our previous study23 points out

that the solid-liquid interface noise can be reduced by decreasing the number of binding sites with large kinetic barriers. In this study we aim to reduce SiNWFET intrinsic device noise by replacing oxide/semiconductor interfaces with metal/semiconductor Schottky junctions. It is well understood that noise at low frequencies (LFN) in MOSFETs, having a 1/f like spectral density, is generated by fluctuations in the number of carriers due to random trapping and detrapping of the carriers to the traps in the vicinity of the interface between the gate oxide and the channel.20, 24 The noise intensity strongly depends on the trap density near the gate oxide/silicon interface and is inversely proportional to the gate area of the device. Efforts have been pursued to reduce LFN of the SiNWFET by optimizing the configuration of SiNWs25, the liquid and back gate bias conditions26,27 and by using a depletion-mode SiNWFET (DeMOSFET)20,28 where the conduction channel is pushed away from the top channel interface by insertion of a depletion layer. The LFN of DeMOSFETs can be further optimized with both top and bottom channel surfaces biased into depletion thereby distancing the conduction channel from both “noisy” interfaces.20 Minimum noise can be achieved on the DeMOSFET with a buried bulk conduction channel and/or with strong inversion at both interfaces in order to shield from the interfacial noise.20, 27 However, it can be challenging to achieve such bias conditions without compromising transducing efficiency in practical applications. Our Schottky junction gated SiNWFET (SiNW-SJGFET) approach uses a metal-silicon Schottky barrier to replace the noisy oxide/silicon interface. This emulates p-n junction gate FETs (JFETs) which are widely used in low noise amplifiers.30 The design of the SJGFET is much like that of the JFET where

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the channel is pinched off by depletion layers originating from the gate Schottky junctions (See, for example, Figure S1). In this work, we design and fabricate the SJGFETs with a fully CMOS-compatible process, along with DeMOSFETs and inversion-mode SiNWFETs (InMOSFET) as the control groups, and demonstrate that the SJGFETs can indeed address the aforementioned intrinsic device noise issue. Thus, combining our low noise SiNW-SJGFET device with a close to Nernstian limit sensing surface can be a promising solution for future high signal/noise sensor applications. In addition, this new device concept is not limited to the nanowire geometry and can easily be adapted to FET fabrication with other semiconductors than silicon. EXPERIMENTAL SECTION Device fabrication. The SJGFETs were fabricated on 100mm silicon-on-insulator (SOI) wafers by means of standard silicon process technology. The SOI wafers comprised a 200nm thick lightly p-type doped silicon layer on top of a 375-nm thick buried oxide (BOX). The top silicon layer was thinned down from 200 to 120 nm via thermal oxidation and an arsenic (As) implantation was employed to convert the top silicon to n-type with an average concentration for the channel doping concentration (ND) of 1.2×1017 /cm3 as confirmed by resistivity measurement. A second As implantation was performed to form the n+-doped source and drain terminals (S/D) with the channel region being protected by photoresist during the implantation. The SJGFET structure with SiNW and S/D was defined by electron beam lithography (EBL) and reactive ion etching. The width of the SiNWs after etching varied from 90 to 150 nm while the length was fixed at 2 µm. A 15-nm thick Pt layer was evaporated and patterned on top of both the center of the SiNW channel and the heavily doped n+S/D regions via lift-off. Platinum silicide (PtSi) was subsequently formed by rapid thermal processing (RTP) at 500 °C for 30 s in N2. The gate length (LG) was 900 nm and a lateral distance (d) of 150 nm from the edges of the PtSi gate to the n+-S/D was designed to avoid gate to S/D short circuiting (see Figure S2(a)). A second lift-off process was used to pattern a 100 nm thick Pt to contact the gate and n+S/D PtSi with a 10 nm Ti layer as an adhesion layer and diffusion barrier, followed by forming gas annealing (FGA) at 400 °C for 30 min in forming gas (5% H2 diluted in N2). For comparison, InMOSFETs and DeMOSFETs were also fabricated with similar device structures, using a 5-nm HfO2 grown by means of atomic layer deposition (ALD) as the gate oxide. The SiNW channel was p-type for the InMOSFETs with the doping level (NA) defined by the starting top silicon layer of the SOI wafer (see Figure S2(a)). For the DeMOSFETs, the SiNW channel was n-type with the same ND as for the SJGFET. Schematic representations of the fabrication processes for the three devices can be found in Figure S2(b). Electrical characterization. Transfer (IDS vs. VG (gate voltage)) and output (IDS vs. VDS (drain to source voltage)) characteristics were measured at room temperature on a probestation using a Keysight B1500A precision semiconductor parameter analyzer. The power spectral density (PSD) of IDS was characterized using a Keysight E4727A advanced lowfrequency noise analyzer, with an f range from 1 to 1M Hz at different IDS. For measurement at each IDS, VDS was biased at 1 V, and VG bias was determined by the E4727A based on the

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transfer characteristic of the SJGFET and IDS set value. In the setup for pH measurement, an extended gate electrode was employed.31 A 10-nm thick HfO2 layer, grown by ALD, acted as the pH sensitive layer on the extended gate. For Na+ sensing, the extended gate was functionalized by membrane containing a commercial Na ionophore. Detailed fabrication process of the membrane can be found in published work.16 A polydimethylsiloxane (PDMS) container was placed on top of the electrode for the solution, in which an AgCl/Ag reference electrode (RE) immersed into was set at a potential denoted as VRE. The pH values and Na+ concentrations are altered manually by the titration of hydrogen chloride (HCl) and sodium chloride (NaCl) into the solution respectively. IDS variations of the SJGFET at a constant VRE=-0.1 V were monitored in real time when the analyte concentration was altered. RESULTS AND DISCUSSION A schematic three-dimensional bird-view of an SJGFET is depicted in Figure 1(a). The S/D are heavily n-doped (n+) while the SiNW channel is modestly n-doped. The Schottky junction gate is formed with PtSi in the middle section on the SiNW. A more detailed schematic representation of the SJGFET including annotations of all critical design parameters can be found in Figure S2(a). VTH of the SJGFET is defined as the depletion layer expands over the entire n-type silicon thickness, even at the source end of the SiNW channel.30 Assuming a flat-band condition at the bottom interface, VTH of the SJGFET can be calculated as:30 𝑉TH = 𝑉bi ―

𝑞𝑁D𝑡2Si 2𝜀Si

,

(1)

where Vbi is the PtSi/silicon junction built-in potential, tSi the channel thickness, and εSi the dielectric constant of silicon. The leakage current of the Schottky junction gate, IGS, can be described by the thermionic emission theory:30 𝐼GS/𝐴 = 𝐴 ∗ 𝑇2exp ( ―

𝑞∅B 𝑘𝑇

)[exp

𝑞𝑉G

( ) ―1], 𝑘𝑇

(2)

where A is the junction area, A* the effective Richardson constant, and ΦB the barrier height of the Schottky junction. It is essential that VTH of the SJGFET is lower than the turn-on voltage of the junction gate to avoid excessive IGS during operation. Therefore, a high ND and a large tSi of the SiNW and a high ΦB of the junction are favorable for achieving low IGS according to Eqs 1 and 2. In addition to its good process compatibility with standard CMOS technology,32 PtSi was selected as the gate metal material in this work for its high ΦB to the n-Si channel so as to avoid excessive gate leakage.33 For practical considerations, our design also requires that VTH of the SJGFET does not exceed -1 V in order to avoid excessive parasitic current between S/D pads and electrolytes when the SJGFET is operating in electrolytes. After extensive theoretical calculations with partial simulation results by Silvaco depicted in Figure S3, we limit our VTH to 0.2 V so as to ensure that IDS of the SJGFET is at least two orders of magnitude higher than IGS. In our first optimized device fabrication, we have a design range of VTH from -1 to 0.2 V, meaning that ND should be controlled within 1.0×1017 and 3.2×1017 /cm3 for tsi = 80 nm, for example. A top-view scanning electron micrograph (TVSEM) image of an SJGFET after the PtSi formation is shown in Figure 1(b) and the corresponding SJGFET after gate metallization is seen

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Figure 1. (a) A three-dimensional sketch of an SJGFET. (b) Top-view SEM micrograph of an SJGFET after the formation of PtSi in the middle of the SiNW channel (brighter region). (c) XTEM image of the SiNW channel along the dash line as indicated in (b) together with the platinum and silicon profiles analyzed by EDX. (d) Top-view optical image of the SJGFET array chip, before the top gate is formed. The long S/D leads are designed for connection between the SJGFETs and contact pads at the edges of the chip. in Figure S4(a). A cross-sectional transmission electron microscopy (XTEM) image is taken within the gate section along the dash line as indicated in Figure 1(b). As shown in Figure 1(c), the PtSi is formed only on the top surface of the SiNW, as further confirmed by the energy dispersive spectroscopy (EDX) elemental profiles (Pt and Si). The PtSi growth on the SiNW leads to a slight volume expansion.32 The thickness of the PtSi and the SiNW channel underneath measured from the XTEM image is about 40 nm and 80 nm, respectively. A lateral erosion of the BOX under the SiNW by 20 nm is also visible, as multiple hydrofluoric acid (HF) etching steps were applied during the fabrication of the SJGFETs. Transfer characteristics, i.e., IDS vs. VG, of an SJGFET, a DeMOSFET and an InMOSFET are depicted in Figure 2(a). The SJGFET gives an off-state current (Ioff) of about 0.1 pA level and an on- (Ion) to off-current ratio (Ion/Ioff) exceeding 106. More importantly, a near ideal subthreshold slope (SS) of 60.5 mV/dec, is achieved. This is expected in a Schottky junction gate structure since the gate capacitance is much larger than the capacitance to the substrate and the gate oxide/silicon interface traps are eliminated (see Note S1). In the case of the MOSFETs, however, the SS is much worse, 157.1 mV/dec and 228.0 mV/dec for the InMOSFET and the DeMOSFET, respectively. Our simulation in Figure S5 verifies that the poor SS for the MOSFETs is not due to a poor gate to substrate capacitance ratio, but most likely due to the presence of a high density of interface traps (Cit) (see Note S1). Our results indeed demonstrate that the Schottky junction gate can provide the most efficient control of the SiNW channel conductance by eliminating the interface traps. VTH of the SJGFET extracted from the IDS vs. VG curve is 0.21 V, which is more positive than the VTH calculated by Eq

1, i.e., 0.09 V, using the measured tSi of 80 nm and with ND=1.2×1017 /cm3 and ΦB=0.85 V. Such difference likely arises from the depletion at bottom BOX/silicon interface which is not accounted in the calculation. Benefitting from the large ΦB of the PtSi/silicon junction, IDS of the SJGFET is more than four orders of magnitude higher than IGS in the subthreshold region. IGS starts to rise when IDS is above 10-8 A. This limits the operation range of the SJGFETs compared to the DeMOSFET and InMOSFET. However, the operation range can possibly be enlarged by lowering VTH, using larger channel thickness and/or higher channel doping (see Eq 1), or by increasing the Schottky barrier height with dopant segregation techniques.33,34 Output characteristics, i.e., IDS vs. VDS, of the SJGFET measured at different VG are shown in Figure 2(b). As VDS increases, the depletion layer on the drain end of the SiNW channel expands and eventually to the entire thickness of the channel at VD sat. Above this point, IDS reaches saturation and becomes independent of VDS. The LFN of an SJGFET was measured at different IDS set values, covering both subthreshold and linear regions in the IDS vs. VG transfer curve. Sid is presented for various IDS as shown in Figure 2(c). 1/f noise is observed at low frequencies (1-1k Hz) for all IDS with a frequency exponent γ between 1.2 and 1.5. Normalized Sid, i.e., Sid/IDS2, extracted at 10 and 100 Hz as a function of IDS are depicted in Figure 2(d). For fieldeffect sensor applications, the gate referred input noise, i.e., Svg, should be as low as possible in order to achieve a high SNR. Svg can be calculated using Sid and transconductance gm of the SJGFET as:

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Figure 2. Measured (a) IDS (solid lines) and IGS (dash lines) as a function of VG for an SJGFET (black), a DeMOSFET (red) and an InMOSFET (green). (b) Output characteristics (IDS vs. VDS) of the SJGFET. The dash line in (b) indicates the locus of VD sat. (c) Sid of an SJGFET as a function of f measured at different IDS levels, VDS=1 V, and (d) Sid/IDS2 and Svg at 10 and 100 Hz as a function of IDS. 𝑆vg =

𝑆id 𝑔2𝑚

,

(3)

As also shown in Figure 2(d), Svg is nearly constant in the subthreshold region and increases by a modest factor of two from the subthreshold region to the linear region. To elucidate the noise benefit of the SJGFET, LFN measurements were also performed on the InMOSFETs and the DeMOSFETs. The TVSEM image of such a MOSFET can be seen in Figure S4(b). To facilitate the comparison, “total noise current” and “total noise voltage”, i.e., 𝑖2T and 𝑣2T, in a given frequency band are used, instead of Sid and Svg at a single frequency.35 𝑖2T and 𝑣2T are defined as: 𝑓

𝑖2T = ∫𝑓𝑚𝑎𝑥𝑆id(𝑓)𝑑𝑓, 𝑚𝑖𝑛 𝑣2T =

𝑖2T 𝑔2𝑚

,

4) (5)

where fmin and fmax are the minimum and maximum frequencies, respectively. fmin=1 Hz and fmax=500 Hz are used for the total noise calculations throughout this paper. Since LFN also scales with the gate area,20,22 gate area-normalized total noise current squared (𝐴 × 𝑖2T) and noise voltage squared ( 𝐴 × 𝑣2T) are used for comparison between different devices. The total Sid of an SiNWFET fabricated in a SOI substrate can be contributed from three uncorrelated noise sources:20,29 𝑆id = 𝑆it + 𝑆ib + 𝑆ibulk, (6)

where Sit and Sib stand for the noise generated by the trapping and detrapping process at the top and bottom oxide/SiNW interfaces, respectively. Sibulk arises from the fluctuations in the SiNW bulk, which is a film-trap related generationrecombination noise and is significantly lower than Sit and Sib.29 Apparently, Sid is strongly dependent on the current distribution within the SiNW channel, e.g., high Sid is expected if IDS flows mainly close to the interfaces. Figure 3(a) shows measured 𝐴 × 𝑖2T as a function of IDS for the SJGFET, an InMOSFET, and a DeMOSFET with a substrate bias Vsub=0 V. Simulated electron density and corresponding current distribution of the devices biased in the subthreshold region are shown in Figure S6 to facilitate the discussion here. The InMOSFET has its current path located mainly close to the top interface and its Sid is thus dominated by Sit. The current conduction of the DeMOSFET is near the bottom interface so that Sib contributes mainly to its Sid. The higher 𝐴 × 𝑖2T observed for the InMOSFET than for the DeMOSFET indicates that the top HfO2/silicon interface has a higher density of interface traps. In both cases, the interface that is far away from the current path can still contribute to Sid as it is not completely shielded by a high concentration of carriers.29, 34 By replacing the top HfO2/silicon interface with a PtSi/silicon interface to completely suppress Sit, minimum 𝐴 × 𝑖2T is achieved as the case for the SJGFET. The noise benefit of the SJGFET is even more pronounced when 𝐴 × 𝑣2T of the three devices is compared. The tremendous advantage in 𝐴 × 𝑣2T of

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ACS Sensors the SJGFET arises from the combination of its low 𝐴 × 𝑖2T and large gm as a result of the near ideal SS. It is noted that measured 𝐴 × 𝑣2T of the SJGFET shown in Figure 3(b) is nearly constant, which is advantageous in practical applications as the SNR of the SJGFET is not affected by the VG. This constant 𝐴 × 𝑣2T implies a constant source of channel potential fluctuations such as interface charge fluctuations.

Figure 3. (a) 𝐴 × 𝑖2T and (b) 𝐴 × 𝑣2T as a function of IDS for the SJGFET, an InMOSFET, and a DeMOSFET at Vsub=0 V. To further investigate the different noise components in the SJGFET, LFN measurements were also conducted at different Vsub. Note that VTH of the SJGFET can be tuned by Vsub as shown in the simulated results in Figure 4(a) and the measured results in Figure S7. As illustrated in Figure 4(b), a positive Vsub can accumulate electrons at the BOX/silicon interface, leading to an IDS being more dominated by the conduction close to that interface. As a result, the contribution of Sib to Sid increases. On the other hand, a negative Vsub can push the conduction away from the BOX/silicon interface, i.e., deep into the SiNW bulk or close to the PtSi/silicon interface. In such a case, Sid becomes more dominated by Sibulk as Sit is now minimized by the PtSi/silicon Schottky junction. As demonstrated in the measurements shown in Figure 4(c), 𝐴 × 𝑖2T of the SJGFET increases considerably with a positive Vsub and decreases with a negative Vsub. It clearly indicates that Sib contribution from the BOX/silicon interface can be modulated by Vsub by moving the conduction path close or away from the bottom interface. A positive Vsub shows stronger effects on 𝐴 × 𝑖2T than a negative Vsub does, which is likely due to slight depletion at the bottom BOX/silicon interface even at Vsub=0 V. With the BOX/silicon interface in accumulation, i.e.,

Vsub=20 V, the SJGFET exhibits similar 𝐴 × 𝑖2T to that of the DeMOSFET, as Sid of the SJGFET is now dominated by Sib. The results confirm that the noise benefit of the SJGFET comes from the minimization of current fluctuations originating from the gate oxide/silicon interface. Measured 𝐴 × 𝑣2T as a function of IDS at different Vsub is also depicted in Figure 4(d). As expected, 𝐴 × 𝑣2T gives the same trend as 𝐴 × 𝑖2T, i.e., it increases as Vsub varies from -20 to 20 V. It is observed that the referred voltage fluctuations decrease strongly with VG and/or IDS at Vsub=20 V. The reason for this behavior is not obvious. A plausible explanation is that it is related to the movement of the Fermi-level at the bottom interface, i.e. the traps becoming fully occupied, hence inactive at higher channel electron concentrations. Considering the significant noise dispersion for nanoscale devices,20,36 𝐴 × 𝑖2T measured on several devices for each type of SiNWFET are included in Figure S8 to highlight the performance advantage of the SJGFET. For benchmarking, we also compared our results with other related work published from different university labs. A comparison of the gate area-normalized Svg is made in Table 1. It is worth noting that the noise of our SiNW-based SJGFET is better than that of the reported SiNW or Si nano-ribbon based FET devices.26,27,37,38 To demonstrate the ion sensing application of the SJGFET, pH and Na+ sensing using an extended gate31 is conducted with the detailed measurement arrangement schematically shown in the insert of Figure S9(a). The IDS-VG curves of an SJGFET measured with the top gate under dry condition and with the extended gate under liquid condition are depicted in Figure S9(a). Close to Nernstian limit sensing signal, 56 mV/dec for pH and 57.4 mV/dec for Na+, are achieved by the employed sensing layers as shown in Figure S9(b) and (c). The low noise properties of the SJGFET together with the close to ideal sensing signal generated by the sensing layers will hold promises for future high SNR sensor applications. It is worth noting that this new device concept is not limited to the nanowire geometry and can easily be adapted to FET fabrication with other semiconductors than silicon. In addition, other metal silicides such as NiSi with proper ΦB modification33 could also be promising gate metal candidates for SJGFETs. Silicide material optimization including process integration, gate leakage control, and noise evaluation & mitigation constitutes an interesting research direction to further improve the performance of SJGFETs. A potential issue with the SJGFET is gate leakage as excessive gate leakage would lead to a drift in the readout current. Therefore, the bias condition in the sensor circuitry needs to be adjusted, by adjusting the bias on reference electrode (VRE), so as to avoid forward biasing of the Schottky junction gate higher than 0.2V. The potential limitation of the SJGFET sensor operation window can be addressed by the source following circuit15, where the VTH shift of the device caused by the pH change is followed by the source potential to maintain a constant IDS.

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Figure 4. (a) Simulated IDS-VG curves of an SJGFET at Vsub=-5 V (red), 0 V (black), and 5 V (green). The effects of oxide charge in the BOX and defects at the BOX/silicon interface are not included in the simulation and Vsub is adjusted in the simulation to achieve similar VTH shifts as shown in Figure S7 with Vsub of ±20 V in the measurements. (b) The corresponding electron density (left column) and current distribution (right column) in logarithm scale extracted at IDS=1 µA/µm as indicated by the dash line in (a) show that the current path moves close to the BOX/silicon interface when the interface is turned from depletion (top) to accumulation (bottom). (c) Measured 𝐴 × 𝑖2T and (d) 𝐴 × 𝑣2T as a function of IDS for the SJGFET with different Vsub. Table 1. Comparison of gate area-normalized Svg of SiNW or Si nano-ribbon based FET publicationsa. This work Vsub=0 V

27

𝐴 × Svg (1 Hz) µm2V2/Hz

2.1×10-9

6×10-8

𝐴 × Svg (10 Hz) µm2V2/Hz

1.3×10-10

37

38

26

5×10-9 6×10-10

aAll

2.8~4.2×10-9

data are reported as values representing the best performance; some data have been converted from the original work for comparison purposes. surface can be a promising solution for future high signal/noise sensor applications. CONCLUSIONS In this work, novel SiNW-based SJGFETs with a Schottky junction gate were fabricated on SOI wafers by means of ASSOCIATED CONTENT standard silicon CMOS technology. The SJGFETs showed a Supporting Information Available: The following files are near ideal SS and a high Ion/Ioff exceeding 106. Significantly available free of charge. reduced LFN was observed on the SJGFETs as compared to the reference InMOSFETs and the DeMOSFETs with HfO2 as the gate oxide. The LFN of the SJGFETs could be further improved by tuning Vsub in order to position the active SJG_FET_SI.docx conduction channel inside the SiNW. We expect distinct improvements by eliminating all oxide interfaces with the use Subthreshold slope of a MOSFET; simulated IDS-VG curve of an of a gate-all-around structure with Schottky junction. SJGFET and electron density in the SiNW channel at different VG; schematic representations and process flows for an SJGFET, a Combining this low noise SiNW-SJGFET and an ideal sensing

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ACS Sensors DeMOSFET and an InMOSFET; VTH optimization for SJGFETs; TVSEM images for FETs with top gate; simulated IDS-VG curve for an InMOSFET in the absence of oxide/silicon interface trap defects; simulated electron density and current distribution for an SJGFET, a DeMOSFET, and an InMOSFET; IDS and IGS as a function of VG for an SJGFET with Vsub=0 V, -20 V, and 20 V; 𝐴 × 𝑖2T as a function of IDS for SJGFETs, DeMOSFETs, and InMOSFETs; and pH and Na+ sensing using a SJGFET.

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AUTHOR INFORMATION Corresponding Author * E-mail: (P.S.) [email protected] and (Z.Z.) [email protected]

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Author Contributions

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The manuscript was written through contributions of all authors. (16)

ACKNOWLEDGMENT This work was supported by the Swedish Strategic Research Foundation (SSF ICA 12-0047 and FFL15-0174), the Swedish Research Council (VR 2014-5588), and the Wallenberg Academy Fellow Program.

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