NANO LETTERS
Epitaxial III−V Nanowires on Silicon Thomas Mårtensson,† C. Patrik T. Svensson,† Brent A. Wacaser,† Magnus W. Larsson,‡ Werner Seifert,† Knut Deppert,† Anders Gustafsson,† L. Reine Wallenberg,‡ and Lars Samuelson*,†
2004 Vol. 4, No. 10 1987-1990
Solid State Physics/The Nanometer Structure Consortium, Lund UniVersity, Box 118, S-221 00, Lund, Sweden, and Materials Chemistry/nCHREM, Lund UniVersity, Box 124, S-221 00 Lund, Sweden Received August 6, 2004; Revised Manuscript Received September 2, 2004
ABSTRACT We present results of ideal epitaxial nucleation and growth of III−V semiconductor nanowires on silicon substrates. This addresses the long-time challenge of integrating high performance III−V semiconductors with mainstream Si technology. Efficient room-temperature generation of light on silicon is demonstrated by the incorporation of double heterostructure segments in such nanowires. We expect that advanced heterostructure devices, such as resonant tunneling diodes, superlattice device structures, and heterostructure photonic devices for on-chip communication, could now become available as complementary device technologies for integration with silicon.
Apart from the seemingly never-ending shrinking of device dimensions, two major routes to push the silicon semiconductor technology of today further are being explored: the integration of Si with other high-performance materials and the use of new ways of device fabrication such as nanoscale self-assembly methods.1-3 The integration of III-V compound semiconductors, which are dominant in applications such as light-emitting diodes4 and optoelectronics, with mainstream Si technology is a long sought after goal for the semiconductor industry. If mastered, several of the limitations of the otherwise ideal Si material could be compensated for: first the low efficiency in light generation in Si and, second, the lack of a versatile heterostructure technology required for many high-speed electronic and photonic devices. We report here the successful epitaxial growth of self-assembled III-V semiconductor nanowires on Si substrates. Epitaxial growth of III-V semiconductors on Si presents several difficulties such as lattice mismatch, differences in crystal structure (III-Vs have a polar zinc blende or wurtzite structure whereas Si has a covalent diamond structure), and a large difference in thermal expansion coefficient. Much work has been done on planar growth of III-V materials on Si using different approaches such as buffer layers, growth on patterned Si surfaces, and selected area growth from small openings. See, e.g., refs 5 and 6 for an in-depth and more recent review, respectively. A major challenge has been to avoid the formation of anti-phase domains related to the initiation of III-V growth on two atomic planes of silicon differing by one atomic layer, which leads to the formation * Corresponding author. E-mail:
[email protected]. † Solid State Physics. ‡ Materials Chemistry/nCHREM. 10.1021/nl0487267 CCC: $27.50 Published on Web 09/23/2004
© 2004 American Chemical Society
of anti-phase domain walls and defective material.5,7 Besides the efforts of integrating III-V materials on Si, other approaches toward the specific goal of efficient lightemission using Si are, for example, the formation of porous Si via electrochemical etching8 and the incorporation of luminescent defects, such as rare-earth impurities.9 Homoepitaxial growth of Si wires on Si on the µm scale using the vapor-liquid-solid (VLS) method was explored by Wagner and others already in the 1960s and 70s.10 More recently, several groups have demonstrated growth of Si nanowires on Si substrates11-14 with various degrees of perfection. Very recently growth of Ge nanowires on Si was also demonstrated.15 In heterostructured III-V nanowires grown on III-V substrates, devices such as resonant tunneling diodes16 and single-electron transistors17 have been demonstrated. Also, complex branched nanostructures,18 as well as large-scale site-controlled growth using nanoimprint lithography, have been realized.19 With the successful monolithic integration of III-V nanowires on Si substrates, the commercial impact of these high-performance devices would increase dramatically. In this work, we show that III-V nanowires can be grown epitaxially on Si substrates. By the term “epitaxially”, we mean that the crystallographic directions are transferred from the substrate to the nanowires. GaP has a lattice mismatch of less than 0.4% relative to Si and would therefore be the best candidate for epitaxial growth on Si among the III-V compounds. The GaP-Si junction could have applications in heterojunction bipolar transistors with GaP as large band gap emitter with sharp and ideal interfaces to Si.20 We successfully synthesized epitaxially oriented GaP nanowires on Si(111) and Si(001) substrates. To demonstrate room temperature light generation on silicon, we inserted light-
emitting GaAsP heterostructure segments. We also present results which suggest that epitaxial growth of nanowires on Si is possible for more heavily lattice-mismatched compounds such as InP (4.1%) and GaAs (8.1%). We used size-selected gold aerosol nanoparticles21 as seeding particles for nanowire growth. Prior to aerosol deposition, the Si substrates were cleaned and organic residues removed using standard methods (see Supporting Information). As a final step before deposition, the samples were treated with hydrofluoric acid to create a hydrogenterminated surface.22 The samples were then immediately transferred to a controlled nitrogen atmosphere where the aerosol deposition took place. Typically, 40 nm diameter Au aerosol particles at a density of 2 µm-2 were used. After aerosol deposition we took care to expose the sample as little as possible to open air as the hydrogen-terminated surface is known to deteriorate with time.22 The nanowire growth was performed in a low-pressure, 10 kPa, MOVPE system.23 Samples were annealed at 625 °C in a hydrogen atmosphere for 10 min before growth. The temperature was then ramped down to the growth temperature of typically 475 °C. Growth of GaP nanowires was initiated when the precursors, trimethyl gallium and phosphine, were introduced simultaneously into the growth cell. A typical growth time was 4 min. For incorporation of an optically active GaAsP heterosegment, arsine was switched on at a certain time during growth. The GaAsxP1-x composition was then controlled by adjusting the arsine-to-phosphine ratio. For growth of InP and GaAs on Si, the procedure was very similar but with different temperatures and precursors (see Supporting Information for details on growth parameters). Samples were then characterized using scanning electron microscopy (SEM), transmission electron microscopy (TEM), and photoluminescence (PL) spectroscopy. Figure 1 shows vertical GaP nanowires grown on a Si(111) oriented substrate. The preferred III-V nanowire growth direction in most reported cases in the literature is the [111]B direction, i.e., corresponding to vertical growth from a (111) oriented surface.24 This is indisputably the case when looking at Figure 1A and B and clearly demonstrates the perfect epitaxial nature of the growth. Well-aligned vertically oriented nanowires were reproducibly obtained in a large number (20+) of growth runs. Using Si(001) substrates, we observe that the nanowires grow in four different 〈111〉 directions (Figure 4B). On the (001) surface orientation, four equivalent 〈111〉 directions make an angle of 35.3° with the substrate distributed 90° apart azimuthally. For epitaxial growth all four directions can be expected since the 〈111〉 directions are equivalent. One of the main challenges is obviously to manage controlled growth orthogonal to the industry standard (001) Si substrate orientation. This is still to be developed, but in the case of InP, defect free growth in the [001] direction on (001) InP substrates has recently been achieved.25 To investigate the interface between the Si substrate and the GaP nanowire, samples were prepared for high-resolution transmission electron microscopy (HRTEM) by cleaving, 1988
Figure 1. Growth of GaP nanowires on Si(111). (A) A 45° tilt SEM micrograph of GaP nanowires growing vertically from the Si(111) surface in the [111] direction. A thin planar film of GaP on the Si substrate can be seen as a corrugation of the surface between the wires. From TEM investigations we estimate the film thickness to be about 20 nm, i.e., the uncatalyzed planar growth rate is approximately 10-2 of the nanowire growth rate. The wires were grown using 40 nm seed Au nanoparticles. Top wire diameter is close to 40 nm. (B) Top view of the same sample showing the perfection in the vertical alignment. Scale bar 1 µm. (C) HRTEM image of the Si substrate-GaP nanowire interface. The crystal directions from the Si substrate are transferred to the nanowire. Scale bar 10 nm.
polishing, and ion milling the silicon substrate after wire growth (Figure 1C). The transfer of crystallographic information from the Si substrate to the GaP nanowires can clearly be seen. Detailed studies of the substrate-nanowire interface will be published separately. Initial results suggest that III-V compounds with a large lattice mismatch such as GaAs (Figure 2A) and InP (Figure 2B), with lattice mismatch of 4.1% and 8.1% respectively, can also be grown epitaxially on Si. The small wire crosssection enables the wires to accommodate and relax strain from the large lattice misfits of otherwise incompatible materials.26-30 We found that hydrogen passivation of the Si surface was a crucial step, consistent with results reported for homoepitaxial growth of Si nanowires on Si.12 On samples where the native oxide was not removed prior to aerosol deposition, no epitaxial orientation was observed. We also noticed that for samples that were kept in a glovebox atmosphere for a longer time (∼3 months), the yield of straight epitaxial wires was lower than from freshly prepared samples. As the reoxidation of the HF-etched surface is moderately slow,22 Nano Lett., Vol. 4, No. 10, 2004
Figure 2. SEM images of vertical (A) GaAs nanowires and (B) InP nanowires grown on a Si(111) substrate. Tilt 45°, scale bars 1 µm.
this suggests that even a very thin layer of native oxide is detrimental to epitaxial wire growth. Compound semiconductors are particularly strong in optoelectronics where Si is hampered by an indirect band gap and thus a low light-generation efficiency. The use of III-V nanowires in optoelectronics has been demonstrated by devices such as light-emitting diodes (LEDs),31 photo detectors,32 and as potential single photon sources.33 In this work, we inserted light-emitting segments of GaAsxP1-x in the GaP wires grown on Si. The composition can be tuned by controlling the arsenic to phosphorus ratio during growth, and the length of the segment is determined by the growth time. Figure 3A shows a high angle annular dark-field scanning transmission electron microscopy (HAADFSTEM) image of a GaP nanowire with a 500 nm long segment of GaAsxP1-x. An X-ray energy dispersive spectrometry (XEDS) composition line scan of the segment (Figure 3B) shows that the interfaces are very sharp. From XEDS composition analysis we infer a composition of ∼30% P and ∼70% As in the segment.34 We characterized the optically active segments using PL spectroscopy and PL imaging. Figure 4A shows room temperature luminescence imaging in the deep red spectral region (725 nm) from standing wires, as-grown on Si (001). The nanowires were excited using an Ar+ laser, emitting at 458 nm and with an intensity of approximately 3 kW/cm2. A sample with a low wire density of ∼0.05 µm-2 was used to make it possible to resolve individual wires. In this case we chose the (001) substrate orientation to ease the collection of the light since light is mainly emitted in lobes from the segment and the light is collected from above. The elongations of the spots in two perpendicular directions correspond to the projection of the four different 〈111〉 directions (Figure 4B) as discussed above. The fact that luminescence of individual nanowires can be imaged at room-temperature suggests that the radiative recombination from GaP/GaAsP/ GaP double heterostructure segments is not thermally quenched even at room temperature. This is explored next. For a detailed PL-spectroscopy study, standing nanowires were scraped off from a (111) substrate and transferred to a grid-patterned SiO2 surface. The advantage of placing the nanowires on the grid structure is that, after PL spectroscopy, Nano Lett., Vol. 4, No. 10, 2004
Figure 3. HAADF STEM images of light-emitting GaAsP segments incorporated in the GaP nanowires during growth. The segments were approximately 500 nm long corresponding to a growth time of 1 min of a total of 5 min. (A) The location of the segment in the nanowire is seen as a brighter region in the mid section. Scale bar 500 nm. (B) XEDS line scan of the GaP nanowire with GaAsP segment showing the sharp nature of the interface. Scale bar 200 nm.
each wire can be located with SEM to confirm that it is a single wire with a well-defined segment. PL spectra from separate nanowires were recorded at 10 K and roomtemperature, demonstrating high uniformity (Figure 4C) in the luminescence from the individual wires. The GaP/GaAsP/ GaP nanowires exhibit sharp peaks at about 1.78 eV with a full width half-maximum (fwhm) of about 60 meV at 10 K. The PL remains bright at room temperature with peaks shifted to 1.71 eV and with an average fwhm of about 75meV, with negligible quenching of the emission. The spectral shift corresponds well with the band-gap shrinkage from 10 K to room temperature. Comparing the PL spectra with data in the literature for bulk GaAsP, we infer a composition of GaAs0.8P0.2, in reasonable agreement with the XEDS composition analysis.29 By changing the AsxP1-x composition in the segment it is possible to continuously tune the emitting wavelength from the band gap of GaP to the band gap of GaAs representing a wavelength span of 550-900 nm, corresponding to the spectral range achieved in the GaAsP LED technology for growth on GaP. We have presented device-quality III-V semiconductor growth on silicon substrates with perfect epitaxial nucleation of oriented III-V nanowires. We demonstrated visible roomtemperature luminescence of these heterostructure III-V nanowires as bright as at cryogenic temperatures. In the extension of this work it is easy to envisage how carefully controlled self-assembly of functioning nanowire building blocks will enable logic devices and circuits as well as optoelectronics and memory systems on silicon, as complementary technologies of today’s mainstream silicon technology. 1989
Figure 4. Photoluminescence from nanowires. (A) Room-temperature PL from standing wires as-grown on a Si(001) surface, seen from above. When excited with a 458 nm laser source the wires emit at 725 nm. The luminescence was visible to the naked eye and the image was recorded using a standard digital camera with 15 s integration time. Scale bar 5 µm. (B) Top view SEM image of the same sample used for the PL recording of panel A. Four nanowires grow in the four different 〈111〉 directions. The nanowires form an angle of 35.3° with the Si(001) surface as illustrated in the cartoon. Scale bar 1 µm. (C) 10 K and room-temperature PL spectra from individual wires scraped off and resting on a SiO2 surface. The luminescence from the wires remained bright at room temperature, with negligible quenching observed.
Acknowledgment. We thank V. Zela for assisting in the sample preparation, N. Sko¨ld for assistance with PL, and I. Maximov, P. Carlberg, and D. Adolph for assisting with the TEM sample preparation. This work was performed within the Nanometer Structure Consortium at Lund University, and supported by the Swedish Research Council (VR), the Swedish Foundation for Strategic Research (SSF), Office of Naval Reasearch (ONR), and the Knut and Alice Wallenberg Foundation. Supporting Information Available: Experimental details and growth parameters. This material is available free of charge via the Internet at http://pubs.acs.org. References (1) Samuelson, L. Mater. Today 2003, 6, 22. (2) Lieber, C. M. Sci. Am. 2001, 285, 58. (3) Xia, Y. N.; Yang, P. D.; Sun, Y. G.; Wu, Y. Y.; Mayers, B.; Gates, B.; Yin, Y. D.; Kim, F.; Yan, Y. Q. AdV. Mater. 2003, 15, 353.
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