NANO LETTERS
Fabrication and Field Emission Properties of Triode-Type Carbon Nanotube Emitter Arrays
2009 Vol. 9, No. 2 595-600
Jianfeng Wu, Madeline Wyse, Devon McClain, Nicole Thomas, and Jun Jiao* Department of Physics, Portland State UniVersity, P.O. Box 751, Portland, Oregon 97207 Received September 12, 2008; Revised Manuscript Received December 5, 2008
ABSTRACT We report here an effective method for the fabrication of a large number of triode-type microgated carbon nanotube field emitter arrays. Our technique combines dual-beam focused ion beam technology and plasma-enhanced chemical vapor deposition, avoiding the tedious lithography and wet chemistry procedures conventionally used to fabricate such structures. Field emission testing revealed that increasing gate voltage by as little as 0.3 V had significant impact on the local electric fields, lowering the turn on and threshold fields by 3.6 and 3.0 V/µm, respectively. The field enhancement factor of the emitter arrays was also increased from 149 to 222. A quantum mechanical model for such triode-type field emission indicates that the local electric field generated by a negatively or positively biased gate directly impacts the tunneling barrier thickness and thus the achievable emitter current.
Carbon nanotubes (CNTs) exhibit excellent field emission properties and will likely be prime candidates as electron sources in future vacuum electronic applications.1-4 Traditional diode-type field emission can be further enhanced with the creation of a triode-type configuration in which an integrated gate electrode is added between the anode and cathode. Since the gate to cathode (emitter) distance is smaller than the anode to cathode distance, these arrangements allow relatively small gate voltages to exert significant control over field emission. The key challenge for fabricating triode-type field emitter arrays is how to accurately grow emitters inside of the gated cavities. The most common method involves multiple steps of etching the cavities, depositing catalyst into the cavities, and synthesizing the emitters. Lee et al.5 successfully employed this method using chemical vapor deposition (CVD) to synthesize CNT emitters. Subsequent work by Gangloff et al.,6 Choi et al.,7 and Li et al.8 were all based on these processes. Gangloff et al.6 greatly improved the morphology of the emitters by replacing the CVD method with plasma enhanced CVD (PECVD) and adding additional steps to reduce the size of the deposited catalyst dots until a single CNT emitter was fabricated within each cavity. Choi et al.7 increased emission control by adding an additional focusing gate layer, and Li et al.8 adapted the method to grow side-gated ZnO nanowire emitters. All of these studies relied on the basic etch-deposit-synthesize method to construct their devices. However, novel approaches to device construction have been explored. She et * To whom correspondence should be addressed. E-mail:
[email protected]. 10.1021/nl802777g CCC: $40.75 Published on Web 01/22/2009
2009 American Chemical Society
al.9 synthesized a Si nanowire-gated field emission device using self-assembled nanomask and anisotropic plasma etching. Guillorn et al.10 created carbon nanofiber emitters using a reversal process, where the deposition of catalyst dots on silicon substrate occurs first and is then followed by the synthesis of single vertically aligned carbon nanofiber emitters using PECVD. Next, they buried the emitters in a SiO2 insulator layer and subsequently deposited a metal gate layer on top of SiO2. To expose the CNT emitters, a targeted wet-etching process had to be used. The aforementioned methods are tedious and time-consuming, which is one of the reasons why we focused our efforts on making this process more efficient. In this study, we demonstrated an effective approach to synthesizing microgated carbon nanotube field emitter arrays (MG-CNT-FEAs). We began by depositing a multilayer substrate, complete with an embedded catalyst layer and capped by a gate layer. We then created a triode structure by milling holes in the substrate using a dual-beam focused ion beam (DB-FIB) and then grew gated CNT emitters from the exposed catalyst. The fundamental differences between our fabrication technique and previously reported methods4-12 are the simplicity of our catalyst positioning method and the employment of the DB-FIB milling, rather than using lithography and wet etching. We conducted field emission tests on our completed device to determine the effectiveness of its gate layer. We also constructed a simple simulation to indicate the general trends in field emission associated with gate potential.
Figure 1. Schematics of the multilayer substrate with embedded Ni catalyst. DB-FIB was used to mill microgated holes and expose the catalyst layer using I(a) the single-hole method, in which we milled directly to the catalyst, and II(a) the two-hole method, in which an initial hole was milled into the SiO2 insulating layer, followed by a smaller, concentric hole milled to the catalyst. This second method prevented short circuiting between the gate and cathode layer. SEM images of milled arrays are shown in I(b) and II(b). I(c) and II(c) demonstrate one of the completed metal-gated CNT emitter holes on the substrate generated by the single-hole method and the two-hole method, respectively.
A schematic of our fabrication method can be seen in Figure 1. To construct the substrate, we coated the surface of the Si substrate with adhesive indium tin oxide (ITO) and then deposited a thin layer of Ni catalyst. The catalyst was then buried under an insulating layer of SiO2, where the SiO2 layer was coated by another layer of ITO followed by a Pt gate layer.13 Selective DB-FIB milling was used to carve gated holes into the multilayer substrate, exposing the catalyst. The milled substrate was then placed in a PECVD reactor and CNTs were synthesized within each gated hole, completing the MG-CNT-FEAs fabrication. This approach achieved controlled exposure of the catalyst without the elaborate, localized catalyst deposition methods reported in previous methods. In addition, the application of the DBFIB technique in combination with PECVD growth allowed for a new level of control and reproducibility in the synthesis of MG-CNT-FEAs. During the development of this tech596
Figure 2. SEM image of MG-CNT-FEAs synthesized by PECVD. In the top image, hole depth increases as we go down each column. Shallow holes failed to uncover the catalyst layer (a) or only partially uncovered it (b) resulting in irregular growth. Uniform CNT growth (c) indicated optimum milling time, while subsequent rows of irregular growth (d) indicated overmilling of the catalyst layer.
Figure 3. (a) A large area MG-CNT-FEAs fabricated by a combination of DB-FIB and PECVD techniques. (b) One of the fabricated MG-CNT-FEAs devices from panel a. (c,d) Cross-section views of one of these MG-CNT-FEAs devices.
nique, we encountered a number of challenges. We were able to find solutions for avoiding gate-cathode short circuiting, Nano Lett., Vol. 9, No. 2, 2009
Figure 4. (a) Schematic illustration of the UHV field emission measurement setup. (b) Current density vs electric field plot. The arrows indicate threshold field, defined as the fields at which current density is equal to 1 mA/cm2. (c) Fowler-Nordheim plot. Field enhancement factor is calculated from the slope of the linear best fit.
Table 1. Relationships Between Gate Voltage (Vg) and the Turn on Electric Field, Threshold Electric Field, and Field Enhancement factor β of the MG-CNT-FEAs gate voltage Vg (V)
turn on electric field (V/µm)
threshold electric field (V/µm)
field enhancement factor β
-0.2 0 0.1
20.0 19.2 16.4
23.8 22.4 20.8
149 165 222
by controlling microgated hole depth for optimal CNT synthesis, and reducing gate-cathode capacitance. When we first used the DB-FIB to mill the substrate for the exposure of the catalyst layer (as shown in Figure 1-Ia,b), the CNTs grew around the perimeter of the hole, resulting in a short circuit between the substrate and the gate layer (Figure 1-Ic). To overcome this obstacle, we were able to modify the fabrication design by milling one hole inside of another (Figure 1-IIa,b) to prevent the CNTs from short circuiting with the gate layer. In this case, the first hole was milled into the insulating SiO2 layer, and then a second hole of smaller diameter was milled further, exposing the catalyst layer. The CNTs now formed around the inner wall of the smaller hole (Figure 1-IIc). The CNTs consistently grew around the perimeter of the holes because the sputtered catalyst particles tended to redeposit on the walls of the inner Nano Lett., Vol. 9, No. 2, 2009
Figure 5. (a) Potential energy contour plot in the CNT emitter cap under constant anode voltage 20 V/µm. The dotted line is the equipotential line for the Fermi energy (-4.95 eV). (b) Schematic diagram of the energy barriers along the central axis of one of MGCNT-FEAs under different anode and gate voltages.
Table 2. Simulation Data of Energy Barrier Thickness Under Different Anode and Gate Voltages anode voltage (V)
gate voltage (V)
barrier thickness (nm)
600 1000 1400 1000 1000
0 0 0 -10 10
35.9 17.9 11.8 20.7 15.8
hole,13 rather than from their centers, because the Ni catalyst layer was completely milled away by the DB-FIB. This new morphology not only solved the short circuit problems but allowed us to control the distance between the CNTs and the gate layer by varying the radius of the outer and inner holes. In this report, we demonstrate the synthesis of MGCNT-FEAs with an outer hole radius of 1.5 µm and an inner hole radius of 0.5 µm. Another challenge in the fabrication process was control over the milling geometry and depth to accurately expose the amount of catalyst required for the CNT growth. We used Autoscript software to optimize the milling procedures for control of the milling depth. In an initial trial, we milled an array of successively deeper rows of holes and then synthesized CNTs in each of them (Figure 2). The results suggest that when the nickel (Ni) layer was barely exposed, very few CNTs grew (Figure 2a). Partially exposing the Ni layer resulted in low CNT density and nonuniform growth (Figure 2b). However, when the Ni layer was completely 597
exposed within the hole, the CNT grew uniformly along the perimeter of the hole, as in Figure 2c. The characterization of subsequent rows suggests that if the ion beam had milled too deep, it would result in reduced numbers of CNTs (Figure 2d). By analyzing these results, we established the optimal milling time for catalyst exposure. In our two-hole case, the outer hole was formed within 44 s of milling time with a beam voltage of 30 kV and beam current of 300 pA. An additional 5 s of milling with the same parameters was used to create the inner hole to expose the catalyst. During the field emission measurement, we found that the capacitance between the gate and cathode layers due to their small separation distance (1 µm) became a problem. The issue of capacitance is important for two reasons. First, because the energy stored in emitter arrays (E ) CVg2/2) increases with the increase of capacitance (C), the larger capacitance could cause leakage current and perhaps breakdown the SiO2 isolating layer.14 Second, for the modulation of the emission, the power required to drive the emitters is proportional to the capacitance squared.15 Thus, it is important to keep the capacitance as low as possible. In general, capacitance (C) can be described as14 C ) εrε0
A d
where A is the area of each plate, d is the separation between the plates, εr is the relative static permittivity of the SiO2 (3.9),16 and ε0 is the permittivity of free space (8.85 × 10-12 F/m).14 The easiest way to decrease the capacitance is to decrease the area (A) of the gate layer. In our experiment, we were able to significantly reduce the relevant gate area by using DB-FIB to cut through the Pt layer in a rectangle around the MG-CNT-FEAs test area (400 µm × 350 µm), separating it from the rest of the gate layer (2 mm × 2 mm). In our field emission testing, this small section of the gate layer, rather than the whole substrate surface, was biased as desired. Calculations indicate this step significantly reduced the gate-cathode capacitance from approximately 138 to 5 pF. Additional study is underway to further decrease the gate area by patterning ring-shaped gates around individual holes. We could also decrease capacitance by increasing the thickness of the SiO2 layer. Since CNTs can be grown to a range of heights, we have a degree of flexibility in our choice of gate-cathode distance, d. Having dealt with the issues of short circuiting, optimal milling depth, and capacitance, we were able to scale up our fabrication. Using the optimized DB-FIB milling conditions, we were able to synthesize over seven hundred uniform CNT emitters within a relatively large area (300 µm × 300 µm) with a packing density of 2.5 × 106 tips/cm2, as shown in Figure 3a. Note that each microgated emitter has a similar microstructure to the one shown in Figure 3b. Figure 3 panels c and d are cross-section views of one of these microstructures, showing the locations of gate electrode, SiO2 insulator, Ni catalyst layer, Si cathode, and vertically aligned CNT emitters. These images reveal CNT emitters formed from the inner walls of the smaller hole, where the sputtered Ni catalyst is located.13 Note that the thickness of the CNTs in Figure 3c is increased due to the substrate redeposition during the DB-FIB milling process to create this cross-section view. 598
We were able to program the DB-FIB to fabricate a largearea emitter array to the millimeter scale. This advancement from single device synthesis to large-scale array is critical for achieving mass production of MG-CNT-FEAs. To test their field emission properties, we loaded the MGCNT-FEAs into a three-probe ultra-high vacuum (UHV) probe station chamber with a base pressure of 10-9 Torr. We heated the sample to 200 °C for 24 h to eliminate water vapor or other possible residual adsorbates on the emitters. The experimental setup for the field emission measurements is shown in Figure 4a. We positioned the 25 µm diameter tungsten anode probe so that the gap between the anode and the sample was 50 µm. All three probes could be moved in the x, y, and z directions. During field emission, the anode was driven positively using a variable dc voltage power supply to extract electrons from the MG-CNT-FEAs. The emitted electrons were measured as anode current by a Keithley 485 picoammeter. Another tungsten probe was connected to the gate layer and used to change the gate voltage controlled by an Agilent 4156C semiconductor parameter analyzer. We began examining the field emission with the gate voltage set to zero. We subsequently introduced positive and negative gate voltages and studied the impact of a triode structure on field emission. All of these tests were repeated on a number of individual emitters and samples in order to ensure the reproducibility of the MG-CNT-FEAs properties. Each measurement was taken using a 25 µm diameter anode probe that stimulated multiple devices simultaneously. The collective field emission from each subset, the 25 µm diameter area defined by the anode probe, is the sum of the emissions from the devices within that subset. Although individual devices may exhibit slight variations in morphology, field emission measurements taken from subsets across the array were highly uniform. In our field emission tests, the anode to cathode distance (50 µm) was much larger than the gate to the CNT emitter (cathode) distance (∼0.1 µm). Therefore, small changes in gate voltage (in the range of -1V to 1V) were able to generate large changes in the local electric field. Figure 4b shows three plots of typical emission current densities versus electric fields. This data was obtained with the Pt gate layer biased at -0.2 (negative gate voltage), 0, and +0.1 V (positive gate voltage). These voltages were selected to investigate the impact of negatively and positively biased gate layers on emitter current density. Also, since the energy stored in emitter arrays (E ) CVg2/2) is proportional to the voltage squared, it is desirable to have the lowest possible gate voltage (Vg) because larger gate voltages could cause damage to the SiO2 isolating layer.14 The plots in Figure 4b clearly indicate that emission current densities can be effectively altered by gate bias. The turn on electric field, defined as the field at which current density reaches 10 µA/ cm2, decreased from 20.0 to 16.4 V/µm as a result of the increase in gate voltage (Vg) from -0.2 to 0.1 V. Similarly, the threshold field, defined as the field at which current density is equal to 1 mA/cm2 (indicated with an arrow in Figure 4b), decreased from 23.8 to 20.8 V/µm as a result of the increase in Vg from -0.2 to 0.1 V. We used the Nano Lett., Vol. 9, No. 2, 2009
Fowler-Nordheim (F-N) field emission model in interpreting our results. According to the F-N theory,17,18 the current density J (Ampere/cm2) can be expressed as J)
(
2 2 φ3 ⁄ 2 I k1β E ) exp -k2 A φ βE
)
where k1 ) 1.54 × 10-6 A eV V-2 and k2 ) 6.83 × 107 eV-3/2 V cm-1. I is the emission current (ampere), A is the emission area (cm2), β is the enhancement factor, E is the applied electric field in V cm-1, and φ is the work function in eV. The equation can be further expressed as 2
(
k1β J φ3 ⁄ 2 exp ) -k 2 φ βE E2
and thus
( ) ( )
ln
)
k1β2 J φ3 ⁄ 2 1 ) ln - k2 2 φ β E E
()
Hence, the field enhancement factor, β, can be calculated from the slope (S) of the F-N curve [ln(J/E2) versus 1/E] using the equation S ) -k2
φ3 ⁄ 2 β
The multiwalled CNT has a work function of φ ) 4.95 eV.19 The F-N plot shown in Figure 4c depicts the effect of gate voltages (Vg) on the MG-CNT-FEAs device. The linearity of the F-N plots confirms that the field emission results from a quantum mechanical tunneling process. We demonstrate in this field emission device that gate potential plays an important role in field emission control. The slope (S) of the F-N plot decreased with increasing Vg, meaning the field enhancement factors increased. This phenomenon indicates that increasing Vg introduces an extra electric field that can help excite more electrons from these CNT emitters, leading to an increase in β and a decrease in turn on and threshold field, as summarized in Table 1. In order to better understand the trends associated with gate potential, we simulated one microgated CNT field emitter and plotted the potential energy contours around the cap under an external field of 20 V/µm using simplified, idealized conditions (Figure 5a) because the experimentally fabricated MG-CNT-FEA is too complicated to simulate. In order to determine the role of gate bias, we only considered the case of a single CNT emitter, rather than the type of circle growth synthesized in our actual experiment and modeled the CNT emitter as a metallic cylinder capped with a hemisphere. Using this model and selected anode and gate voltages, we were able to establish the correlation of gate voltage, anode voltage, and the field emission. In this simulation, we solved Laplace’s equation to determine the variation in electrostatic potential energy, represented in Figure 5a as a color spectrum from blue (low potential) to red (high potential). The dotted line marks the energy contour for Fermi energy (-4.95 eV) of the multiwalled CNT. Note that the equipotential surfaces are closest together directly above the CNT tip, indicating that the Nano Lett., Vol. 9, No. 2, 2009
strongest electric field points along the central axis and that this is the direction the electrons are most likely to tunnel. Figure 5b shows a schematic of the simulated energy barriers along the central axis of the CNT’s tip under five different field emission conditions (listed in Table 2). As anode voltage increases from 600 to 1000 to 1400 V, the barrier thickness decreases from 35.9 to 17.9 to 11.8 nm respectively. If the potential barrier is thin, there is a significant chance that the electrons will pass through the barrier and escape into the vacuum, a process called quantum mechanical tunneling.20 The probability of tunneling vanishes with the increased thickness of the barrier, which can be adjusted by changing the gate voltage. To determine the impact of positive and negative gate voltages on barrier thickness, we simulated a single gated CNT emitter with constant anode voltage of 1000 V and gate voltages of -10, 0, 10 V. The negative gate voltage increased the tunneling barrier thickness from 17.9 to 20.7 nm, decreasing field emission, while the positive gate decreased barrier thickness from 17.9 to 15.8 nm, increasing field emission (Figure 5b). This trend is consistent with our experimental data. This suggests that changing the gate voltage will effectively modify the emission current generated by the anode and cathode voltage. In sum, we reported here an effective technique to fabricate large-scale, reproducible MG-CNT-FEAs. This technique employs DB-FIB to carve gated holes from a multilayer embedded catalyst substrate and PECVD to synthesize CNT emitters in these microgated holes. The special hole and gate structures were designed to prevent short circuiting between the cathode and gate layers, to reduce cathode-gate capacitance, and to ensure an optimal CNT emitter yield. In testing the field emission of this triode structure, we found that increasing gate voltage from -0.2 to 0.1 V lowered the turn on field from 20.0 to 16.4 V/µm and the threshold fields from 23.8 to 20.8 V/µm, while increasing the field enhancement factor from 149 to 222. A theoretical simulation of the relationships among anode voltage, gate voltage, and the tunneling barrier thickness was conducted. The results demonstrate that negative gate voltages increased tunneling barrier thickness, while positive gate voltages decrease thickness, making electron tunneling significantly easier and thus generating a higher emission current density. It is expected that the fabrication and testing techniques introduced here will generate impacts for the further advancement of CNT field emission devices in emerging technologies and applications. Acknowledgment. Financial support for this research was provided in part by the National Science Foundation under award Nos. ECS-0348277, ECS-0520891, and DMR0649280. The authors would also like to thank our colleagues, Dr. Mark Mann and Dr. Kenneth Teo, at Cambridge University (U.K.) who provided the multilayer substrate. References (1) Zhu, W.; Bower, C.; Zhou, O.; Kochanski, G.; Jin, S. Appl. Phys. Lett. 1999, 75, 873. 599
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