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Fabrication of Pt-Si Schottky Diodes Using Soft Lithographic Patterning and Selective Chemical Vapor Deposition Martin K. Erhardt† and Ralph G. Nuzzo*,†,‡ Department of Chemistry, Department of Materials Science and Engineering, and the Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, Urbana, Illinois 61801 Received September 9, 1998. In Final Form: December 21, 1998
This work demonstrates the feasibility of using soft lithographic patterning in conjunction with additive metallization to fabricate micron-scale electronic devices. Specifically, the fabrication of platinum/platinum silicide/silicon Schottky diodes is demonstrated using a unique combination of soft lithographic patterning and additive metallization techniques. The diode architecture provides a useful means through which to demonstrate the specific characteristics and general utility of this fabrication technique. A 30 × 10 array of micron-scale diode features was patterned on a silicon substrate using a polymeric film prepared by micromolding in capillaries (MIMIC), a soft lithographic patterning technique. Following etching to remove oxide from the substrate surface, metallization by selective platinum chemical vapor deposition (CVD) was used to form rectifying contacts to the substrate. The polymeric film successfully served both as an oxide etch resist before metallization and as a deposition-inhibiting surface for the selective deposition of platinum. The selectivity of the deposition was confirmed by secondary ion mass spectrometry (SIMS). Electrical characterization of the metallized areas showed expected diode behavior. Rutherford backscattering (RBS) and Auger sputter-depth profiling revealed the presence of significant amounts of both Pt and Si at the surface of the platinum film, suggesting that silicide formation accompanies the thin film growth. An unusual feature of the platinum-silicon microstructures obtained in this work was the presence of a platinum concentration gradient within the film instead of the well-defined interfaces between intermetallic phases that are typically seen in platinum silicide layers. A backscattering simulation was used to extract the elemental depth profiles from the RBS data.
Introduction The growing interest in new methods for effecting the micron-scale patterning of thin metal films on semiconducting substrates has been fueled by their centrality in solid-state microelectronic devices. Such devices are currently mass-produced by photolithographic patterning followed by metallization,1 yet the utility of these fabrication methods for microelectronics is limited both by the feature resolution permitted by the wavelength of the light used and by constraints on the size and planarity of the substrates.2 The prohibitive cost and complexity of exposure optics and high-energy light sources for sub-193 nm wavelengths are also significant obstacles clouding the future of photolithographic patterning.3 Therefore, it is potentially advantageous to minimize the use of photolithography as a necessary tool for microfabrication. Aside from photolithography, a second area with potential for improvement in traditional device fabrication is the development of alternatives to subtractive processing techniques which create a pattern by blanketing the substrate with the deposited material and subsequently removing the excess according to the pattern desired. Patterning metal films via subtractive processing methods is also limited by the availability of high-throughput etching processes that are chemically compatible with † ‡
Department of Chemistry. Department of Materials Science and Engineering.
(1) Streetman, B. G. Solid State Electronic Devices; Prentice-Hall: Englewood Cliffs, NJ, 1995. (2) Xia, Y.; Whitesides, G. M. Angew. Chem., Int. Ed. Engl. 1998, 37, 550. (3) Moore, G. Electrochem. Soc. Interface 1997, Spring, 18.
integration on silicon.4 More generally, the expense of waste stream disposal, the intensive use of solvents in processing, and the need for stringent environmental controls provide additional incentives to search for alternative processing techniques. The use of unconventionally patterned polymeric films in place of photoresist in microelectronic device fabrication has been a topic of recent interest in the literature.2,5-11 This work demonstrates how such films can be made by “soft lithographic” patterning and then used in two sequential device fabrication processes: oxide etching and additive metal deposition. In this demonstration, the polymeric film on the silicon substrate acts both as an etch resist and as a template for metalization of the device by selective chemical vapor deposition (CVD). The film is formed using the micromolding in capillaries (MIMIC) polymer patterning method demonstrated by Xia, Kim, and Whitesides.5 This method offers significant promise for industrial application and as a soft lithographic patterning tool.2 We have recently reported the fabrication (4) Mogab, C. J. In VLSI Technology; Sze, S. M., Ed.; McGraw-Hill: New York, 1983; p 303. (5) Xia, Y.; Kim, E.; Whitesides, G. M. Chem. Mater. 1994, 8, 1558. (6) Jeon, N. L.; Hu, J.; Whitesides, G. M.; Erhardt, M. K.; Nuzzo, R. G. Adv. Mater. 1998, 10, 1466. (7) Hu, J.; Beck, R. G.; Westervelt, R. M.; Whitesides, G. M. Adv. Mater. 1998, 10, 574. (8) Terris, B. D.; Mamin, H. J.; Best, M. E.; Logan, J. A.; Rugar, D.; Rishton, S. A. Appl. Phys. Lett. 1998, 69, 4262. (9) Martin, C. R. Science 1994, 266, 1961. (10) Garnier, F.; Hajlaoui, R.; Yassar, A.; Srivastava, P. Science 1994, 265, 1684. (11) Chou, S. Y.; Krauss, P. R.; Zhang, W.; Guo, L.; Zhuang, L. J. Vac. Sci. Technol., B 1997, 15, 2897.
10.1021/la9812222 CCC: $18.00 © 1999 American Chemical Society Published on Web 02/24/1999
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Figure 2. Template pattern used to define features for an ensemble of three separate diodes. The whole mold consisted of a 30 × 10 array of identical ensembles. Figure 1. Schematic of diode fabrication steps. The polyurethane is deposited on the silicon substrate by spreading through recessed areas of a patterned poly(dimethylsiloxane) mold.
of Si-based MOSFETs using soft lithographic patterning methods.6 Here we show how soft lithography can be used in conjunction with selective chemical vapor deposition to fabricate platinum silicide Schottky diodes. We chose to make Schottky diodes because they provided a convenient and industrially important architecture by which to demonstrate the specific characteristics of this fabrication technique. As noted above, additive processing offers several potential advantages over the subtractive processes that are traditionally used in microelectronic device fabrication. These include the more efficient use of metal source precursors and solvents, reduced number of process steps, potential for enhanced scalability, and time savings. The selective Pt metalization described here shows potential for replacing traditional metal evaporation followed by liftoff or etching.12 We have previously described the selective CVD of platinum and other metals directed by self-assembled monolayers (SAMs) of octadecyltrichlorosilane (OTS) patterned by microcontact printing (µCP).13,14 SAMs patterned by µCP, while possessing many attractive qualities as templates for CVD growth, do have some limitations. First, they are poor etch resists and thus limit the range of processes which can be joined to the additive CVD step. Second, SAMs are very thin and thus are not expected to be effective in constraining the lateral dimensions of a CVD film as the mass coverage of the film becomes very large compared to that of the SAM. In an effort to overcome these shortcomings, we have examined the utility of polyurethane films patterned by MIMIC to serve both as an etch resist and as a selective CVD template. These issues are explored using the construction of an array of platinum silicide Schottky diodes as a test example for the joined use of additive (12) Mayer, J. M.; Lau, S. S. Electronic Materials Science; Macmillan: New York, 1990. (13) Jeon, N. L.; Lin, W.; Erhardt, M. K.; Girolami, G. S.; Nuzzo, R. G. Langmuir 1997, 13, 3833. (14) Jeon, N. L.; Clem, P. G.; Nuzzo, R. G.; Payne, D. A. J. Mater. Res. 1995, 10, 2996.
metalization and soft lithography as tools for device microfabrication. The present work complements and extends an earlier report on the use of soft lithographically defined etching as a means to fabricate Schottky diodes with Au/Cr contacts to Si.7 Experimental Section The Schottky diodes were fabricated on a 500 µm thick, heavily n-doped (Sb, 1018 cm-3) silicon (100) substrate with a 4.5 µm deep, lightly n-doped (P, 1016 cm-3) epilayer. The entire wafer was covered with 1500 Å of thermal oxide. A patterned polymeric mold (poly(dimethylsiloxane), Dow Corning Sylgard 184) was fabricated from a photolithographically produced master pattern on a silicon substrate following a previously reported method.15 The mold consisted of a 30 × 10 array of a MOSFET contact definition pattern, shown in Figure 2. This mold yields features of up to 200 µm, with spacings down to 40 µm; we note, though, that features as small as 1 µm have been patterned using MIMIC.15 To facilitate subsequent introduction of polyurethane into the recessed regions of the mold, one edge of the mold was cut slightly into the patterned area. The mold was then brought into contact with the SiO2 layer covering the wafer’s lightly doped epilayer. Polyurethane (Norland Products, NOA 73) was then placed dropwise along the open edge of the mold. After 15 min, the polyurethane had permeated the entire patterned region. The polyurethane was then cured for 8 min under a mercury vapor UV lamp, after which the mold was peeled from the wafer, revealing a polyurethane pattern. The wafer was placed in a 6:1 buffered NH4F/ HF solution for 2.5 min to remove the oxide from the exposed regions of the wafer, rinsed in deionized wafer and 2-propanol, and finally dried under a nitrogen stream. Immediately after the etching step, the wafer bearing the polyurethane film was placed in a home-built, cold-wall stainless steel CVD reactor,13 and 800 Å of platinum was deposited. The thickness of the deposited film was measured by surface profilometry. To effect this deposition, the sample temperature was maintained at 300 °C throughout the deposition, with a total chamber pressure of 1 Torr. Platinum (II) hexafluoroacetylacetonate (Pt(hfac)2, Strem Chemicals) was used as a precursor and was delivered to the substrate by argon gas flowing at 35.0 sccm. The precursor vial was kept in a 55 °C constanttemperature water bath throughout the deposition. Hydrogen gas was flowed across the sample to effect precursor reduction to metal. Water vapor was introduced into the chamber to assist nucleation via a reservoir attached to the hydrogen delivery line. (15) Kim, E.; Xia, Y.; Whitesides, G. M. Nature 1995, 376, 581.
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Figure 3. (a) Optical micrograph of diodes fabricated by the method shown in Figure 1 before removal of the polyurethane layer. (b) Optical micrograph of diodes fabricated by the method shown in Figure 1 after removal of the polyurethane layer. The reservoir was held at 40 °C, and a needle valve was used to regulate the water vapor flow. The argon and hydrogen flow rates were maintained at 35.0 and 20.0 sccm, respectively, using MKS mass flow controllers. Secondary ion mass spectroscopy (SIMS) data were obtained using a Cameca ims Sf secondary ion mass spectrometer equipped with a resistive anode encoder for position-sensitive ion counting. The ion beam used for the analysis was a 14.5 keV Cs+ beam. Negative secondary ions were detected. Auger electron spectroscopy (AES) was performed with a PHI 660 Scanning Auger multiprobe. The sputter-depth profile was acquired using a 10 keV electron gun to stimulate Auger electron emission and a 1 keV Ar+ ion gun with a current density of 32 µA/cm2 for sample sputtering. Due to the potential for destruction of the polymeric film during data acquisition, AES was performed on unpatterned samples that were otherwise subjected to identical processes and conditions to those for the patterned diode samples. Rutherford backscattering spectrometry (RBS) was used to characterize the platinum-silicon interface using a 2 MeV He+ ion beam, with a backscattering angle of 150°. The sample was positioned 7.5° off-normal to the beam. Film composition and thickness information was obtained from RBS data using a commercially available simulation package (RUMP, v. 3.51, Computer Graphics Service). Due to the large cross-sectional area (1 mm2) of the ion beam used for RBS, these studies were performed on unpatterned samples that were otherwise subjected to identical processes and conditions to those for the patterned diode samples.
Results and Discussion Figure 1 summarizes the fabrication scheme used in this study. The essential steps include (1) polymer template fabrication by MIMIC, (2) oxide wet etch, and (3) direct Pt metalization to form a patterned array of rectifying Pt/PtxSiy/Si contacts. Although not shown in the figure, the polyurethane template can be removed (as is described below). The micrograph shown in Figure 2 reveals the pattern features of the cured polyurethane template obtained by MIMIC. The mask used to construct the master for this work defined the contact level in a three-level architecture used earlier to construct MOSFET devices on a silicon wafer.6
Figure 4. Surface profile taken across a step from the metalized substrate surface to a bare substrate region.
Immersion of the templated Si wafer in the wet etch bath for 2.5 min at room temperature sufficed to strip the 1500 Å thermal oxide. The buffered HF etch on Si(100) yields a faceted surface that is imperfectly passivated by Si-H groups.16 The presence of water vapor in the CVD chamber, which is used as a nucleation promoter, causes some oxide regrowth on the Si surface and likely contributes to the oxygen content in the silicide film detected by AES. The polyurethane mask serves as an excellent template for the directed CVD of Pt from Pt(hfac)2. As suggested by the image shown in Figure 3a, at least 800 Å of Pt can be deposited without a loss of selectivity or fidelity, and without degradation of the patterned features. A repre(16) Higashi, G. S.; Chabal, Y. J.; Trucks, G. W.; Raghavachari, K. Appl. Phys. Lett. 1990, 56, 656.
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Figure 5. (a) SIMS image of a patterned region. Areas of high platinum concentration appear bright. The numbers given on the scale bar are counts per second. (b) SIMS image of the same region as shown in part a. Areas of high carbon concentration appear bright. The numbers given on the scale bar are counts per second.
sentative image of the patterned sample after the removal of the polyurethane layer is shown in Figure 3b. To obtain this image, the polyurethane layer was removed in two steps. First, the sample was immersed in a furfuryl alcohol solution (Summers Laboratories, Lens Bond Decementing Agent) at 160 °C for 10 min. In this manner, the polyurethane layer was loosened from the substrate and was subsequently removed by mild mechanical abrasion. The diodes on the substrate were protected from damage by the thick field oxide layer that protrudes above the platinum contacts and isolates each device. Finally, the substrate was rinsed in acetone and 2-propanol at room temperature. While this removal method was relatively convenient for this demonstration, it has obvious limitations. We are currently investigating alternative resins for MIMIC that can be ashed effectively after a hightemperature treatment. One noted concern about MIMIC, namely the possibility of unreacted prepolymer contaminating the wafer by seeping under the contact regions of the mold, did not appear relevant to the fabrication carried out in this work. Such residues, which can be removed by reactive ion etching, may have been stripped by the wet etching step. The devices characterized in this study were fabricated as described in the Experimental Section, typically yielding a formal mass coverage of Pt of 800 Å after a 60 min deposition. Figure 4 shows a representative surface profilometry trace measured on an unpatterned sample that was subjected to identical processes and conditions to those for the patterned diode samples. A section of this sample was physically masked to prevent the deposition of platinum. The sharpness of the step edge profile is, as always, limited by the profile of the profilometer tip. As suggested by the curve, the Pt surface obtained by CVD is quite rough.13,17-19 Since the growth process is ac(17) Kwak, B. S.; First, P. N.; Erbil, A.; Wilkens, B. J.; Budai, J. D.; Chisholm, M. F.; Boatner, L. A. J. Appl. Phys. 1992, 72, 3735.
companied by interfacial reactions (see below), the mass coverage value cited is approximate. The selectivity of the Pt CVD process was confirmed by secondary ion mass spectrometry (SIMS). The SIMS images shown in Figure 5 show the contrast seen between the reactive (Pt on bare Si) and template (polymer only) areas of the substrate after depositing the Pt. For purposes of contrast, we show images taken near the center of the pattern, where several different features could be included in the SIMS image field. Figure 5a shows an image constructed using the m/e ) 194.9216 negative-ion yield. The metalized regions appear bright, with dark areas being those where little or no platinum is present. Figure 5b shows an image of inverted contrast constructed using the m/e ) 11.9482 ion yield. Here, the carbon-containing (polymeric) regions appear bright and the Pt areas dark. In addition to confirming the selectivity of the deposition, the SIMS images reveal the integrity and definition of the pattern even after being subjected to concentrated oxide etchant solution and heating in the CVD process. We should note that the heating of the polymer does significantly increase the difficulty of removing it. The plasma ashing rate of this polyurethane is quite poor, being significantly slower than can typically be achieved with traditional photoresist removal. Under more rigorous conditions, as noted above, the polymer can be removed by chemical-mechanical means, however. Electrical characterization revealed the expected diode behavior of the structures, as shown by the data presented in Figure 6. All of the devices tested displayed similar characteristics. Parts a and b of Figure 6 show the I-V (18) Vellaikal, M.; Streiffer, S. K.; Woolcott, R. R., Jr.; Kingon, A. I. In Polycrystalline Thin Films: Structure, Texture, Properties, and Applications II, Materials Research Society Symposium Proceedings, Vol. 403; Frost, H., et al., Eds.; Materials Research Society: Pittsburgh, PA, 1996; p 27. (19) Xue, Z.; Strouse, M. J.; Shuh, D. K.; Knobler, C. B.; Kaesz, H. D.; Hicks, R. F.; Williams, R. S. J. Am. Chem. Soc. 1989, 111, 8779.
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a
b
c
Figure 6. (a) Diode current versus voltage behavior under forward bias. (b) Diode current versus voltage behavior under reverse bias. (c) Diode capacitance versus voltage behavior under reverse bias.
Figure 7. Auger sputter-depth profile of the platinum-silicon interface.
characteristics of a representative device under forward and reverse bias, respectively. Figure 6c shows the measured capacitance as a function of voltage in the reverse-bias regime. Diode capacitance under reverse bias is typically dominated by the capacitance at the metallurgical junction, which is an important parameter in circuit applications and can be used to calculate a doping concentration profile in the silicon if it is unknown. The behavior seen in Figure 6 corresponds to that expected for a rectifying contact.1 These data thus reveal the utility and compatibility of soft lithographic patterning and additive metallization techniques in the fabrication of simple microelectronic devices. Though achieving minimal device size was not a goal of this effort, further reduction in device size appears feasible using this combination of techniques. We now consider the structure of the Pt-Si contact interface. Characterization of the metal-silicon interface by RBS and Auger sputter-depth profiling yielded surprising results. Previous studies have shown that, following annealing at 300 °C, the physical deposition of thin platinum films on silicon substrates yields well-defined platinum silicide films. The depositions yield Pt2Si and, subsequently, PtSi layers via sequential interdiffusion processes.12,20-23 Our data, however, suggest the presence of a graded interface, with the Pt composition gradually decreasing from a near-surface concentration of 70 atomic % to below 5 atomic % 1500 Å below the surface. The form of this compositional gradient is shown by the Auger depth profile given in Figure 7. The oxygen gradient is abrupt, suggesting either oxidation at the surface after the removal of the sample from the growth chamber or segregation of oxygen impurities to the surface during growth. Through a much greater depth, though, the silicon concentration (20) Murarka, S. P. Silicides for VLSI Applications; Academic: Orlando, FL, 1983. (21) Crider, C. A.; Poate, J. M.; Rowe, J. E.; Sheng, T. T. J. Appl. Phys. 1981, 52, 2860. (22) Ottaviani, G. J. Vac. Sci. Technol. 1979, 16, 1112. (b) Canali, C.; Catellani, C.; Prudenziati, M.; Wadlin, W. H.; Evans, C. A., Jr. Appl. Phys. Lett. 1977, 31, 43. (23) Nicolet, M.-A.; Lau, S. S. Formation and Characterization of Transition-Metal Silicides. In VLSI Electronics: Microstructure Science; Einspruch, N. G., Larrabee, G. B., Eds.; Academic: New York, 1983; Vol. 6, p 330. (b) Ottaviani, G.; Mayer, J. W. Silicide Formation. In Reliability and DegradationsSemiconductor Devices and Circuits; Howes, M. J., Morgan, D. V., Eds.; Wiley: Chichester, 1981; p 105.
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In light of the different experimental procedure used, our data are qualitatively consistent with the results of this earlier study. The RBS results shown in Figure 8a are in qualitative agreement with the insights obtained from Auger depth profiling, though the quantitative analysis obtained from the RBS data simulation (Figure 8b) differs significantly. While we do not have a complete understanding of the origin of this quantitative discrepancy at present, the qualitative agreement remains, namely that the deposition yields a graded interface. The quantitative aspects of the RBS simulation shown in Figure 8b deserve specific comment. First, we note that no fits are possible using only planar slabs of known platinum silicide phases. The gradient profiles also could not yield a convergent simulation without using a second gradient of a low-z component, a difficulty also noted by Kwak et al., who used a quartz substrate.17 The fit shown in Figure 8b used oxygen for this purpose, although carbon could have been used as well. We believe that this profile is nonphysical, primarily because it contradicts the very clear profiles obtained by Auger sputter-depth profiling. We simply note, then, that other structural heterogeneities may be contributing here in ways that we have not been able to model. A degree of surface roughness was confirmed by SEM prior to analysis, but it is not clear whether it is sufficient to account for the differences seen between the RBS and AES data. It is also possible that the CVD-mediated reactions are run under conditions of kinetic control not related strictly to transport. The grain structures of CVD Pt films are known to be quite complex,13,17,18,20 and it is possible that a significant fraction of voids may be present. Such structural issues would complicate the quantitative RBS analysis.
Figure 8. (a) Rutherford backscattering raw data with a simulated spectrum overlaid. (b) Depth profile generated from simulation parameters used to fit the data in part a. Atomic percentages may not total 100% due to the simulation of voids within the film.
increases gradually from a near-surface concentration of 70 atomic % to an essentially bulk limit near depths of ∼1500 Å beneath the surface. The data do not show plateaus for compositions that might be expected for sequentially transforming films of Pt2Si and PtSi, although the near-surface composition of Si is similar to that of Pt2Si. In a previous study of CVD-grown platinum silicides, Morabito and Rand grew 800 Å of Pt on a Si substrate by CVD at 225 °C and obtained composition profiles with significant concentration gradients of Pt and Si; welldefined silicide phases wereobtained after annealing at 450-625 °C.24,25 We found that a separate annealing step was not necessary to form a rectifying contact and therefore was not used as a necessary step in the fabrication scheme. (24) Morabito, J. M.; Rand, M. J. Thin Solid Films 1974, 22, 293.
Acknowledgment. This work was supported by the National Science Foundation (Grant CHE-9626871), the Department of Energy (Grant DEFG02-91-ER45439), and the Defense Advanced Research Projects Agency (Grant N66001-98-1-8915). RBS, SIMS, AES, and surface profilometry studies were carried out in the Center for the Microanalysis of Materials, University of Illinois, which is supported by the U.S. Department of Energy under Grant DEFG02-91-ER45439. Electrical characterization was performed at the Microelectronics Laboratory and at the Integrated Circuits Fabrication Laboratory, operated by the University of Illinois Department of Electrical and Computer Engineering. We are especially grateful to Edward Lang and Brad Clymer for their assistance with RBS and to Dane Sievers and Anu Mahajan for their help with electrical characterization. Nancy Finnegan and Judith Baker were very helpful with Auger and SIMS data acquisition and analysis. Special thanks goes to Noo Li Jeon for his help with fabricating masters for the mold pattern. M.K.E. acknowledges a fellowship from the Department of Chemistry. LA9812222 (25) Rand, M. J.; Roberts, J. F. Appl. Phys. Lett. 1974, 24, 49. (b) Rand, M. J. J. Electrochem. Soc. 1973, 120, 686.
