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Charge Transfer-Induced P-type Channel in MoS Flake Field Effect Transistor Sung-Wook Min, Minho Yoon, Sung Jin Yang, Kyeong Rok Ko, and Seongil Im ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.7b15863 • Publication Date (Web): 10 Jan 2018 Downloaded from http://pubs.acs.org on January 10, 2018

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ACS Applied Materials & Interfaces 1

Charge Transfer-Induced P-type Channel in MoS2 Flake Field Effect Transistor Sung-Wook Min‡, Minho Yoon‡, Sung Jin Yang, Kyeong Rok Ko and Seongil Im* Institute of Physics and Applied Physics, Yonsei University, Seoul, 120-749, Korea

KEYWORDS: charge-transfer, p-channel, n-channel, transition metal dichalcogenide, twodimensional semiconductor, MoS2, IGZO, field-effect transistor.

ABSTRACT

Two-dimensional (2D) transition-metal dichalcogenide semiconductor (TMD), MoS2 has received extensive attention for decades due to their outstanding electrical and mechanical properties for next generation devices. One weakness of MoS2, however, is that it only shows n-type conduction revealing its limitations for homogeneous PN diodes and complementary inverters. Here, we introduce a charge-transfer method to modify the conduction property of MoS2 from n- to p-type. We initially deposited n-type InGaZnO (IGZO) film on top of MoS2 flake, so that electron charges might be transferred from MoS2 to IGZO during air ambient annealing. As a result, electron charges were depleted in MoS2. Such charge depletion lowered MoS2 Fermi level, which makes hole conduction favorable in MoS2 when optimum source/drain electrodes with high work-function are selected. Our IGZO-supported MoS2

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flake field effect transistors (FETs) clearly display the channel type conversion from n- to pchannel in this way. Under short and long annealing conditions, n- and p-channel MoS2 FETs are achieved, respectively and low voltage complementary inverter is demonstrated using both channels in a single MoS2 flake.

INTRODUCTION

Transition-metal dichalcogenides (TMDs) have shown outstanding properties, which are required for next generation devices for both electronics and optoelectronics.1-12 Among many of TMD semiconductors, MoS2 is the most famous and thus receiving extensive attention. Bulk hexagonal-structured (2H) MoS2 has a band gap of ~1.2 eV while one monolayer demonstrates a direct optical band gap of 1.8 eV.13-15 Toward its practical device applications, PN diodes,16-19 field effect transistors (FETs),1,2,20,21 and even complementary metal oxide semiconductor (CMOS) inverters22,23 have been reported. However, its conduction type was always n-type requiring other p-type TMD materials for PN coupling which is necessary for PN diode and CMOS inverter.16-19,22,23 Therefore, heterojunction PN diode or hetero CMOS devices have generally been reported.16-19,22,23 The charge carrier polarity (n-type) of this material could be seldom changed by either gate voltage or high work function metal contact in metal insulator FET (MISFET) form because its band gap is quite large13-15 and strong Fermi level pinning in the metal/2H-MoS2 exists.24,25 P-type conduction in MoS2 is difficult to obtain in general, although a few cases using MoOx,26 surface plasma,27 and chemical doping28,29 might be seen in report.


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In the present study, we introduce another novel way to make p-type channel in MoS2 FETs, which is charge transfer. We initially deposited n-type InGaZnO (IGZO) film on top of MoS2 flake, so that electron charges might be transferred from MoS2 to IGZO during air ambient annealing. As a result, electron charges were depleted in MoS2. Such charge depletion lowered MoS2 Fermi level, which makes hole conduction favorable in MoS2 when optimum source/drain electrodes with high work-function are selected. Our IGZO-supported MoS2 flake FETs clearly displayed the channel type conversion from n- to p-channel in this way. Under short and long annealing conditions, n- and p-channel MoS2 FETs are achieved, respectively and low voltage complementary inverter is demonstrated using both channels in a single MoS2 flake. We regard that this n- to p-channel conversion based on charge transfer may be one of the most convenient and novel methods for conduction type change.

RESULT AND DISCUSSION Figure 1a shows optical micrograph images of our bottom gate MoS2 flake FET with a top IGZO layer. The channel width and length of the FET are 31.6 and 6.2 µm, respectively. The thickness of the MoS2 flake appears as thick as 123.7 nm when obtained from atomic force microscopic measurement (AFM; Figure 1b). Schematic cross section is illustrated in Figure 1c, where a hydrophobic 300 nm-thick BCB organic layer is noted as inserted between 285 nm-thick SiO2 and MoS2 to reduce the channel/dielectric interface trap density. (As a result, the geometric dielectric capacitance was as small as ~ 4.8 nF/cm2 due to the increased thickness. More details of BCB dielectric are in Methods) Figure 1d-h presents the transfer characteristics (drain current-gate voltage; ID vs.VGS) of the n-channel MoS2 FET with Au source/drain electrodes. Prior to the deposition of the IGZO top layer (known as an n-type



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semiconductor30), the FET shows no remarkable gate modulation (Figure 1d) as shown in the transfer curves, due to the conductive characteristics of 123.7 nm-thick MoS2 flake. However, this conducting characteristic of the device dramatically changes to semiconducting by the deposition and subsequent annealing of 50 nm-thick IGZO top layer; post-anneal for 10 min at 300 °C in air ambient seems to bring optimum device performances of electron mobility of 24.4 cm2 V-1.s-1 along with an on/off current ratio of ~104 as shown in Figure 1e. Corresponding output characteristics (drain current-drain voltage; ID vs.VDS) are shown in Figure 1i. This change of gate modulation is highly regarded to originate from the charge transfer which might take place between the conducting MoS2 flake and the semiconducting n-IGZO top layer. It seems that charge carriers (electron) from the MoS2 flake are transferred into the IGZO top layer. Such directional charge transfer can take place if two conditions are met after IGZO deposition. Fermi level of MoS2 should be higher than that of n-IGZO and the electron carrier density of IGZO is lower than that of MoS2. Since the IGZO film was formed by sputter-deposition, the interface between IGZO and MoS2 may not be in perfect van der Waals interaction but includes some damage-induced defects even after annealing at 300 oC. As air ambient annealing continues at the temperature of 300 oC, IGZO becomes a more intrinsic semiconductor because O vacancies in IGZO becomes less in density filled by O atoms in air.31 Simultaneously, the charge transfer also continues and induces more serious charge depletion in MoS2, which initially leads to affordable n-channel state for gate modulation (Figure 1e and f) but later to ambipolar state (Figure 1g and h). We conducted Raman spectroscopy analysis on our thick MoS2 before and after IGZO deposition processes, and found that there was no spectral change after IGZO deposition and 300 oC annealing (supporting information 1 and Figure S1). To confirm the property change of top IGZO film according to annealing-induced O content, we investigated the transfer characteristics of


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IGZO FET as a function of annealing time at 300 °C in air ambient (relative humidity: RH ~ 45%). As revealed in literatures and also in our measurements (supporting information 2 and Figure S2), the conductivity of the IGZO film rapidly decreases from ~10 S/cm to ~ 1.2 × 106

S/cm after 10 min passes and further deceases to ~ 7.7 × 10-7 S/cm after 300 min, as

measured with van der Pauw samples for four probe measurement. Consequently, the linear electron mobility (peak mobility) of the MoS2 device rapidly decreases to 4.6 from 24.4 cm2 V-1.s-1 in 40 min and steadily decreases to 0.1 cm2 V-1.s-1 till anneal time reaches to 300 min, as seen in Figure 1j and k. These electron mobility degradation and appearance of ambipolar conduction due to charge transfer at the MoS2/IGZO heterojunction interface cannot be a good sign for n-type channel FET, however might rather be a good useful message for pchannel possibility. It is because p-channel MoS2 FET can be possibly realized if we change the source/drain contact electrode from Au to p-type favorable metal (such as Pt32,33). In fact, although ambipolar conduction in our MoS2/IGZO heterojunction FET is observed in Figure 1h, p-type conduction appears weaker than n-type one. This would be because Au shows Fermi-pinning with MoS2 surface and does more favor to n-channel MoS2 than to pchannel.24,25 Hence, it is also expected that strong p-type conduction in the MoS2/IGZO heterojunction FET could be obtained when high work function materials such as Pt (~ 5.5 eV)22 are used as source/drain electrodes. Figure 2a displays an optical micrograph image of our bottom gate MoS2/IGZO FET with Pt source/drain electrodes, which was prepared for p-channel FET experiments. The channel width and length of the FET are 28.4 and 5.3 µm, respectively. The thickness of the MoS2 flake was measured by atomic force microscopy, to be 49.0 nm (Figure 2b). The schematic cross section of the device is displayed in Figure 2c. Transfer characteristics of the MoS2/IGZO heterojunction FET with Pt source/drain electrodes are displayed in Figure 2e-h.



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The MoS2 FET without IGZO top layer exhibits poor n-type performance in the transfer curves of Figure 2d because of the work function mismatch between n-MoS2 and Pt contact,21 which also causes non-linear n-type output characteristics (Figure 2i). However, this inferior n-type transfer characteristic of the device is rapidly converted to the superior p-type transfer characteristic by the IGZO top layer and subsequent 10 min annealing (Figure 2e) which would cause the electron charge transfer from MoS2 to 50 nm-thick IGZO. Longer annealing strengthened such p-type conduction as evidenced in Figure 2f, g, and h for respective transfer curves of 40, 120, and 300 min-long annealed FETs. Figure 2j exhibits a typical strong p-type output curves of the MoS2/IGZO heterojunction FET as obtained after 300 minlong anneal. The hole mobility of the device significantly increases from 8 to 24.1 cm2 V-1.s-1 as annealing duration increases as plotted in Figure 2k and its inset. We summarized all the output characteristics of our Au and Pt contact FETs before and after IGZO deposition in Figure S3 to show their ohmic contact behavior. In fact, our p-type MoS2 FET surprisingly maintained most of its performance in air ambient even until 142 days and it is attributed to the encapsulation effects of IGZO as shown in Figure 2h. Moreover, it was also found with another MoS2 FET that the p-type FET behavior obtained through air ambient annealing could be changed back to n-type mode by N2 annealing (see Figure S4). For additional confirmation of n- and p-type channels in MoS2/IGZO FETs, capacitancevoltage (C-V) measurements on their best condition devices were carried out. As illustrated in Figure 3a, our C-V measurements use the same FETs by grounding the source electrode only. DC gate voltage sweep would not only cover source area capacitance but also eventually cover the capacitance of channel and drain electrode area: when DC voltage becomes large, the source and drain would be connected through the chargeaccumulated/conducting channel. Then, the capacitance (CS), which was under one electrode


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(source) for channel depletion, should be doubled-up by channel accumulation. Here, MoS2 channel is too small to be counted for capacitance, however, its conduction type can be clearly revealed. Bottom OM images of Figure 3a are those of FET with Pt contact as a measurement example. According to Figure 3b, 10 min-annealed MoS2/IGZO heterojunction FET with Au source/drain clearly shows n-channel behavior confirming I-V results of Figure 1e, while 300 min-annealed FET with Pt contacts also reveals p-channel as seen in I-V results of Figure 2h. For both cases, their total capacitances appear doubled-up during DC gate voltage sweep (from 23.9 to 48.3 nF for n-channel, from 31.6 to 57.4 nF for p-channel; difference between 23.9 and 31.6 nF may come from patterned area). Although any direct proof for the charge transfer mechanism is not provided but only indirect experimental findings, we here propose the charge transfer as one of the potential nto-p type conversion mechanisms illustrating the energy band diagrams for MoS2/IGZO heterojunction in Figure 4a-c. The electron affinities of MoS2 and IGZO are quite similar each other, to be ~4 and ~4.3 eV, respectively.34,35 However, their respective band gaps are very different (1.2 and ~3.1 eV for MoS2 and IGZO),13,14,35 so that the initial band diagrams of n-MoS2 and n-IGZO are suggested as in Figure 4a. During the air ambient thermal annealing on the heterojunction structure, the carrier concentration of the IGZO decreases with the increase of oxygen content.31,36 As a result, the Fermi level of the IGZO is lowered below the Fermi level of MoS2 (as indicated by yellow arrow in Figure 4a). Then, electrons in MoS2 should be transferred to IGZO for thermal equilibrium, and further annealing of the device drives the Fermi level of MoS2 to be lowered even below its intrinsic Fermi level as illustrated in Figure 4b and c. Hence, n-type conduction is readily prepared with Au after 10 min-short annealing (Figure 4b), but after 300 min-long annealing p-type conduction becomes more favorable. Since Au is ohmic-favorable for n-type MoS2,24,25 it cannot make p-



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type conduction even after 300 min annealing while p-type favorable electrode, Pt makes it very possible (Figure 4c). Based on conducted experiments and analysis, we finally fabricated low voltage operating MoS2/IGZO heterojunction FETs and complementary metal oxide semiconductor (CMOS) inverter, which use single MoS2 flake on glass substrate as shown in the OM view of Figure 5a. MoS2 flake thickness for these final devices was ~ 65 nm as measured from AFM scan (Figure 5b) and a 30 nm BCB/10 nm Al2O3 bilayer with a high capacitance of 142 nF cm-2 is used as a gate dielectric layer for 1 volt operation (see supporting information 5 and Figure S5 for the thin dielectric capacitance). Figure 5c and d show the transfer characteristics of MoS2–based FETs with Au and Pt source/drain electrodes, respectively. Before IGZO top layer deposition, the both FETs exhibit n-type conduction characteristics (black lines), however, after the IGZO deposition and subsequent thermal annealing for 40 minutes, n- and p-type FETs were obtained with Au and Pt electrodes, respectively (red lines). An optimum n-type channel was obtained from 10 min annealing of our FET device with Au electrode (blue lines). A primitive MoS2-CMOS inverter circuit was thus achieved through 40 min anneal which simultaneously produced n- and p-channel from the same MoS2 flake. Figure 5e shows a schematic cross section of the CMOS inverter, and Figure 5f displays the output curves of p- and n-channel MoS2 FETs as obtained from the same 40 min annealing. Our primitive CMOS successfully operates as shown in the voltage transfer characteristics (VTCs) of Figure 5g and its voltage gain appears to be ∼1.9 at a low supplied voltage (VDD = 1 V). Since we here did not focus on high performance CMOS inverter which should have its separate n- and p-channel in optimum condition, our CMOS circuit appears quite primitive in


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performance. However, it proves our concept that both of p- and n-channel MoS2 are possibly realized by charge transfer using IGZO top layer.



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CONCLUSION We have fabricated n- and p-type channel MoS2 FETs with Au and Pt source/drain electrodes, respectively, using IGZO layer on top of thick MoS2. Through the deposition of IGZO top layer and subsequent thermal annealing in air ambient at 300 oC, n-type conduction of MoS2 FETs has been converted to ambipolar or even p-type depending on source/drain contact electrode, as observed from I-V transfer and C-V characteristics. Such n- to p-type conversion in MoS2 channel is attributed to electron charge transfer from MoS2 to IGZO during air ambient annealing, as proposed with energy band diagrams for MoS2/IGZO heterojunction. Under optimum short and long annealing conditions, n- and p-channel MoS2 FETs are achieved with appropriate contact metal, respectively, reaching to a high mobility of 24.1 cm2 V-1.s-1. Low voltage operating FETs and complementary inverter could be demonstrated using both p- an n-channels of a single MoS2 flake on highly capacitive thin dielectric. We conclude that the charge transfer-based conduction type conversion is novel in view of using MoS2/IGZO heterojunction and also practically promising since MoS2 and IGZO are well known semiconductors.


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Methods The

300

nm-thick

hydrophobic

polymer,

BCB

[divinyl-tetramethyldisiloxane-bis

(benzocyclobutene), from Dow Chemical] was formed on 285 nm-SiO2/p+-Si substrate covered by spin casting and subsequent post annealing at 300 °C in N2 ambient for 10 minutes. Since 285 nm-thick SiO2 dielectric and 300 nm-thick BCB have their geometric capacitances as 12.1 nF/ cm2 and 7.6 nF/ cm2, BCB/SiO2 bilayer appears to have only 4.8 nF/ cm2, however, BCB was much useful to reduce gate hysteresis improving the mobility performance of FETs (see Figure S6). Thick MoS2 flakes were mechanically exfoliated with scotch tapes and were transferred on the substrate. The transferred MoS2 flakes underwent atomic force microscopy (XE-100, Park Systems) to define thickness and were exposed at 532 nm laser of Raman spectrometer (LabRam Aramis, Horriba Jovin Yvon) for identification of the flakes. The Au or Pt electrodes with thickness of 50 nm are deposited by DC sputtering and these electrodes are defined by conventional photolithography and lift-off processes. A 50-nm thick IGZO top layer is finally deposited on the MoS2 channel by RFsputtering and patterned with a shadow mask. Device annealing was conducted at 300 oC in air ambient (RH ~45%). For CMOS inverter and low voltage FETs, 30 nm-thin BCB on 10 nm-thin atomic layer deposited Al2O3 was formed on patterned Au gate on glass substrate (Figure 5a). The current-voltage measurements on the MoS2-IGZO transistors are conducted with a semiconductor parameter analyzer (HP4155C, Agilent Technologies) and the capacitance-voltage (C-V) measurements on the transistors are carried out with a LCR meter (HP4284A, Agilent Technologies). Capacitance-voltage measurement is executed at 10 kHz for both the Au and Pt contact devices.



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ASSOCIATED CONTENT Supporting Information Raman Spectra of MoS2 bulk and MoS2/IGZO heterostructures; Conductivity of IGZO film according to annealing time at 300 °C in air ambient; Transfer and output characteristics of MoS2 transistors without and with finally annealed IGZO top layer; Transfer characteristic of MoS2/IGZO transistors according to sequential annealing conditions (MoS2 only, MoS2/IGZO annealed in air ambient and annealed annealing in N2); The geometrical capacitance of the 30 nm-BCB/10 nm-Al2O3 dielectric; Hysteresis reduction effect of BCB layer. The material is available free of charge via the Internet at http://pubs.acs.org.

AUTHOR INFORMATION Corresponding Author *E-mail [email protected]. Tel: +82-2-2123-2842. Fax: +82-2-392-1592. Author Contributions The manuscript was written through contributions of all authors. All authors have given approval to the final version of the manuscript. ‡ Sung-Wook Min and Minho Yoon contributed equally. Notes The authors declare no competing financial interest.

ACKNOWLEDGMENT


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The authors acknowledge the financial support from NRF (NRL program: Grant No. 2017R1A2A1A05001278, SRC program: Grant No.2017R1A5A1014862, vdWMRC center), Creative Materials Discovery Program through NRF funded by the Ministry of Science, ICT and Future Planning (Grant No. 2015M3D1A1068061). M.Y. acknowledge the support from NRF (Grant No. 2017R1A6A311034195).



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FIGURES

Figure 1. (a) Optical microscopic (OM) image of MoS2/IGZO FET with Au source and drain electrodes. Width and length of the MoS2 channel are determined as about 31.6 and 6.2 µm, respectively. (b) Height profile (~ 123.7 nm) and three dimensional AFM image (inset) of MoS2 channel (Scan direction is shown in Figure 1(a)). (c) Schematic cross section of the MoS2/IGZO FET with Au contact. (d) Transfer characteristics (VDS = 0.1 V) of MoS2 only


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FET. (e-h) Transfer characteristics (VDS = 0.1 V) of MoS2 / IGZO heterojunction FET annealed for 10 minutes, 40 minutes, 120 minutes, and 300 minutes at 300 °C in air ambient. (i) Output characteristics and (j) linear mobility curve of 10 min-annealed MoS2 / IGZO FET. (k) Field-effect electron mobility changes according to annealing time. Inset: linear mobility plots of MoS2 / IGZO FET annealed for 10, 40, 120, and 300 min at 300 °C in ambient.



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Figure 2. (a) OM image of MoS2/IGZO FET with Pt contact electrodes. The MoS2 channel has 28.4 µm-width and 5.3 µm-length. (b) Height profile (~ 49.0 nm) and three dimensional topographic image (inset) of MoS2 channel (Scanned line is indicated in Figure 3(a)). (c) Schematic cross section of the MoS2-IGZO FET with Pt contact. (d) Transfer characteristics (VDS = 0.1 V) of MoS2 only FET. Transfer characteristics (VDS = -0.1 V) of MoS2/IGZO heterojunction FET annealed for (e) 10 minutes, (f) 40 minutes, (g) 120 minutes, and (h) 300


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minutes at 300 °C in ambient (the state was mostly maintained even till 142 days). Output characteristics of (i) MoS2 only and (j) MoS2/IGZO heterojunction FETs. (k) Field-effect hole mobilities of MoS2/IGZO FET as a function of annealing time (at 300 °C, air ambient).



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Figure 3. (a) Circuit schematic and device image for C-V measurements on MoS2-IGZO FETs. When the channel is depleted, a capacitance (CS) is measured from the dielectric area under only source electrode, however the capacitance is doubled when the channel is accumulated. The accumulated channel would electrically connect the source and drain. The channel area (~less than 140 μm as seen in the inset OM) for Cch (channel capacitance) is negligible compared to that of an electrode which is ~4.55 10 μm . Green square is a patterned IGZO. (b) Result of capacitance measurements on n-MoS2/IGZO FETs with Au contact after post annealing for 10 min. (c) Capacitance-voltage plot of p-MoS2/IGZO FETs with Pt contact after post annealing for 300 min. Capacitance-voltage measurement is executed at 10 kHz for both the Au and Pt contact devices.


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(a)

4 "#

(b) Good injection for electrons

, ,

(c)

4.3 "#

,

Poor injection for electrons

, ,

Au ,

())"*+,)-

,

,

,

$ , 1.2 eV

, ,

, ,

,

, Pt $ ,

3.1 eV

Poor injection for holes

,

,

IGZO

,

,

,

, MoS2

Good injection for holes

Contact

MoS 2/IGZO

, Contact

MoS2/IGZO

Figure 4. (a) Each energy band diagram of MoS2 channel and IGZO film. The post-annealing lowers Fermi level of IGZO film as indicated by thick arrow. After forming MoS2/IGZO heterostructure, the Fermi level (Ef) of MoS2 also decreases with ambient annealing due to charge transfer. According to the energy band diagrams of (b) and (c), initial n-type conduction in MoS2 is converted to p-type as annealing elapses. The 10 min- and 300 minlong anneals thus result in n- and p-type conductions, respectively as determined by the location of intrinsic Fermi level (Ei). Au contact is favorable to n-type while Pt contact is to p-type, as illustrated.



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Figure 5. (a) OM image of two MoS2 FETs with Au or Pt contacts in single MoS2 flake. (b) The thickness of MoS2 is determined as ~ 65 nm. Transfer characteristics MoS2 FETs with (c) Au and (d) Pt contact. IGZO top layer was annealed for 10 min and 40 min at 300 °C in ambient for each measurement. (e) Schematic cross section of CMOS inverter which possibly works on the single flake. For low voltage operation, thicknesses of Al2O3 and BCB were reduced to ~10 and ~30 nm, respectively. (f) Output characteristics of MoS2/IGZO FET Pt and Au contact annealed for 40 min. (g) Voltage transfer characteristics and voltage gains obtained under VDD = 0.2, 0.6 and 1 V. Inset shows CMOS circuit.


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Flake Field Effect Transistors - ACS Publications - American Chemical

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