Fully 'Erase-free' multi-bit operation in HfO2 based resistive switching

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Functional Inorganic Materials and Devices

Fully ‘Erase-free’ multi-bit operation in HfO2 based resistive switching device Jin Joo Ryu, Kanghyeok Jeon, Seungmin Yeo, Geonhee Lee, Chunjoong Kim, and Gun Hwan Kim ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.8b20035 • Publication Date (Web): 01 Feb 2019 Downloaded from http://pubs.acs.org on February 6, 2019

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ACS Applied Materials & Interfaces

Fully ‘Erase-free’ multi-bit operation in HfO2 based resistive switching device Jin Joo Ryu1,2‡, Kanghyeok Jeon1,2‡, Seungmin Yeo1,3‡, Geonhee Lee1, Chunjoong Kim2* and Gun Hwan Kim1* 1

Division of Advanced Materials, Korea Research Institute of Chemical Technology (KRICT)

141 Gajeong-Ro, Yuseong-Gu, Daejeon 34114, Republic of Korea 2

Department of Materials Science and Engineering, Chungnam National University, Daejeon

34134, Republic of Korea 3

School of Electrical and Electronic Engineering, Yonsei University, Seodaemun-gu, Seoul

03722, Republic of Korea *

Correspondence and requests for materials should be addressed to C. Kim. (email:

[email protected]) or to G. H. Kim (email: [email protected])

KEYWORDS resistive switching, multi-bit operation, erase-free, W electrode, energy-efficient

ACS Paragon Plus Environment

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ABSTRACT

Fully ‘Erase-free’ multi-bit operation was demonstrated in a W/HfO2/TiN stacked resistive switching device. The term ‘Erase-free’ means that a digital state in multi-bit operation can be achieved without initializing the device resistance state when the device moves to another digital state. Because initializing the resistance state of a resistive switching device causes high energy consumption, omitting this sequence can achieve energy efficient multi-bit operation during rewriting of the resistance state of device. Experimentally, an operational energy savings of up to 75% was confirmed. For stable and reliable ‘Erase-free’ operation, several prerequisites are required, such as gradual resistance change with electric pulse stimuli during both writing and erasing, predictable operational voltages for certain resistance states, and high reliability of resistive switching. These prerequisites could be achieved by adopting a W top electrode in a W/HfO2/TiN stacked resistive switching device. These results can pave the way to future nonvolatile memory applications.


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Introduction Metal-oxide based resistive switching (RS) technology has been regarded as a leading candidate for future non-volatile memory (NVM) applications, i.e., resistive switching random access memory (ReRAM), because of its superior electrical characteristics such as low energy consumption, fast operation speed, high re-writability up to 1012 cycles, and simple 2-terminal structure (Metal-Insulator-Metal, MIM). 1-5 After L. Chua established the theory of memristors 6 and Hewlett-Packard Lab experimentally demonstrated memristive properties in TiO2-based devices,

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an enormous number of metal-oxide materials have been reported for ReRAM

applications. Among them, Ta2O5 and HfO2 have shown excellent performance and reliability, and currently these two materials are considered as the most promising candidates for ReRAM. 7-12 Meanwhile, to compete with currently available commercial memory devices, such as NAND FLASH memory or dynamic random access memory (DRAM), ReRAM devices with higher-end performance and operational reliability must be developed. For example, multi-bit operation, which means the ability to possess more than one bit (a digital state of ‘0’ or ‘1’) in one particular memory cell is essential for developing highly integrated memory devices. Up to now, many researchers in related fields have made great efforts to achieve reliable multi-bit operation in an RS device, and notable results have been reported.5, 12-17 For example, bi-layered RS devices such as ZrO2/HfO2 18, TiO2/HfO2 19, and Ta2O5/HfOx 20 were examined for 2 or 3-bit operation. Although the improved multi-bit operation was shown in previous literatures, the state-overlapprobability (SOP) and energy efficient state control were not considered seriously. In this point of view, there are some issues which remain to be solved before ReRAM can be adopted in standalone memory devices. First, the individual resistance states in a multi-bit RS operation should maintain a sufficiently low SOP so that they are not misread during a reading operation. Because


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the RS operation has a stochastic nature,

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a finely distinguishable SOP cannot be easily

achieved, especially when the RS device has an insufficient total available current range and a higher level of multi-bit RS operation is required. To overcome this difficult problem, Kim et al. reported an operational method which is called incremental step pulse programming (ISPP) and error check and correction (ECC), and successfully achieved 4-bit (16 resistance states in one RS device) operation in a HfO2 based RS device. 23 With this method, the SOP could be adjusted as desired, and an SOP of up to 6σ (in a Gaussian distribution) was demonstrated. However, in Kim’s research, the energy efficiency during the ISPP/ECC operation was not seriously considered. Although the SOP can be controlled by using the ISPP/ECC method, the individual ISPP/ECC sequence consumes a significant amount of energy during the repetitive writing/erasing and verifying processes. This problem was mainly caused by the ‘abnormal case’, which refers to a situation in which the resistance state of an RS device is out of its target range during the ISPP/ECC processes. In this case, the resistance state of the RS device should be initialized to an original resistance state and the ISPP/ECC process can then be resumed. This is the second issue to be solved. Ryu et al. utilized a thin Al2O3 layer between the top electrode and RS layer and found that the number of occurrences of the ‘abnormal case’ during multi-bit RS operation could be reduced significantly. Because the inserted Al2O3 layer plays the role of a load resistor, the operational voltage margin increased compared to the case without an Al2O3 layer. 24 In Ryu’s report, however, the ‘writing’ based multi-bit RS operation was only possible because Ryu’s RS device exhibited abrupt resistance variation in the erasing operation, which could not provide a large enough voltage margin to achieve gradual erasing. Motivated by the results described above, to achieve more energy efficient multi-bit RS operation, an ‘Erase-free’ based operation was developed in this work. The term ‘Erase-free’


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means that a certain digital state in multi-bit RS operation can be achieved without initializing the resistance state of the RS device when the device moves to another digital state. For example, in 2-bit operation, there are 4 possible digital states (00, 01, 10, and 11). Assume that each resistance state refers to a descending sequence from ‘00’ to ‘11’. In the case of ‘non Erase-free’ operation, to rewrite the resistance state from ‘10’ to ‘01’ a two-step operation should be performed, i.e., ‘10’ → ‘00’ (reference state) → ‘01’. In the case of ‘Erase-free’ operation, however, the direct resistance transition from ‘10’ to ‘01’ is possible. To achieve ‘Erase-free’ multi-bit RS operation, the resistance variation of an RS device should be sufficiently gradual in both writing and erasing processes. If the resistance is changed abruptly during the operation with external electric pulse stimuli, the intermediate resistance state cannot be achieved, and an initializing process must be accompanied to program the new resistance state. In this research, fully ‘Erase-free’ based multi-bit RS operation was achieved using a W/HfO2/TiN stacked RS device with a 100 ns-long electric pulse, and an energy efficiency of up to 75% as confirmed compared to ‘non Erase-free’ operation. This efficiency is attributed to the oxidized W, which can form an oxygen-deficient layer near the W/HfO2 interface. The detailed experimental results and discussions are provided below sequentially. First, the W/HfO2/TiN stacked RS device was analysed in terms of its material properties. Second, the electrical performance during 3-bit operation, electrical measurement conditions, and relative energy efficiency of the W/HfO2/TiN stacked RS device were investigated. The overall results of this study might be a positive step forward to commercialization of ReRAM for future NVM applications.


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Result & Discussion

Structural analyses of W/HfO2/TiN stacked RS device

The tested RS device structure is shown in Figure 1(a) which was investigated by atomic force microscopy (AFM) analysis. The W top electrode (TE) and TiN bottom electrode (BE) cross perpendicularly with each other. The individual metal lines of TE and BE were defined to be 2 μm in width, and consequently, the active area of the cross-point junction is 4 μm2. While the TiN BE showed a rectangular shaped morphology, the W TE showed a rounded shape. This originates from the difference in the fabrication processes of the TE and BE. The dry-etched TiN BE has a finely defined 2-μm metal line width; on the other hand, the conventional lift-off processed W TE was formed with a slightly wider metal line width. This is a generally recognized discrepancy between dry-etching and lift-off processes. 25, 26 More detailed descriptions of the fabrication processes will be provided in the Method section. Figure 1(b) shows a cross-sectional image of the W/HfO2/TiN stacked RS device obtained from high-resolution transmission electron microscopy (HR-TEM) analysis. The 10-nm-thick HfO2 layer sandwiched between the W TE and TiN BE was observed finely (white arrows in Figure 1(b). The morphology of the deposited HfO2 resembles that of the TiN BE, which is a general characteristic of the atomic layer deposition (ALD) technique. It was noted that the W TE layer is composed of two distinguishable layers: a dark upper layer (~100-nm-thick) and a relatively bright lower layer (~100-nm-thick) (marked by yellow arrows in Figure 1(b).


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Considering the operational characteristics of HR-TEM, the bright region in the W TE layer can transmit a larger amount of accelerated electrons than the dark region, which suggests that the bright region has a higher oxygen concentration. The detailed explanation about HR-TEM analysis is included in Figure S1 (Supporting Information). Figure 1(c) shows the measured current-voltage (I-V) curves of the W/HfO2/TiN stacked RS device. During the electrical measurement, the W TE was biased while the TiN BE was electrically grounded. The resistance transition from a high resistance state (HRS) to a low resistance state (LRS) was observed in the positive bias region (SET). The reverse resistance transition (RESET) occurred in the negative bias region. Before the RS hysteresis was observed, there was an electro-forming step with a current compliance (CC) of 1 μA to make the RS device wake-up. It should be noted that the stable RS hysteresis of the W/HfO2/TiN stacked RS device was only observed in the counter-clockwise direction. Considering the n-type nature of HfO2 and oxygen mediated RS phenomena,

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it was thought that the W TE had a stronger oxygen

reservoir effect than that of a TiN BE. A more detailed discussion can be found in the Supporting Information (see Figure S2). It was also noteworthy that only applied-bias-controlled RS hysteresis was observed in both the SET and RESET processes. Because there is not CC function during the electrical pulse measurement, the RS device must exhibit ‘self-compliance’ characteristics to achieve reliable RS performance. As the applied bias was increased from 1.5 to 2.6 V in the SET process, the current of the LRS (verified at 0.1 V) increased gradually from 4 to 15 μA. This range is the total available current range for multi-bit RS operation in this study and was divided into 7 LRSs for 3-bit operation. (7-LRSs and 1-HRS) The inset of Figure 1(c) is a few selected I-V curves for SET operation. More obvious LRS resistance variation can be confirmed as the SET voltage increases.


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After every SET operation, the RESET operation was performed with a fixed voltage of -3.6 V. While the curves of LRSs in negative bias region split as a result of applied SET voltage variation, the HRS was maintained almost constantly. This means the total available current range up to 15 μA does not influence the rejuvenation of the HRS, which is one of the important aspects deciding the total available current range for multi-bit RS operation. If the HRS could not be restored to its original state by forming excessive LRS, reliable multi-bit RS operation would be impossible. The gradual resistance variation in both the SET and RESET processes shown in Figure 1(c) are essential characteristics for achieving fully ‘Erase-free’ multi-bit RS operation. If the resistance variation with applied bias is abrupt, the intermediate resistance state cannot be obtained stably because of a severely restricted programming voltage margin. It was thought that the W TE plays an important role as a load resistor due to its appropriate oxygen affinity. To investigate the structural material distribution of the W/HfO2/TiN stacked RS device, Auger electron spectroscopy (AES) analysis was conducted, and the results are shown in Figure 1(d). Each thin film layer in the W/HfO2/TiN RS device is well distinguished in the AES depth profile. Interestingly, the atomic concentration profiles of W and O crossed each other at almost the middle depth of the W TE layer, which is consistent with the HR-TEM observations in Figure 1(b). Except for the outer surface of the W TE, the relative oxygen concentration increases gradually while that of W decreases as the AES detecting position moves deeper into the layer. Although the qualitative chemical composition of the W TE at each depth position could not be determined from the AES analysis results, it was demonstrated that the bright region of the W TE in Figure 1(b) has a larger oxygen concentration than the dark region. Although some amount of oxygen concentration was revealed from AES analysis, it should be noted that the partly oxidized W TE can play a role of metal electrode. In previous report, Sun et al. had revealed the metallic


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characteristic of W even when it has a chemical composition of WO2.72.

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Considering the

stoichiometric tungsten oxide is WO3, a little deficiency of oxygen from WO3 layer can maintain the intrinsic metallic property. In addition, the W/TiN stacked device showed the electrical ohmic behaviour. (not shown here) The HfO2 layer was observed between the W TE and TiN BE, and the relative atomic concentrations of Hf and O were confirmed to be 33% and 66%, respectively, which means an almost stoichiometric HfO2 layer was formed by the ALD process. It should be noted that the TiN BE layer has an oxygen concentration of almost 20% through the whole thickness. This phenomenon is easily observed when the TiN layer is exposed to the atmosphere. Due to the columnar structure of the TiN BE layer, the columnar structured grain boundaries can serve as preferred oxygen diffusion paths.

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However, it was thought that the 20% oxygen

concentration in the TiN BE is not a critical amount when the TiN BE acts as an electrode. Considering the highly oxidizing nature of W, it is natural that there is an interfacial layer between W TE and HfO2 layer. In many previous reports, it was revealed that such an interfacial layer can play a role of series resistor and oxygen reservoir during RS. Li et al. reported that the interfacial TiOx layer inserted between Ta and Ta2O5 layer in Pt/Ta2O5/Ta stacked RS device can improve the RS uniformity due to series resistor effect which can prevent unwanted current flow during SET process.32 Moreover, it was also revealed that the interfacial TiOx layer can improve the endurance characteristic of RS device because of the role of oxygen source during RESET process. Wang et al. also reported that the RS behaviour can be varied as a function of interfacial layer type using Ta/Ta2O5/ Pt, Ta/Ti/Ta2O5/Pt, and Ta/Hf/Ta2O5/Pt stacked RS devices.33 The interfacial layer placed between Ta2O5 RS layer and Ta TE has a comparable resistance value with that of LRS, which can prevent the current overshoot during SET process.


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In identical point of view with previous reports, the interfacial layer between W TE and HfO2 layer can also play a role of series resistor in W/HfO2/TiN stacked RS device. It is thought that the physical characteristic (series resistor) of interfacial layer is maintained during RS, and it acts as a voltage divider, and make the gradual SET and RESET behaviour which is favourable for ‘Erase-free’ operation of this study. Electrical characteristics and 3-bit operation of W/HfO2/TiN stacked RS device Figures 2(a) and (b) show the current variation behaviours with sequentially applied positive (bias direction of SET) and negative (bias direction of RESET) bias, respectively. The insets in Figure 2(a) and (b) show schematics of the electrical measurement method. In the positive bias case, the 100 ns-long incremental electric pulses (0.1 V incremental voltage step) were applied to the TE of the RS device, and after every pulse the reading voltage of 0.1 V was applied to verify the resistance state of the RS device. Similar to the positive bias measurement, inversely decreased electric pulses and verifying biases were applied alternatively to monitor the resistance variation of the RS device. To achieve 3-bit operation, 7 LRSs and 1 HRS are required. Considering that the total available current range of our RS device is 4 ~ 15 μA, the entire range of individual states (called ‘levels’) in 3-bit RS operation could be ~ 1.5 μA. At this point, the SOP should be considered. That is, if the given current range of 1.5 μA was fully utilized as a certain specific level, the SOP would increase dramatically. To avoid this fatal situation, the given current range of 1.5 μA was divided into two regions, the target current range and the forbidden current range. The former is the available current range where a certain specific level can take the current value, the latter is a restricted current range. By using the forbidden current range, the SOP could be effectively reduced. In this work, the target current range and the forbidden current range were set to 0.5 and 1 μA (0.5 + 1 = 1.5 μA), respectively. Consequently, the target current ranges of the 7


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levels were set to 4 ~ 4.5, 5.5 ~ 6, 7 ~ 7.5, 8.5 ~ 9, 10 ~ 10.5, 11.5 ~ 12, 13 ~ 13.5 μA for level 1 (L1), L2, L3, L4, L5, L6, and L7, respectively. Now, to investigate the current variation behaviour of the SET and RESET processes, sequential electric measurements were conducted at each of the target current ranges. As expected in Figure 1(c), both SET and RESET showed sufficiently gradual current variation behaviours which are favourable for reliably achieving a certain current level during ISPP/ECC. However, obviously different characteristics were observed during the SET and RESET processes. In the case of SET operation, the gradually increasing current values overlapped in the increasing current region deviated from the starting current level, while the current values in the decreasing current region of the RESET operation did not. The reason for this phenomenon is introduced in Figure S3 (Supporting Information). This phenomenon means that the required SET voltage can be easily estimated when a certain level changes to another higher level. For example, when the L2 was subjected to change to L7, ~ 3.5 V of SET voltage is the expected value necessary to achieve L7. This expected value of ~ 3.5 V becomes almost constant regardless of the initial level. However, the situation becomes different in the RESET process. The expected RESET voltage will change as a function of initial level. For example, when the L4 was subjected to change to L2, a RESET voltage of ~ -3.8 V should be adopted. However, in the case of moving ‘from L7 to L2’, the expected RESET voltage will be ~ -4.5 V, even though the final level is still L2. From the viewpoint of device application, a programming voltage that varies with the initial level can be a great disadvantage to accurate RS device operation. To solve this problem, an experiment based expectation was performed. It should be noted that the ‘expectation’ is not any kind of theoretical model, but extracted from only I-V results.


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Figure 2(c) shows the ‘gradualness of RESET current’ and ‘RESET start voltage’ variation as a function of ‘current of state level’. The gradualness of RESET current stands for the slope of the I-V curve in RESET operation. One example is shown as a red dashed line in Figure 2(b). The RESET start voltage is the value of the intercept between the lines of the ‘gradualness of RESET current’ and ‘current of state level’ (as an example, the closed black circle in Figure 2(b)). Interestingly, both of these parameters exhibited an almost linear relationship with the current of state level. Due to this linear relationship, the values of gradualness of RESET current and RESET start voltage could be easily estimated for an arbitrary current of state level. Based on these two parameters, the expected I-V curve for RESET operation could be obtained. To confirm the consistency between the expected and experimentally measured I-V curves, 9 and 12 μA current of state levels, which are not the target current level in this 3-bit RS operation, were examined as an example. As shown in Figure 2(d), the expected and measured I-V curves agree well with each other, which means the required RESET voltage for state level movement can be easily estimated from a couple of preliminary I-V measurement. Using the demonstrated experimental expectation, multi-bit RS operation which has an arbitrary target current range and forbidden current range can be achieved reliably with expected operational voltage values. Figure 3(a) shows 3-bit RS operation results for the W/HfO2/TiN stacked RS device using the ISPP/ECC method. The ISPP/ECC method is explained in detail in previous reports. 23, 24 One notable difference between the previously and currently used ISPP/ECC methods is that the currently applied ISPP/ECC method utilizes the verifying steps not only in SET but also in RESET operation. By using the bi-directional ISPP/ECC method, ‘Erase-free’ based multi-bit RS operation was performed.


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Firstly, the sequential 7 levels were tested as shown in Figure 3(a). For each level, 100 RS cycles were attempted to confirm the statistical reliability, and each RS cycle was performed between the tested level itself and the HRS. The target current range of the HRS was set to 1.5 ~ 2 μA which is a sufficiently lower current range than that of L1. The operational voltages of the 7 levels and corresponding HRS were extracted during the measurements. The extracted voltage values are the very applied voltages achieving a certain target current range of SET or RESET during the ISPP/ECC operation. In both cases, the operational voltages of SET and RESET were consistently matched up with the experimental results in Figure 2(a) and (b), respectively. To evaluate the characteristic SOP between neighbouring levels, statistical analysis was performed. Assuming the current values obtained over 100 cycles of RS for each level follow a Gaussian distribution, the qualified SOP values could be evaluated by Equation (1) expressed below.

ܱܵܲ ൌ

௠మ ି௠భ ఙమ ାఙభ

(1)

where m and σ are average and standard deviation values of the current in a certain level, respectively. The physical meaning of Equation (1) is that as the difference in the average current values between neighbouring levels increases, and as the current standard deviations decrease, the SOP becomes large. As the SOP increases, the classification of levels in multi-bit RS operation becomes clearer. The evaluated SOPs are depicted in Figure 3(b), from 5.38 to 5.94. An SOP of 5.38 means the overlap probability is 3.7×10-6% (only 3 times in 108 cycles of operation), which


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stands for almost ‘non-overlap’. It was noted that the SOP between HRS and L1 has larger values than those of the 7-levels because the forbidden current range is large enough. One more important aspect of multi-bit RS operation is the reliability of individual levels. To confirm the reliability, retention and endurance characteristics were tested as shown in Figure S4 (Supporting Information) At last, ‘Erase-free’ based 3-bit RS operation was performed as shown in Figure 3(c). Firstly, the multi-bit RS operations between just neighbouring levels were performed. Due to the gradual current variation with applied electric pulses, stable and reliable RS between neighbouring levels could be achieved. If the current variation is abrupt, only the type of multi-bit RS operation shown in Figure 3(a) would be possible. However, the gradual current variation behaviours of SET and RESET can make reliable resistance transition between 7 levels possible without accompanying the HRS. Moreover, to confirm the randomized multi-bit RS operation, L4 ↔ L6, L2 ↔ L5, and L1 ↔ L6 were tested sequentially. As can be seen in the last 3 panels shown in Figure 3(c), the RS between arbitrary levels was also achieved reliably. The experimentally extracted operational voltage values are in good agreement with the experimental results in Figure 2(a) and (b). Finally, the operational energy efficiency was investigated in each case of Figure 3. The relative energy efficiency is defined by Equation (2) as follows.

ሺΨሻ ൌ

ா௡௘௥௚௬ಿ೚೙ಶೝೌೞ೐ష೑ೝ೐೐ ିா௡௘௥௚௬ಶೝೌೞ೐ష೑ೝ೐೐ ா௡௘௥௚௬ಿ೚೙ಶೝೌೞ೐ష೑ೝ೐೐

ൈ ͳͲͲ (2)


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To evaluate the energy of RS during ISPP/ECC, the values of current, voltage, RS time, and the number of ISPP/ECC operation are required. For this, the transient electric signal was detected by oscilloscope during ISPP/ECC. The detailed measurement circuit and signal analysis method have been well described elsewhere.

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It should be emphasized that the energy

efficiency can be differently evaluated even though the initial and final levels are identical because the number of ISPP/ECC operation might be different. Fortunately, in our measurements, the number of ISPP/ECC operation was less than 3 in almost measurement cases. This is due to the appropriate voltage step used in ISPP/ECC operation. The 10 mV incremental voltage step used can bring about ~150 nA of variation in a single electric pulse which is less than 500 nA of the target current range. (The gradualness of the RESET current in Figure 2(c) has a 15 μA/V as a maximum value. This means 150 nA of variation for every 10 mV voltage variation.) Consequently, ‘abnormal cases’ during the ISPP/ECC operation rarely occurred. Figure 4(a) shows the relative energy efficiencies of the ‘Erase-free’ and ‘Non Erase-free’ cases as schematically shown in Figure 4(b). Efficiencies from 14 to 75% were evaluated. As the levels of two targeted LRSs become higher, the higher energy efficiency was observed. This is because the higher levels of LRSs should accompany the larger operational energy of SET and RESET processes in ‘Non Erase-free’ case. Similarly, energy efficiencies from 52 to 74% were evaluated in randomized multi-bit RS operation, as shown in Figure 4(c). Because the ‘Erase-free’ based multi-bit RS operation does not accompany the HRS in ‘Non Erase-free’, the operational energy can be significantly saved. As shown in Figure 4(e) and (f), the two kinds of ‘Erase-free’ based multi-bit RS operation were investigated comparatively. One is direct and the other is sequential change between levels. Comparably, the direct change showed more than 20% energy efficiency. It was thought that


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because the sequential multi-bit RS operation requires an increased number of ISPP/ECC than the direct case, the direct change of levels can be an efficient way to achieve energy efficient and reliable multi-bit RS operation.

Conclusion In conclusion, ‘Erase-free’ based bi-directional, highly reliable, and operational energy efficient multi-bit RS operation was demonstrated for the first time. The key factor necessary for such an achievement is the appropriate material choice in the tested RS device, W/HfO2/TiN. The W has chemical characteristics suitable for oxidizing itself at the W/HfO2 interface where it plays an important role as an oxygen reservoir layer for reliable RS performance and an external load resistor for gradual current variation. One more important thing is the modified ISPP/ECC method that was utilized for ‘Erase-free’ based multi-bit RS operation. In previous reports, the unidirectional ISPP/ECC was used only because the previously tested RS devices did not have the bidirectional ‘self-compliance’ characteristic. In this work, however, to achieve ‘Erase-free’ based multi-bit RS operation, the bi-directional ISPP/ECC method for SET and RESET processes was adopted. Unfortunately, while the SET process showed almost constant operational voltage values for each level, the RESET process showed current of state level dependent variation in operational voltage. To solve this problem, the experimental expectation was performed, which could predict the operational RESET voltage for an arbitrary current of state level. This means that the various multi-bit RS operations which have different target and forbidden current ranges can be operated reliably due to the predictable operational voltage parameters. Of course, the utilization of the ISPP/ECC method can be an obstacle from the viewpoint of overall RS operation speed because


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the repetitive ECC during multi-bit RS operation can be a time consuming process. Considering the severely stochastic nature of RS devices, however, the most effective way for achieving high reliability and energy efficient multi-bit RS operation is utilizing the ISPP/ECC method. Meanwhile, the ‘Erase-free’ operation may be an inefficient way when it is adopted to NAND FLASH which utilizes page- or block-erase based operational scheme. However, considering the crossbar structured ReRAM, which is more like DRAM in regard to ‘random access’, it can be thought that the ‘Erase-free’ operation of individual memory cell in crossbar ReRAM may be useful. Multi-bit RS operation is an essential characteristic which is necessary for ReRAM devices to compete with or replace currently matured memory devices because higher-end memory performance and reliability can be a good motivation for chip-makers to adopt a manufacturing system. Although many previous reports have shown notable research results about multi-bit RS operation, reliable SOP and energy efficiency had not been achieved at the same time. From this point of view, the fully ‘Erase-free’ based multi-bit RS operation presented in this work can be a step forward to commercializing ReRAM for future NVM applications.

Method

Device fabrication


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A 200-nm-thick TiN layer was sputtered on a SiO2/Si substrate and patterned to a shape of crossbar-type BE. The TiN BE was patterned by a conventional photolithography and dry-etching process using an inductively coupled plasma (ICP) power of 200 Watts (W) and substrate bias power of 20 W. During the dry-etching process, the reactant gas flow rates of Ar and Cl2 were maintained at 50 standard cubic centimetres per minute (sccm) and 30 sccm, respectively. During the dry-etching process, the process temperature was maintained at 25 °C by a water-circulation cooling system. The observed etching rate was ~100 nm/min. The residual photo-resist (PR) on the patterned TiN BE was removed by acetone etchant and cleaned sequentially with isopropyl alcohol and deionized water. Then the blanket type 10-nm-thick HfO2 thin film layer was deposited by travelling wave-type ALD at 250 °C using a tetrakis-ethylmethylamido hafnium (TEMA-Hf) precursor and H2O as a source of Hf and oxidant, respectively. On the HfO2 thin film, the 200-nmthick W layer was patterned by a conventional lift-off process. Structural analysis of RS device The elemental depth profile was analysed using AES (ULVAC-PHI, CMA type analyser, 5 kV / 10 nA of electron beam energy) measurements. During the AES measurement, a sputtering rate of ~7 nm/min was maintained. HR-TEM (LIBRA 200 HT Mc Cs TEM) analysis was performed to obtain a cross-sectional view of the W/HfO2/TiN stacked RS device. To make the sample for HR-TEM observation, a focused ion beam (FIB, Helios NanoLab by FEI) process was used. AFM (Digital Instruments Dimension 3000, Veeco Science) analysis was conducted to observe the device morphology and exact feature sizes of the RS device.

Electrical measurements


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Electrical measurements were conducted using an HP4145B semiconductor parameter analyser (SPA), Agilent 81150A arbitrary function generator (AFG), oscilloscope (OSC, MSOX3024T, Tektronix), electromechanical radio frequency (RF) electric-circuit switch box, and a hot chuck with a temperature controller. In all of the measurements, the voltage was biased to the TE, while the BE was electrically grounded. The resistance (or current) values were read at 0.1 V using the SPA. In the case of multi-bit RS operation, ISPP/ECC operations were performed using two convertible electrical circuits composed of [AFG-RS device-OSC] and [SPA-RS device], respectively. These two types of electrical circuits were approached alternately by the electromechanical RF electrical circuit switch boxes. All of the electrical measurements were performed using a LabViEWTM based control program.


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Figure 1. (a) The single RS device topology analysed by AFM measurements. The 4 μm2 of active area was confirmed. (b) The cross-sectional view of W/HfO2/TiN stacked RS device observed by HR-TEM analysis. The 10-nm-thick HfO2 and 200-nm-thick columnar structured TiN BE layer was finely observed. In the W TE layer, the dark upper and bright lower layers were obviously observed which implies the different chemical states of the upper and lower layers in the W TE. (c) The I-V characteristics of the W/HfO2/TiN stacked RS device. With the self-compliance characteristic of the RS device, the applied bias controlled resistance variations were observed in


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both the SET and RESET operation regions. The inset shows a few selected I-V curves of SET process which confirms the LRS resistance variation as a function of applied bias. (d) The AES depth profile analysis results of the W/HfO2/TiN stacked RS device. As expected from the HRTEM observations, the W TE has an increasing oxygen concentration toward the W/HfO2 interface. The stoichiometric HfO2 layer and 20% oxygen concentration in the TiN BE were also confirmed.


21


15 L7 L6 L5 L4 L3 L2 L1

5 Pulse

Read

0

0

1

16

(a)

2 3 Voltage (V)

(c)

-3.4 -3.6

6

-3.8

4 3

6

9

12

-4

-4.0 15

-3

-2

-1

0

Voltage (V)

-3.0

8

2

(b) -5

-3.2

10

5

HRS

4

14 12

10

0 15

12 μA 9 μA 10

(d)

5

Expected Curve Measured Curve

-5

-4

Current of state level (μA)

-3

-2

-1

0

Current @ 0.1 V (μA)

10

RESET start voltage (V)

Current @ 0.1 V (μA)

15

Gradualness of RESET Current (μA/V)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

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0

Voltage (V)

Figure 2. (a) and (b) show the applied electric pulse induced current variation behaviours in SET and RESET operations, respectively. The obvious different current variation behaviour during SET and RESET can be observed, with current state level independent voltage values in SET and current state level dependent voltage values in RESET. To solve this problem and generalize the ‘Erase-free’ operation, an experimental expectation was performed. For this, two parameters were required as shown in (c), the gradualness of RESET current and RESET start voltage as a function of current of state level. (d) With these two parameters, the calculated RESET I-V curve could be estimated, and the expected I-V curve is consistent with the experimentally measured one.


22

14 12

(a)

10 8 6 4 2 0

L3

L2

L1

L5

L4

L7

L6

HRS 100

100

100

100

100

100

100

Number of RS cycle (#)

RS cycle (#)

Current (μA) @ 0.1 V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Current (μA) @ 0.1 V

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(b) HRS

L1

L2

2

14

4

L3

L4

L5

6 8 Current @ 0.1V (μA)

L6

10

L7

12

14

4

L7 L6 L5 L4 L3 L2 L1

2

HRS

12

(c)

10 8 6

0

100

100

100

100

100

100

100

100

100

RS cycle (#) Figure 3. (a) The conventional 3-bit (7-LRSs ad 1-HRS) RS operation results using ISPP/ECC method. The target current range of the HRS was set to 1.5 ~ 2 μA. (b) The statistical analysis of the results shown in (a). It was assumed that the obtained current values obey a Gaussian


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distribution. The SOP was evaluated as at least 5.38, which means a negligible probability of 3.7×10-6%. (c) The sequential and randomized ‘Erase-free’ based multi-bit RS operation results. Unlike the conventional multi-bit RS operation in (a), the HRS was not involved in all of the operation, which can save operational energy.


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Non Erase-free

Erase-free Energy efficiency ( % ) Energy efficiency ( % ) Energy efficiency ( % )

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


100 75

(a)

50 25 0 L1↔L2

100 75

L2↔L3

L3↔L4

L4↔L5

L5↔L6

L6↔L7

(c)

50 25 0

100 75

L4↔L6

L2↔L5

(e)

L1↔L6

Erase Write

L7 L6 L5 L4 L3 L2 L1 HRS

(b)

L7 L6 L5 L4 L3 L2 L1 HRS

(d)

Erase-free

(f)

50 25 0

L4↔L6

L2↔L5

L1↔L6

Figure 4. (a) The relative energy efficiencies of ‘Erase-free’ and ‘Non Erase-free’ operation, as schematically shown in (b). Up to 75% energy efficiency was confirmed. Similar results were also confirmed in randomized multi-bit RS operation as shown in (c) and (d). Because the ‘Erase-free’ based multi-bit RS operation does not involve a resistance transition related to the HRS, RS operational energy can be saved. (e) shows a comparison of the energy efficiency results between direct and sequential ‘Erase-free’ operation, as schematically described in (f). Compared to the direct resistance transition case, the sequential one can consume more operational energy due to the increased number of ISPP/ECC operations.


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Supporting Information. Supporting Information includes the 4 items like following. Local HR-TEM observation of W/HfO2/TiN stacked RS device, the direction of RS hysteresis in voltage bias sweep measurement, the area dependent RS characteristics of W/HfO2/TiN stacked RS device, the reliability characteristics of 3-bit RS operation in W/HfO2/TiN stacked RS device

AUTHOR INFORMATION Corresponding Author *E-mail: [email protected] *E-mail: [email protected]

Author Contributions J. J. Ryu, K. Jeon and S. Yeo performed the RS device fabrication and measurement of electrical characteristics. G. Lee conducted AFM measurement and analysis. C. Kim and G. H. Kim planned and supervised this work. ‡These authors contributed equally. (J. J. Ryu, K. Jeon and S. Yeo)

Notes The authors declare no competing financial interest.

ACKNOWLEDGMENT


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This research was performed as Project No. SI1803 (Development of Smart Chemical Materials for IoT Devices) and supported by the Korea Research Institute of Chemical Technology (KRICT). G.H.K. also acknowledges that this research was performed as Project No. KK1807C05 (Development of Low-Power and Reliable Multi-Bit Operation in Resistive Switching Device for Realizing of Artificial Synapse) and supported by the Korea Research Institute of Chemical Technology (KRICT).

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Fully 'Erase-free' multi-bit operation in HfO2 based resistive switching

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