Letter pubs.acs.org/NanoLett
Single InAs/GaSb Nanowire Low-Power CMOS Inverter Anil W. Dey,‡,† Johannes Svensson,‡,† B. Mattias Borg,†,∥ Martin Ek,⊥ and Lars-Erik Wernersson*,† †
Electrical and Information Technology, Lund University, Lund 221 00, Sweden Solid State Physics, Lund University, Lund 221 00, Sweden ⊥ Division of Polymer and Materials Chemistry, Lund 221 00, Sweden §
S Supporting Information *
ABSTRACT: III−V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III−V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal−oxide−semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III−V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at Vds = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies. KEYWORDS: Nanowire, inverter, InAs/GaSb, low-power operation, III-V CMOS
D
between the two transistors, for a low input voltage applied to the gate electrodes and vice versa (Figure 1b). InAs is suitable for n-type devices since it is one of the III−V binaries with the highest electron mobility (μe = 33000 cm2/(V s)) and has therefore successfully been used in high electron-mobility transistors (HEMTs).6 Among the III−V binary compounds, GaSb has the highest hole mobility of 1000 cm2/(V s), with a Fermi level pinning at the valence band edge, and is also naturally p-type even without doping. Consequently, it is a suitable choice for p-type devices.7 However, to fabricate III−V semiconductors using epitaxial growth, a lattice-matched substrate is required to avoid strain that could result in interface defects detrimental for device operation. Furthermore, buffer layers lattice-matched to InAs and GaSb tend to be conducting due to impurity incorporation when grown by production methods like CVD. This limits the choice of materials considerably and thus integration of n- and p-type devices on the same substrate is challenging and has hampered the development of III−V digital CMOS logic circuits. To compete with low-cost Si CMOS, III−V semiconductors should also preferably be integrated on a Si platform through,
ownscaling of the mainstream Si CMOS technology has led to an increase in the speed of logic circuits, but also to an increase in dissipated power density, which places high demands on chip cooling capability. Since the dissipated power for dynamic operation is proportional to the cube of the powersupply voltage (Vdd), much is gained by lowering Vdd, which is presently 0.7 V for the 22 nm node.1 However, lowering Vdd also results in a deteriorated Ion/Ioff ratio, impairing efficient logic operation. One approach to address this issue is to replace Si with e.g. III−V semiconductors,2,3 carbon nanotubes4 or graphene5 as the channel material in the transistors. The benefit of higher mobilities and injection velocities lead to a potentially higher on-state current for the same Vdd. Since the electron mobility is considerably higher than the hole mobility for all III−V materials, n-type III−V transistors for analogue applications have dominated research efforts thus far.2 For CMOS digital logic, both n- and p-type transistors are essential for efficient operation unless inferior ratioed logic, where a resistive load replaces the p-type transistor, is used. The CMOS inverter, which in its simplest form consists of one n- and one p-type transistor connected in series, is one of the most fundamental logic gates and is often used to demonstrate the viability of an emerging technology as all other logic gates can be realized by combining inverters with AND gates. This fourterminal circuit produces a high output voltage, measured © 2012 American Chemical Society
Received: July 18, 2012 Revised: September 18, 2012 Published: October 8, 2012 5593
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Figure 1. Device schematic: (a) Scanning electron microscope (SEM) image of an InAs/GaSb nanowire grown on an InAs substrate. The image is taken at a 30° angle. (b) Inverter layout as designed for a single nanowire. (c) Schematic fabrication steps starting with definition of the Vsupply, Vout, and Vground electrodes. (d) Deposition of an Al2O3/HfO2 gate dielectric layer overlapping all the electrodes. (e) Deposition of a common top gate. (f) Colorized SEM image of a completed device tilted 52°.
Figure 2. DC electrical characteristics of a long-channel InAs nFET and GaSb pFET with a gate length of Lg = 750 nm. (a) Output characteristics for the GaSb (orange) and the InAs (blue). (b) Transfer characteristics on a logarithmic scale for the GaSb (orange) and the InAs (blue) at Vds = 50 mV (dashed) and Vds = 500 mV (solid). (c) Transfer characteristics from part b on a linear scale.
e.g., epitaxial layer growth8 or mechanical transfer of thin membranes.9,10 By growing the materials in the shape of nanowires instead of planar layers, the issue of lattice mismatch can be avoided since most of the strain is relaxed through radial relaxation instead of defect formation.11 This enables the combination of materials with lattice mismatch as large as 15%,12 which would also allow integration on, e.g., Si.13 In addition, the nanowire geometry offers ideal electrostatic control of the potential in the channel by a gate-all-around architecture, which allows aggressive scaling of the gate length to improve device performance. An elegant solution to integrate high-performance n-type InAs and p-type transistors have been demonstrated by mechanically transferring a variety of nanoscale materials to insulating substrates, which also enables more complex circuits to be fabricated.9,10,14,15 Inverters using stacked layers of multiple n-type InAs and ptype Si/Ge core−shell nanowires exhibit an impressive DC gain but require high power supply and input voltages to achieve a sufficiently large voltage swing to be competitive with Si CMOS.16 Graphene inverters have recently been demonstrated but face a similar challenge as the core−shell nanowires in order to compete with Si CMOS.17 Promising results have begun to appear in the field of carbon nanotubes (CNT) where reports present low power operation of CNT circuitry.18 Very recent results using mechanically transferred III−V semiconductor nanoribbons demonstrate inverter operation at 0.5 V.15 However, it is clear that there is still a lack of (i) n- and ptype III−V devices integrated on the same platform, and (ii) low power logic circuits operating at 0.5 V. Here we have
demonstrated that (i) a n-type InAs and a p-type GaSb transistor can be integrated in a single nanowire and (ii) used as an inverter operating at 0.5 V, a key accomplishment crucial for the development of III−V CMOS circuits. The excellent inverter performance, already at a supply voltage of 0.5 V, is an essential requirement for future low-power electronics. InAs/GaSb nanowires were grown using metalorganic vapor phase epitaxy (MOVPE) from 30 nm Au aerosol particles deposited on InAs(111)B substrates (Figure 1a). The InAs segment was grown at 450 °C using trimethylindium and arsine as precursors with a V/III ratio of 41 yielding a pure wurtzite crystal structure with a low density of stacking faults (8 μm−1) followed by a zinc blende GaSb segment grown at 500 °C using trimethylgallium and trimethylantimony with a V/III ratio of 2 (Figure 1a). More details regarding nanowire growth will be reported elsewhere. Energy dispersive X-ray spectroscopy (EDX) in a transmission electron microscope (TEM) revealed that the GaSb is actually In0.03Ga0.97Sb due to remaining In in the Au particle during growth. The InAs and GaSb segments are each approximately 1 μm long and have diameters of 55 and 65 nm, respectively. Nanowires were mechanically transferred to a Si/SiO2 chip with predefined alignment marks and contact pads. Supply, output and ground electrodes were then defined by electron beam lithography (EBL) (Figure 1c). All EBL patterning steps were performed using a single layer PMMA 950 A5 exposed with 20 keV at a dose of 240 μC/cm2. The output electrode was defined to be sufficiently wide to cover the InAs/GaSb interface and extend at least 150 nm over each segment. Since all three contacts were processed in a single 5594
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Figure 3. Inverter characteristics. (a) Inverter VTC at different Vsupply. The inset shows the voltage gain extracted by smoothing and differentiating the VTC. Gain obtained by point slope derivation is available in Figure S3. (b) Noise margin extraction. The inset displays inverter characteristics of five devices indicating a small device-to-device variability. (c, d) Time-resolved inverter characteristics with Vsupply = 0.5 V and a square-wave input signal at (c) 100 Hz and (d) 10 kHz.
knowledge. For the InAs segment SS = 98 mV/dec at Vds = 0.5 V is obtained for a long-channel transistor. The asymmetry in the drive current between the InAs and the GaSb segments is related to a difference in both mobility and the distribution of interface states. The poorer subthreshold slope for the GaSb transistor indicates a larger Dit for the GaSb and a less effective modulation of the channel charge with the gate potential. Combined with a lower carrier mobility, we observe a lower transconductance and field-effect mobility. Short-channel devices exhibit higher ION at the expense of a decreased ION/ IOFF ratio (Supporting Information, Figure S1). Previous results show that the on-state performance of the InAs nanowire transistor can be enhanced by at least a factor of 20 by scaling down device dimensions and implementing doped source and drain regions.19 The aggressively scaled high-κ dielectric shows no sign of leakage, with a gate current of IG < 100 fA, which suggests there is room for further scaling that could improve the gate electrostatics. In addition, reducing the nanowire diameter increases the ION/IOFF ratio considerably. Figure 3a shows the voltage transfer characteristic (VTC) of a single nanowire inverter where the supply voltage (Vsupply) and ground (Vground) is applied to the GaSb and InAs segments, respectively (Figure 1b). The output is read at the middle electrode while the common gate is swept from −0.5 to 0.5 V. The VTC demonstrates that an input swing of −0.25 to 0.25 V is sufficient to reach an output swing larger than 93% of Vsupply, for the lower supply voltages (Vsupply ≤ 0.75 V). For a Vsupply = 1 V, the n-type InAs does not turn off as efficiently, leading to a slightly lower output voltage than desired. The maximum gain is 10.5 for Vsupply = 1 V. Figure 3b shows the inverter VTC from which the noise margins NML = VIL − VOL = 146 mV and NMH = VOH − VIH = 290 mV represent the tolerance to signal
lithography step, forming contacts to both InAs and GaSb simultaneously, a short pretreatment of HCl:H2O (1:10) was used to etch the native oxide, followed by thermal evaporation of 20 nm Ti/55 nm Au. A lift-off process is used to define areas of 4-nm-thick Al2O3/HfO2 high-κ gate dielectric deposited by atomic layer deposition (ALD) at 100 °C using 4 cycles of TMAl and 36 cycles of TDMAHf using H2O as the oxidizing agent (Figure 1d), followed by deposition of an overlapping topgate defined by a lift-off process by EBL and thermal evaporation of 20 nm Ni/55 nm Au (Figure 1e and f). Figure 2a shows the output characteristics of the individual parts of the inverter, i.e. a n-type InAs and a p-type GaSb FET, by grounding the middle electrode and biasing the respective end of the nanowire (Figure 1b). Both materials are nonintentionally doped with measured on-state drive currents of 58 and 1.7 μA/μm (RON = 3.5 Ω·mm and 212 Ω·mm) and transconductances of gm,max (InAs) = 160 mS/mm and gm,max (GaSb) = 3.4 mS/mm, normalized to the nanowire circumference, for the InAs segment and the GaSb segment, respectively. Due to the on-state asymmetry, the speed of the inverter will be limited by the p-type GaSb transistor. Figure 2b shows typical device transfer characteristics of the individual parts of a long-channel inverter, where the InAs exhibits enhancement mode behavior with a threshold voltage Vth = 46 mV extracted by linear extrapolation from the maximum transconductance. The GaSb has Vth = 117 mV and a comparably high off-current that is believed to originate from a high density of interface states (Dit) at the high-κ/III−V interface.7 This is also reflected in a large difference between the ION/IOFF ratios of InAs (ION/IOFF = 1190) and GaSb (ION/ IOFF = 63). The subthreshold swing SS = 400 mV/dec at Vds = 0.5 V is the lowest reported to date for GaSb to the authors’ 5595
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fluctuations. These values are well above the minimum requirement that the noise margin should be at least 10% of Vsupply, since 29% and 58% of Vsupply for NML and NMH, respectively, is obtained. The peak current when switching from high to low is found to be Isupply = 500 nA for Vsupply = 1 V (Supporting Information, Figure S2). However, the devices aim for operation at Vsupply = 0.5 V, which also reduces the peak switching current to 240 nA. The direct current contribution to the power consumption at Vsupply = 0.5 V, calculated by integrating Isupply over a switching event corresponds to a power of 93.6 nW. The minimum current, Isupply,min = 6 nA, is found for the lowest input voltage, Vinput = −0.5 V, limited by the OFFstate of the n-type InAs transistor. Device-to-device variability is low as is evident from VTC measurements on five different devices (inset in Figure 3b). Parts c and d of Figure 3 show time-resolved measurements of an inverter stage at two different frequencies. The operational frequency is primarily limited by the load capacitance of the output pads on the prepatterned coordinate chip, which is estimated to be 17.3 pF. The measurements reveal that the low to high switching is slower than the opposite switch, which is directly related to the asymmetry of the device where the p-type GaSb transistor has a lower drive current than the n-type InAs transistor as seen in Figure 2a. Our experimental results clearly show that the impressive properties of InAs are still not being exploited to their full potential in the inverter, since the GaSb processing technology is still in its infancy which hampers the inverter performance. The limited performance of GaSb devices is not inherent to nanowires since also conventional planar III−V p-MOSFET technology is still relatively immature20−22 compared to nMOSFETs although promising device characteristics have recently been reported.23 However, the GaSb performance could be further improved by reducing the access resistance, optimizing the high-κ integration,24 introducing surface passivation and increasing the drive current by strain engineering or incorporation of In.25 Finally, we also consider our results in terms of the ultimate scaling. Even if the classical intrinsic performance limit of GaSb would be achieved, the mobility of electrons in InAs is still approximately 33 times larger than that of holes in GaSb, which could make III−V CMOS logic difficult to realize on a large scale. However, for an aggressively scaled technology, the transport approaches the ballistic regime where the injection velocity and density of states, rather than classical low-field mobility, determine the device characteristics. In this regime, we expect that the device performance approaches the ballistic limit and the performance difference between n-InAs and p-GaSb is reduced increasing the III-V CMOS inverter performance. On the basis of the very promising results from single nanowire devices, we expect large arrays of InAs/GaSb aligned nanowires in either a lateral26 or vertical geometry13 to be the next milestone in high-performance III−V semiconductor electronics, enabling materials that have traditionally only been used for analogue applications to bridge the gap to the digital realm and compete with Si CMOS.
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AUTHOR INFORMATION
Corresponding Author
*E-mail:
[email protected]. Present Address ∥
Presently at IBM Research, Zürich, CH-8803 Rüschlikon, Switzerland Author Contributions ‡
These authors contributed equally to this work.
Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS This work was supported in part by the Swedish Foundation for Strategic Research (SSF), by the Swedish Research Council (VR), by VINNOVA, by The Nanometer Structure Consortium at Lund University, and by the Knut and Alice Wallenberg Foundation.
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ASSOCIATED CONTENT
* Supporting Information S
Electrical characteristics of short channel devices, switching current Isupply as a function of Vin, and gain extracted by point derivation of the VTC. This material is available free of charge via the Internet at http://pubs.acs.org. 5596
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