NANO LETTERS
Germanium Nanowire Epitaxy: Shape and Orientation Control
2006 Vol. 6, No. 2 318-323
Hemant Adhikari,† Ann F. Marshall,‡ Christopher E. D. Chidsey,§ and Paul C. McIntyre*,†,‡ Department of Materials Science and Engineering, Geballe Laboratory for AdVanced Materials, and Department of Chemistry, Stanford UniVersity, Stanford, California 94305 Received November 11, 2005; Revised Manuscript Received December 19, 2005
ABSTRACT Epitaxial growth of nanowires along the 〈111〉 directions was obtained on Ge(111), Ge(110), Ge(001), and heteroepitaxial Ge on Si(001) substrates at temperatures of 350 °C or less by gold-nanoparticle-catalyzed chemical vapor deposition. On Ge(111), the growth was mostly vertical. In addition to 〈111〉 growth, 〈110〉 growth was observed on Ge(001) and Ge(110) substrates. Tapering was avoided by the use of the twotemperature growth procedure, reported earlier by Greytak et al.
One-dimensional structures such as nanotubes and nanowires are being actively investigated for various applications in nanotechnology, including nanoelectronics. In the emerging technology of 3-dimensional (3D) nanoelectronics, vertically aligned nanowires have been proposed to provide a solution to attain ultrahigh-density nanoscale device arrays. Direct integration of vertical zinc oxide and indium oxide nanowires has been reported in which surround gate and top gate vertical field effect transistors were fabricated.1,2 However, silicon and germanium-based nanowire devices are much more desirable for electronic and other applications because of their compatibility with existing Si CMOS integratedcircuit technology. Although, historically, Si replaced Ge in microelectronics largely because of the superior structural and electrical characteristics of the Si/SiO2 interface, recent work on surface passivation of planar germanium surfaces and gate dielectric deposition on those surfaces suggests that Ge may again become an important material for highperformance transistors.3,4 Germanium nanowire (GeNW) transistors are very promising components for active device layers above a single-crystal silicon substrate because of (a) their potential for high density arrays of devices, (b) the relatively low growth temperature (
