Graphene and Carbon Nanotube Heterojunction Transistors with

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Graphene and Carbon Nanotube Heterojunction Transistors with Individual Gate Control Mao Shiomi, Yuta Mochizuki, Yuki Imakita, Takayuki Arie, Seiji Akita, and Kuniharu Takei ACS Nano, Just Accepted Manuscript • DOI: 10.1021/acsnano.9b01395 • Publication Date (Web): 01 Apr 2019 Downloaded from http://pubs.acs.org on April 1, 2019

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Graphene and Carbon Nanotube Heterojunction Transistors with Individual Gate Control

Mao Shiomi, Yuta Mochizuki, Yuki Imakita, Takayuki Arie, Seiji Akita, Kuniharu Takei* Department of Physics and Electronics, Osaka Prefecture University, Sakai 599-8531, Japan *Corresponding author: [email protected]

ABSTRACT Heterogeneously integrated nanomaterial devices show interesting characteristics for transistors and sensors due to their band diagram or steep material junctions. If these junctions and band alignments can be tuned by an electrical input bias, not only could the device platform be expanded but it could also be used to explore fundamental characteristics. However, most reports on hetero nanomaterial junctions use a global back-gate voltage, which makes it difficult to control band alignment at an interface. To explore device junctions, this study reports a laterally integrated heterojunction of graphene and a carbon nanotube (CNT) network film with individual gate electrodes to tune the band alignment corresponding to the Fermi level shift of graphene in contact with the semiconducting CNT network film. By developing the fabrication process, multiple gate structures are designed to apply a gate bias to CNT and graphene separately. The threshold voltage shift of the CNT transistor depends on the gate voltage of graphene. Based on

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the thermionic emission theory, the barrier height between graphene and CNT for both the conduction and valence band sides varies from 70~85 meV with a linear change as a function of the applied gate voltage to graphene. Although the current Fermi level shift is small, this device platform may realize the exploration of fundamental properties and device concepts.

KEYWORDS: graphene, carbon nanotube, heterojunction, Fermi level shift, transistors

Nanomaterials allow platforms for electronics to be built by utilizing unique properties such as interesting functionalities and significant performance enhancements. Nanomaterials, including zero-, one-, and two-dimensions, have been widely synthesized and applied to a variety of applications.1-4 In addition, heterogeneous nanomaterial junctions realize an interesting device design to enhance the functionalities and properties. For example, van der Waals and other nanomaterial interactions show interesting and/or high-performance characteristics for device applications of transistors,5-10 diodes,11-13 and other electronics.14-16 Due to their properties, nanocarbons, including carbon nanotubes (CNTs) and graphene, are promising nanomaterials. Graphene has a Dirac-cone band structure, which causes a zeroband gap with semiconductor characteristics and a high carrier mobility.17 Furthermore, the Fermi level (EF) can be readily tuned by a field effect from a gate bias. However, due to the zero-band


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gap, the off-current of the transistor is very high, which is one of the bottlenecks in digital circuit applications. On the other hand, single-walled CNTs are metallic and semiconducting, depending on the chirality of CNTs. By choosing semiconducting CNTs, a relatively high on/off current ratio for a transistor can be realized with a high mobility because unlike graphene, it has a large band gap. Although nanocarbon materials are promising as the next class of electronics, doping, which corresponds to threshold voltage control, remains a challenge due to difficulties applying the ion implantation process. If the doping-level or EF tuning issue can be addressed, material systems may show significant progress towards practical applications. In this regard, electrical control is one of the approaches to tune EF between electrodes and a semiconductor. In fact, several approaches have utilized the EF shift of graphene to improve the performance of transistors.10, 18-22 In addition to graphene, other material systems with dual-gate structure have been studied to investigate the device characteristics.23,24 However, because most reports focus on the vertical structure or common gate voltage for all material junctions, it is difficult to systematically analyze the band alignment tuned by the gate bias. In this study, a heterostructure of graphene and CNTs is proposed to tune EF using the properties of the Dirac-cone band diagram of graphene and the high mobility of CNTs with a large bandgap. To move EF by an external voltage, three gate structures are designed (Figure


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1a–b) with a graphene/CNT/graphene structure between the source (S)/drain(D) electrodes (Figure 1c). In addition, the fundamental characteristics of this junction device with gate bias dependences are systematically investigated using the thermionic emission theory based on experimental results. Figure 1d–e shows the device concept and mechanism. Each material (graphene and CNTs) has its own gate electrode to control the electron charge density into the semiconductor (Figure 1a). Due to low density of states in graphene at around the Dirac point, EF can be modulated by the gate bias.25,26 Applying a negative gate voltage to graphene moves EF to the conduction band (Ec) side, resulting in an n-type behavior (Figure 1d). In contrast, applying a positive gate voltage works as a p-type behavior by moving EF to the valence band (Ev) (Figure 1e). This EF movement results in a barrier height change between CNT and graphene (Figure 1d– e) due to the individual gate voltage control (Figure 1a, gate-source bias (VGS) and graphene gate bias (VGra)). If this can move largely between the valence band and conduction band sides of CNTs, the n-type and p-type behaviors can be controlled by just applying VGra.

RESULTS AND DISCUSSION A low-density CNT network was designed to realize a high on/off current ratio as shown in the result of atomic force microscope (AFM) (Figure 1c, inset). In addition to scanning electron


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microscopy (SEM) and AFM images, Raman spectroscopy was conducted to verify material formation (Figure 1c). Figure 1f shows the results in (1) the graphene region, (2) graphene/CNT junction region, and (3) CNT region for the Raman spectroscopy region described in Figure 1c. Regions with CNTs, including the junction of graphene/CNT, clearly show an RBM peak near 171 cm-1. In contrast, the graphene region does not have such a peak. Hence, this RBM peak was used to estimate the diameter of CNTs as ~1.45 nm.27 For graphene, the peak intensity is 2D peak (~2700 cm-1) > G peak (~1560 cm-1) confirms that the transferred graphene is a monolayer almost free from the defect peak (~1360 cm-1). Furthermore, Raman spectroscopy mappings focusing on the RBM peak intensity and the 2D peak intensity were measured to observe the uniformity of the device. The graphene and CNT layers are relatively uniform on the channel region (Figure 1g). Before discussing the junction device, each material was characterized in terms of the field-effect transistor (FET) by applying a global back gate bias. The device was capped with a SiOx/Al2O3/SiOx insulator without a top-gate electrode (VGS and VGra) to make the surfaces of graphene and CNT similar to the final device structures. Furthermore, without having the insulator layer, only p-type characteristic was observed regardless graphene contact (Figure S3). To discuss both p-type and n-type properties, the devices with insulating layer were characterized. The CNT network film FET shows a high on/off current ratio of >103 with an ambipolar behavior (Figure


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1h), whereas the graphene FET does not have a high on/off current ratio (Figure 1i). However, graphene FETs still display a gate bias dependence, which is an important characteristic to tune the EF movement. For the graphene/CNT junction device discussed later, VGra is selected from the Dirac point of graphene extracted from Figure 1i. It should be noted that these IDS-VGS curves are based on the band gap and Dirac-cone structures for CNT and graphene, respectively. This agrees well with previous studies on CNT networks and graphene FETs.17, 28 Using the global back gate bias, CNT network FETs with and without a graphene junction were measured. To compare the device performance, graphene was defined as the electrodes by fixing channel length L=100 µm for both device structures (Figure 2a-b) because the graphene conductance is much higher than that of the CNT network film, as discussed in Figure 1h-i. Consequently, the material between graphene and Au/Cr electrodes does not affect the transistor properties. Figure 2c shows the IDS-VGS characteristics of multiple samples for devices with/without graphene. Devices with a graphene contact have a high on-current for both n-type and p-type performances compared to those without graphene. For a more quantitative discussion, the field-effect mobilities for both p-type and n-type properties were extracted using the parallel plate capacitance of the channel area multiplied by the width and length. The mobility µ was extracted by using the equation of 𝜇=

𝐿

𝑑𝐼𝐷𝑆

𝑊𝐶𝑜𝑥𝑉𝐷𝑆𝑑𝑉𝐺𝑆 6

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where W is the channel width (~150 µm), Cox is the parallel plate capacitance (11.5 nF/cm2), and VDS is the drain-source voltage. The performances for both the p-type and n-type with a graphene contact have ~14.9 times higher hole mobility (7.0±1.6 cm2/Vs) and ~3 times higher electron mobility (1.1±0.2 cm2/Vs) (Figure 2d-e). However, the mobility of FETs is relatively low compared to other CNT network FETs reported previously.29 This is mostly because the CNT network density is low (Figure 1c, inset). To understand the reason for the on-current increase for the device with graphene, a systematic and fundamental contact resistance study is required. However, due to complicated structure with junctions of CNTs and graphene, the device structure for four-point probe method or transmission line method to extract the contact resistance could not be fabricated in this study. To dig into the detail analyses of the contact resistance change with and without graphene, further developments of the device fabrication and analyses are required in the future. In terms of the subthreshold slope (SS), Qiu et al. reported that the band alignment of EF in graphene due to the gate bias improves the SS of single CNT FET.10 However, such an improvement is not observed in this study. SS values for p-type (n-type) behaviors are 4.25±1.32 V/dec (4.54±0.73 V/dec) and 3.78±0.53 V/dec (4.77±1.04 V/dec) without and with graphene contacts, respectively, as shown in Figure S2. Based on the results, obvious trend difference for SS depending on graphene contacts was not observed. This is most likely due to the network


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structure of CNTs and the large channel length. In particular, the network structure of CNTs causes variations in the device performance, including the threshold voltage. Hence, an improved SS is not observed. After confirming the fundamental characteristics of each material and the junction, the top-gated structures were investigated by applying different VGra for the IDS-VGS properties of CNTs. In addition, IDS-VDS characteristics were measured (Figure S4). The device structure and device setup are shown in Figure 1a. For all top-gated device measurements, Si substrate corresponding to the back-gate bias was grounded to be zero voltage. As a control experiment to confirm the graphene effect, an all-CNT network structure without a graphene contact was prepared (Figure 3a). At different VGra biases from –6 V to 3 V, the threshold VGS voltage, which is defined as the lowest IDS current in this study, shifts to the negative side while maintaining the on/off current ratio for all VGra biases (Figure 3b). In contrast, the threshold voltage is almost constant at different gate biases of external gate voltage (Vext) for the all-CNT network FET described in Figure 3a but the on/off current ratio drastically changes (Figure 3c). For a more systematic threshold voltage change for graphene/CNT junction device, Figure 3d plots the trend of the threshold voltage shift as a function of VGra bias. The threshold voltage shifts linearly at different VGra, which implies that the EF shift of graphene is caused by VGra. To further assess the EF movement generated by the external gate voltage, a more


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detailed experiment was conducted to extract barrier height ϕB using the thermionic emission theory. The theory is expressed by

(

𝐼𝐷𝑆 = 𝐴𝑇2exp ―

𝑒∅𝐵 𝑘𝑇

)[𝑒𝑥𝑝( ) + 1] , 𝑒𝑉𝐷𝑆 𝑘𝑇

where A is the effective Richardson constant, T is the measurement temperature, and k is the Boltzmann constant. Figure 4a displays a representative IDS-VGS curves at VGra=0 V and different measurement temperatures. Depending on VGS, temperature, and VGra, the slope of Arrhenius plots can be extracted using the IDS difference (Fig. 4b). The compiled results typically have two linear slopes. One corresponds to both tunneling and thermionic transports at higher electron/hole charge density induced by the gate voltage (i.e. higher VGS for valence band side and lower VGS for conduction band side), and the other is based on thermionic transport only at lower charge density (i.e. lower VGS for valence band and higher VGS for conduction band). The boundary of the two linear slopes is defined as the barrier height (ϕB) (Figure 4b, arrow).30 This ϕB is explained as the Schottky barrier height of both the valence and conduction bands for p-type and n-type FET behaviors, respectively (Figure 4c). By collecting all datasets from the VGra and VGS results, Figure 4d–e compiles the barrier height as a function of VGra. As expected, the barrier heights for both p-type and n-type FETs linearly change due to EF movements caused by the electron charge injected from VGra. For example, at VGra=6 V, EF of graphene should be on the conduction band side, lowering the barrier height to n-type CNT FETs. The lowest barrier


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height is ~70 meV, while the highest barrier height of ~85 meV is observed at VGra = –6 V. (Figure 4e). In addition to the case of n-type, the barrier height trend for the p-type FET is also consistent based on band alignment. In this study, the barrier height can be controlled by VGra between 70~85 meV only. This EF shift is smaller than the vertically integrated graphene/WS2 structures (EF movements > 300 meV) reported elsewhere.8 This small EF shift may be due to two reasons. One is the variation of the threshold voltage of CNTs, which corresponds to the EF position of CNTs. This variation most likely suppresses the effect of the EF shift in graphene caused by the gate bias. The other is a poor quality interface between CNTs and graphene due to the solution-based CNT deposition on graphene, which may result in contamination and a bad interface that leads to defects in the band alignment and carrier movements.

CONCLUSIONS In this study, the EF shift is used to control the threshold voltage via an external gate bias using low density of states in graphene. Adjusting EF of graphene successfully controls the threshold voltage of CNT network FET. Based on the thermionic emission theory, the barrier height between CNT and graphene, which corresponds to the EF shift, is 70~85 meV for both p-type (valence band side) and n-type (conduction band side) with a linear change as a function of VGra.


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To increase the EF shift at the gate voltage, the device and heterogeneous semiconductor junctions modulated by the external gate voltage must be further analyzed as this should improve the CNT performance variation in the network film and the interface between CNTs and graphene. Although the EF shift is small, this study demonstrates a concept and platform for devices as well as analyzes the electrical characteristics. Realization of a platform with a highly efficient band shift should control the threshold voltage. Unlike standard transistors, this platform could realize polarity (n-type and p-type) using an electrical input signal.

EXPERIMENTAL SECTION Fabrication process. Device fabrication process is introduced (Figure S1). Cr/Au metals as S/D electrodes were deposited and patterned by an electron-beam (e-beam) evaporator and a lift-off process, respectively, on a Si/SiO2 substrate (300 nm-thick thermally grown SiO2). Chemical Vapor Deposition (CVD)-grown monolayer graphene was transferred from a Cu foil to the substrate with S/D electrodes. The transfer method is reported elsewhere.31 O2 plasma was applied to pattern the transferred graphene. After patterning graphene, a 99% semiconductor-enriched CNT network film was formed via chemical adhesion. To enhance the CNT network formation, poly-L-lysine was chemically treated on the substrate. This chemical treatment creates a positively charged surface. A CNT solution (NanoIntegris, USA) was modified with sodium


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cholate to make a negative charge on CNTs.32 Due to the negative and positive surfaces between the substrate and CNTs, the CNT network was chemically bonded on the surface of the substrate. To improve the performance of CNT FET, it was annealed at 200 °C in a vacuum for 90 min. For a gate structure, a SiOx layer (10 nm) was deposited by an e-beam evaporator to form a uniform Al2O3 layer using atomic layer deposition (ALD). A 50 nm-thick Al2O3 layer was deposited followed by another SiOx layer (10 nm). An aluminum gate electrode was sputtered for VGS (Figure 1a) and patterned by wet etching. These gate dielectric material and electrode depositions were repeated to form VGra (Figure 1a).

ASSOCIATED CONTENT Supporting Information The Supporting Information is available free of charge on the ACS Publications website at DOI:. Supplemental figures showing the device fabrication process, subthreshold slopes with and without graphene contacts, IDS-VGS characteristics without deposition Al2O3 layer.

ACKNOWLEDGEMENTS This study was supported by the TEPCOM Memorial Foundation.


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Figure 1. (a) Schematic of the graphene/CNT junction transistor. (b) Optical microscope image of the device. (c) SEM image of the graphene/CNT junction. Inset is an AFM image of the CNT network. Mechanism of the Fermi level shift of graphene at (d) VGra > 0 V and (e) VGra < 0 V. (f) Raman spectroscopy at the (1) graphene region, (2) graphene/CNTs region, and (3) CNTs region, where the position is indicated in (c). (g) Raman mapping of RBM and the 2D peak at the junction of graphene and CNT network films. IDS-VGS characteristics of (h) CNT FET and (i) graphene FET without a junction.


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Figure 2. Schematic cross-sectional global back-gated device structure (a) with and (b) without a graphene junction. (c) IDS curves as a function of back-gated voltage VGS with and without a graphene junction. Field-effect mobility with/without a graphene junction for (d) p-type and (e) n-type properties.


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Figure 3. (a) Detailed schematic cross-sectional image of the top-gated devices without a graphene junction. (b) IDS-VGS characteristics for a graphene/CNT device at different VGra bias. (c) IDS-VGS characteristics for a CNT device at different Vext bias. (d) Threshold voltage shift of graphene/CNT FET as a function of VGra.


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Figure 4. Barrier height extraction based on the thermionic emission theory. (a) Representative IDS-VGS characteristics at VGra=0 V and different temperatures. (b) Barrier height extraction curve of the p-type behavior (top) and the n-type behavior (bottom) at VGra=0 V. (c) Band diagram to explain the barrier height for each p-type and n-type properties. Barrier height as a function of VGra for the (d) valence band side (p-type) and (e) conduction band side (n-type).


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Graphene and Carbon Nanotube Heterojunction Transistors with

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