Graphene Gate Electrode for MOS Structure-Based Electronic

LETTER pubs.acs.org/NanoLett

Graphene Gate Electrode for MOS Structure-Based Electronic Devices Jong Kyung Park, Seung Min Song, Jeong Hun Mun, and Byung Jin Cho* Department of Electrical Engineering, KAIST, 335 Gwahak-ro, Yuseong-gu, Daejeon, Korea, 305-701

bS Supporting Information ABSTRACT: We demonstrate that the use of a monolayer graphene as a gate electrode on top of a high-k gate dielectric eliminates mechanical-stress-induced-gate dielectric degradation, resulting in a quantum leap of gate dielectric reliability. The high work function of hole-doped graphene also helps reduce the quantum mechanical tunneling current from the gate electrode. This concept is applied to nonvolatile Flash memory devices, whose performance is critically affected by the quality of the gate dielectric. Charge-trap flash (CTF) memory with a graphene gate electrode shows superior data retention and program/ erase performance that current CTF devices cannot achieve. The findings of this study can lead to new applications of graphene, not only for Flash memory devices but also for other highperformance and mass-producible electronic devices based on MOS structure which is the mainstream of the electronic device industry. KEYWORDS: Graphene, gate dielectric, charge-trap flash (CTF) memory, graphene gate electrode, mechanical stress, tunneling current

I

n the past few years, continual efforts to demonstrate the practical use of graphene have been made for electronic device applications.1
3,5,6 To date, however, the use of graphene as a channel material is limited due to the fundamental obstacle of the zero band gap characteristic of graphene,1 which limits the utilization of this material in field-effect transistors (FET) for digital circuit applications.2 Although the use of graphene in analog RF applications is of interest as a channel material,3 it only constitutes a minor portion compared to mainstream semiconductor products including digital logic and memory devices, within the vast semiconductor manufacturing industry. However, our findings show that graphene has clear advantages as a gate electrode for devices with metal
oxide
semiconductor (MOS) structure. State-of-the-art nanoscale CMOS devices use a combination of high-k dielectrics and metal gate electrodes for their gate stack structure.4 If the metal gate electrode were to be replaced with graphene, it is expected that the monolayer graphene with its inherent flexible and stretchable nature would eliminate the metal-gate-induced mechanical stress in the high-k gate dielectric.5,6 Given that mechanical stress is known to generate electron/hole traps in a dielectric material,7 the elimination of mechanical stress through the use of monolayer graphene electrode will result in a considerable improvement in the gate dielectric quality and therefore enhance the performance of the device. In addition, the high work function of hole-doped graphene on given dielectrics is another significant advantage in that it reduces the tunneling current from the gate electrode,8
11 one of the key issues associated with nanoscale integration. In this work, as a demonstration of this concept, we have applied a graphene layer as the gate electrode of a nonvolatile r 2011 American Chemical Society

Flash memory device,12 whose performance is, among all types of commercial electronic devices, most critically affected by the quality of the dielectric material. Especially for this Flash memory device, the charge-trap Flash (CTF) device structure is chosen,13 as it is highly sensitive to the dielectric quality and is considered to be the most practical and promising candidate for nextgeneration high-performance and mass-producible nonvolatile memory devices.14 In this paper, we demonstrate clear and tremendous improvements in the performance of the CTF device through the use of a monolayer graphene gate electrode, thus introducing a new area of application for graphene in the electronic devices. The conventional CTF device is composed of a stack of three insulator layers: a tunneling oxide (SiO2) thermally grown on a silicon substrate, a silicon nitride (Si3N4) charge trapping layer, and a high-k blocking oxide (Al2O3). On top of the Al2O3 blocking oxide, a TaN metal gate electrode with typical thickness of 100
150 nm is used, as shown in Figure 1a. TaN metal, a midgap work function material, has been widely used as the gate electrode material in the CTF devices because of its good thermal stability, scalability, and compatibility with CMOS front-end process flow.14
16 We have replaced the thick TaN metal gate with a monolayer graphene prepared via chemical vapor deposition (CVD) on Cu and a layer transfer technique (Supporting Information).17
20 Raman spectroscopy reveals that the CVD Received: August 27, 2011 Revised: October 17, 2011 Published: November 07, 2011 5383

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Nano Letters

Figure 1. (a) Structure of CTF devices with typical TaN metal and the proposed monolayer graphene for the gate electrode. (b) Program and (c) erase characteristics for the device with graphene and TaN electrodes. Devices were programmed or erased for a time interval of 100 ms.

grown graphene film transferred onto the dielectric is high quality and preferentially formed into a monolayer as shown in Figure S2 of the Supporting Information.21 By replacing the thick metal electrode with the monolayer graphene, the total height of the gate stack is significantly reduced. This presents an additional benefit to process integration, because the more planar surface facilitates the subsequent lithography and deposition processes. Panels b and c of Figure 1 present a comparison of the program/erase characteristics of devices with graphene and TaN gate electrodes. Devices were programmed or erased by applying a positive or negative bias voltage for 100 ms. The graphene electrode device offers a much wider program/erase window compared to the TaN electrode device. During the erase operation, the TaN electrode device shows early saturation and dielectric breakdown at the same electric field as applied to the tunnel oxide. In our experiment, the maximum achievable flat band voltage shift (ΔVFB,max) was 16.8 and 10 V for the graphene and TaN gate electrode devices, respectively; this constitutes a significant difference, considering that the two devices are identical except for the gate electrode. One of the most important factors for CTF devices is their charge retention capability, which has become the main technical hurdle obstructing mass production of CTF devices.22 Figure 2a shows the retention properties of the devices with graphene and TaN electrodes. The device with a graphene electrode shows a significant improvement in the data retention property compared to the device with the conventional TaN metal gate electrode. The graphene electrode device demonstrates successful multibit operation, which is essential for modern high density Flash memory,23 by securing ΔVFB > 2 V between adjacent states of two bit operation when the retention time is projected to 10 years. The charge loss of the “11” state after 10 years is only 0.7 V for the graphene electrode device while it is 3.3 V for the TaN metal gate electrode device. The wide program/erase windows and demonstration of multibit operation with an excellent charge retention property presented in Figures 1 and 2a show that the major technical hurdles of CTF devices can feasibly be overcome by adopting a graphene electrode. The results in Figures 2b to 4 explain the strong improvement observed with incorporation of the graphene electrode in the CTF device. The leakage currents through the gate dielectric

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Figure 2. (a) Charge retention properties of the devices with graphene and TaN electrodes. The graphene electrode device demonstrates successful multibit operation, by securing ΔVFB > 2 V between adjacent states of two bit operation when the retention time is projected to 10 years. (b) Comparison of leakage current performance. The leakage current was measured using the whole gate stack including the tunnel oxide, nitride, and blocking oxide. (c) Capacitance
voltage (C
V) curves of the initial state of the devices with different electrodes. The entire curve of the graphene electrode device shifts to positive voltage by ∼0.7 V, indicating strong hole doping and a high effective work function of graphene.

stacks are compared in Figure 2b. The gate leakage current of the graphene electrode device is 2
3 orders of magnitude lower than that of the TaN electrode device at the typical operation voltage range of
14 to
20 V. This is attributed to the different effective work function between the graphene and TaN electrodes, which is evidenced by the capacitance
voltage (C
V) curves of the initial state of the two devices shown in Figure 2c. The entire curve of the graphene electrode device shifts to positive voltage compared to that of the TaN electrode device, indicating that the graphene electrode has a higher effective work function than the TaN electrode. For confirmation of this shift, we conducted separate experiments to fabricate single Al2O3 gate dielectric MOS devices without a charge trap nitride layer, and the same shift in flat band voltage between the graphene and TaN electrodes was observed consistently for different sets of Al2O3 thickness. This positive shift of the graphene electrode implies that the monolayer graphene on the Al2O3 dielectric is strongly hole doped.8
11 The results show that the effective work function of graphene is mathematically around 0.7 eV higher than that of TaN metal. As the TaN metal gate is known to own the midgap work function,24 the graphene electrode on Al2O3 oxide is estimated to have an effective work function in a range of 5.2
5.3 eV. This extremely high effective work function of graphene significantly reduces back tunneling current from the gate electrode during erase operation as shown in Figure S3 in the Supporting Information. Removing electrons from the Si3N4 charge trap layer consequently becomes easier, leading to a wider erase window. Other metals with high work functions such as Pt and Au can also suppress the back tunneling current during erase operation. However, metals with high work functions usually present challenges in the patterning process due to a lack of volatile byproduct during reactive ion etching, thereby preventing their use in patterned lines in semiconductor device production. Furthermore, some noble metals are the sources of contamination that are detrimental to silicon device performance 5384

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Nano Letters

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Figure 3. Simulated mechanical stress contour maps of devices with a 150 nm thick TaN metal gate electrode and a monolayer graphene gate electrode.

and thus are not compatible to the CMOS front-end process. For example, the high work function metal like Au can introduce deep level traps in the band gap of silicon that act as generation
recombination centers, causing high junction leakage in CMOS devices. In contrast, monolayer graphene does not present such problems in fine patterning. Although the high effective work function is an important advantage of the graphene electrode and can account for the wide erase window, the change in the program characteristics of the device cannot be explained by the difference in the work function. When the same electric field is applied on the tunnel oxide, we can expect the same program speed and program saturation level between the graphene device and TaN device, because the same amount of electrons is injected from the silicon substrate into the Si3N4 trap layer. However, the graphene device shows a much wider program window. Since the same amount of electrons is injected, the only possibility for the difference is the different leak rates of electrons through the side opposite to where electrons are injected, that is, through the Al2O3 blocking layer as shown in Figure S4 in the Supporting Information. This indicates that the leakage current through the blocking layer is significantly reduced by the use of the graphene electrode. As the oxide leakage current is greatly enhanced by the presence of traps in the bulk of the dielectric through a trap-assisted-tunneling (TAT) mechanism,7 the Al2O3 blocking oxide under the graphene electrode should have a much lower density of electron traps compared to that under the TaN metal electrode. Since the Al2O3 blocking oxide was formed together for both devices, the difference in Al2O3 quality should be caused by the electrodes. It is accordingly attributed to the different mechanical stress between the graphene and metal electrodes, as mechanical stress in the dielectric can generate electron traps. To clarify this, we carried out a technology computer-aided design (TCAD) simulation to estimate the mechanical stress in both devices, with input parameters of actual mechanical stress values of each layer measured by laser scanning of the wafer curvature and using the Stoney formula.25 The simulated mechanical stress contour maps of devices having the two different gate materials are shown in Figure 3. The results show that TaN metal generates a very high level of stress to the Al2O3 blocking oxide; the peak stress value in the Al2O3 blocking oxide caused by a 150 nm thick TaN metal electrode is 656 MPa (tensile stress). On the other hand, for the graphene electrode device, the stress in Al2O3 under the graphene electrode is built mostly by the nitride layer, as it is expected that the graphene electrode will not cause any mechanical stress to the Al2O3 blocking oxide due to its excellent mechanical flexibility5,6 and monatomic thickness. In this case, the peak stress value in the Al2O3 blocking oxide is only 2 MPa (compressive stress).

Figure 4. (a) Change in gate voltage during constant current stress test for the devices with graphene and TaN electrodes. (b) Measured mechanical stress caused by the TaN metal film on the silicon wafer as a function of TaN thickness. (c) Simulated peak stress value in the Al2O3 dielectric as a function of TaN gate electrode thickness. (d) Average electron trapping rate in the Al2O3 dielectric as a function of the TaN gate electrode thickness.

In order to obtain direct evidence of the effects of the mechanical stress in the Al2O3 dielectric on trap generation, a constant current stress (CCS) test, a widely used method in semiconductor device reliability studies, was applied to the Al2O3 dielectric with the two different electrodes. For the CCS test, MOS devices with a 27 nm thick Al2O3 layer and a 2 nm thick interfacial SiO2 layer were used and CCS of
5 μA/cm2 was applied to the gate electrode. Figure 4a shows the change in the gate voltage during the CCS test performed on devices with a 150 nm TaN electrode and a monolayer graphene electrode. The results clearly show that the trapping efficiency is significantly reduced when the graphene gate electrode is used. The average trapping rate in terms of ΔVG/s is 0.22 and 0.05 ΔVG/s for the TaN and graphene electrodes, respectively (Supporting Information). When the thickness of the TaN gate electrode is reduced from 150 to 30 nm, the measured compressive stress is gradually reduced (Figure 4b) and thereby the stress level in Al2O3 is also reduced gradually from 656 to 396 MPa (Figure 4c). The electron trapping rate during the same CCS test is also reduced from 0.22 to 0.19 (Figure 4d). This direct correlation is good evidence that the trap generation in the dielectric increases with mechanical stress in the dielectric. It should also be noted that, even for the 30 nm thick TaN, the stress level and the electron trapping rate are not comparable to the case of the 5385

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Nano Letters graphene electrode. If the TaN electrode thickness is reduced to the 1 nm range to obtain a similar range of mechanical stress as accompanied by the graphene electrode, the sheet resistance will be around 45k Ω/sq,26 which negates possible use of the electrode. As electron traps in the blocking oxide cause trap-assistedtunneling as shown in Figure S5 in the Supporting Information, the reduction of traps in the Al2O3 blocking oxide with the graphene electrode is the main source of the improved program property (Figure 1b) and the excellent charge retention property (Figure 2a) of the graphene electrode device. In addition, as the device size becomes smaller, metal-gate-induced stress to the dielectric will be more serious due to edge-induced stress.27 Therefore, the advantages of the graphene gate electrode compared to other metal gate electrodes may become more pronounced in highly scaled devices. In conclusion, we applied a graphene layer as a gate electrode in a CTF memory device, which is considered as the strongest candidate as a near-future solution for mass-producible nonvolatile memory devices. Excellent charge retention properties and multibit operation of the CTF device, the most critical issues in CTF devices, were successfully demonstrated with a graphene electrode. As the graphene electrode with its monatomic layer eliminates mechanical stress in the blocking oxide, significant enhancements of the data retention properties and program window are easily achieved. Moreover, the extremely high effective work function of strongly hole-doped graphene greatly improves the erase characteristics. This dramatic improvement of the quality of the gate dielectric due to the use of a graphene electrode is promising not only for Flash memory devices but also for other MOS-structured devices in which excellent reliability is required, such as those devices in automobile electronics. The results presented here represent the opening of new application areas of graphene toward high-performance and mass-producible electronic devices based on the MOS structure which is the mainstream of the electronic device industry.

’ ASSOCIATED CONTENT

bS

Supporting Information. Experimental details and additional supporting figures. This material is available free of charge via the Internet at http://pubs.acs.org.

’ AUTHOR INFORMATION Corresponding Author

*E-mail: [email protected].

’ ACKNOWLEDGMENT This work was supported by the National Research Foundation of Korea (NRF) Research Grants 2008-2002744 and 20100029132. ’ REFERENCES (1) Balog, R.; Jørgensen, B.; Nilsson, L.; Andersen, M.; Rienks, E.; Bianchi, M.; Fanetti, M.; Lægsgaard, E.; Baraldi, A.; Lizzit, S.; Sljivancanin, Z.; Besenbacher, F.; Hammer, B.; Pedersen, T. G.; Hofmann, P.; Hornekær, L. Nat. Mater. 2010, 9 (4), 315–319. (2) Schwierz, F. Nature Nanotechnol. 2010, 5 (7), 487–496. (3) Lin, Y. M.; Dimitrakopoulos, C.; Jenkins, K. A.; Farmer, D. B.; Chiu, H. Y.; Grill, A.; Avouris, P. Science 2010, 327 (5966), 662. (4) Moore, G. E. No exponential is forever: But 00 forever00 can be delayed! In Solid State Circuits Conference, Digest of Technical Papers;

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