Letter pubs.acs.org/NanoLett
High Critical-Current Superconductor-InAs NanowireSuperconductor Junctions Simon Abay,† Henrik Nilsson,‡ Fan Wu,† H.Q. Xu,‡,§ C.M. Wilson,† and Per Delsing*,† †
Department of Microtechnology and Nanoscience (MC2), Chalmers University of Technology, SE-412 96 Göteborg, Sweden Division of Solid State Physics, Lund University, Box 118, S-221 00 Lund, Sweden § Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China ‡
ABSTRACT: We report on the fabrication of InAs nanowires coupled to superconducting leads with high critical current and widely tunable conductance. We implemented a double lift-off nanofabrication method to get very short nanowire devices with Ohmic contacts. We observe very high critical currents of up to 800 nA in a wire with a diameter of 80 nm. The current− voltage characteristics of longer and suspended nanowires display either Coulomb blockade or supercurrent depending on a local gate voltage, combining different regimes of transport in a single device. KEYWORDS: InAs nanowires, supercurrent, Andreev reflection, Coulomb blockade
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and lift-off processes. In addition, most previous studies have used a back gate that has only a weak capacitive coupling to the nanowires conducting channel, requiring large gate voltages to tune charge transport significantly.11 Here, we used a two-step process to fabricate very short nanowire devices.16 In this process, the minimum length of the devices was not limited by the e-beam resist, but rather by the alignment accuracy between successive lithography steps. Using this method we have fabricated nanowire devices with lengths down to 30 nm combined with highly transparent interfaces to Ti/Al contacts. This has allowed us to enhance the critical current by approximately an order of magnitude compared to previously reported devices. We also successfully fabricated suspended nanowire junctions with a nearby local gate. The local gate not only ensures strong coupling to the nanowire conducting channel but also allows individual control of different nanowires on a single chip. The result of the present study opens up the possibility to apply semiconducting nanowire weak links in nanodevices where a higher critical current is needed. In this manuscript, we also show that the conductance of the nanowires can be tuned by a gate voltage between a superconducting and an insulating state. In this paper, we present measurements done on two sets of samples, very short samples placed directly on the substrate and somewhat longer suspended samples with individual gate control. We used standard nanofabrication techniques, such as electron beam (e-beam) lithography, metal deposition, and liftoff to fabricate the two sets of samples. They were made on
hen two superconductors are coupled by a weak link, a dissipationless supercurrent can flow through the junction as a result of the proximity effect1,2 which has a microscopic origin in Andreev reflection.3−5 Devices based on the proximity effect can be used in a broad range of applications, for example, in superconducting quantum interference devices,6 and it has also been suggested that they can be used as quantum bits.7 The nature of the weak link can be of many different kinds including an insulator, an atomic contact, a normal conductor, or a semiconducting nanowire. The semiconducting nanowire version of the weak link offers the possibility to tune the coupling strength with a gate voltage, and hence, allows for control of the magnitude of the supercurrent. The small scale dimensionality of nanowires also makes them promising platforms to study fundametal phenomena such as quantum interference effects8 and Majorana fermions.9,10 In particular, InAs nanowires are promising as a result of their high electron mobility and strong spin−orbit interaction. Furthermore, Ohmic contacts can easily be formed. InAs nanowires have been used as weak links to demonstrate a Cooper-pair field effect transistor,11 the interplay between Andreev reflection and Coulomb blockade,8 a Cooper-pair beam splitter,12 and recently, to observe high orders of multiple Andreev reflections on highly transparent contacts.13 However, the magnitudes of critical currents that have been reported are relatively small, typically of the order of 50 nA or smaller.14,15 The small critical currents are at least partly due to the long channel lengths. Fabrication of short channel devices is limited by the resolution of electron beam resist; in particular, for electrodes as thick as the diameter of the nanowires, an exposed e-beam resist easily disintegrates during the resist development © 2012 American Chemical Society
Received: July 24, 2012 Revised: September 26, 2012 Published: October 3, 2012 5622
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In addition, the large spacing of the electrodes in both steps means that it is possible to increase the development time of the e-beam resist. An increase in the resist development time enables us to get rid of residual resist which in turn helps to produce better metal−nanowire interfaces. However, the second lithography step needs to be done within hours to avoid degradation of the interfaces between the nanowire and the already deposited electrodes. For the fabrication of a suspended sample, a standard Sisubstrate was patterned with interdigitated Ti/Au stripes.19 The interdigitated metal stripes were made in a two-step nanofabrication process to get a height difference of 15 nm such that the nanowire rests on the thicker electrodes and is suspended above the substrate as well as above the thinner electrodes. InAs nanowires were then mechanically transferred to the patterned Si substrate, and their relative positions were located with the help of SEM images. The extracted locations were then used to pattern superconducting Ti/Al (5/150 nm thick) contacts on top of the nanowires. A SEM image of the final device is shown in Figure 1c. To get good transparency of the interfaces (lower contact resistances), an ammonium polysulfide solution (NH4Sx) cleaning process20 was used prior to evaporation of the superconducting contacts for both short and suspended samples. The samples are then characterized at room temperature and are stored in vacuum before further measurements at low temperature. Current−voltage characteristics (IVCs) of the devices were measured in a dilution refrigerator with a base temperature of 15 mK. To decrease noise coupling to the devices, electrical lines in the measurement set up are well-filtered and thermally anchored at the different temperature stages of the refrigerator. The IVCs were obtained in a symmetric current-bias configuration as it is shown in the schematic picture of Figure 1c. As the bias voltage Vb was swept, both the current through the sample (I1 is the same as I2) and the voltage drop (V) across the sample were simultaneously measured with differential amplifiers. IVCs were obtained for many devices with a range of nanowire lengths 30−400 nm and normal resistances Rn = 160 Ω to 4.5 kΩ. The resistance essentially scales with the nanowire length, implying a low contact resistance to the wires. A typical IVC of a short device with a length of 30 nm is shown in Figure 2a. For temperatures above the critical temperature, Tc, of the superconducting electrodes, the junction showed Ohmic behavior with a normal state resistance of Rn = 165 Ω (red curve). Once the temperature drop below Tc, the current− voltage characteristic started to exhibit enhanced conductance below a voltage corresponding to the superconducting gap, 2Δ ∼ 260 μeV, followed by an abrupt switch to a dissipationless supercurrent branch (blue curve). To clearly see the enhanced conductance, we have plotted the differential resistance as a function of source-drain voltage (Vds) in Figure 2b. We note that there is a steep decrease of differential resistance which starts at Vds = 2Δ/e. The microscopic origin of this sub gap conductance (GSG) is explained in terms of Andreev reflection3 that takes place at the two nanowire−superconductor (NW-S) interfaces. For an ideal device with interface transparency close to 1, the ratio of the sub gap conductance to the normal conductance (GSG/Gn) can be equal to 2, due to the doublecharge transfer in the Andreev reflection process.2 As can be inferred in Figure 2b, the high conductance ratio of our device, GSG/Gn ∼ 1.4, indicates that it possesses highly transparent
standard Si-substrates capped by 400 nm thick SiO2. In both sets of samples, we used 80-nm-diameter InAs nanowires which were grown by chemical beam epitaxy in an ultrahigh vacuum.17 From field effect measurements of the conductance as a function of gate voltage G(Vg) near the pinch-off regime, we obtain an estimate for the electron mobility of μ ≈ 1500 cm2/ (V s) and average electron density n ≈ 1017 cm−3 at Vg = 0 at a temperature of 15 mK. These values correspond to a Fermi velocity of vF ≈ 108 cm/s and an elastic mean free path of le ≈ 20 nm. These values are comparable to what have been reported in similar devices,18 but exact numbers vary with Vg. Fabrication of the short devices was done in two steps (double lift-off) after InAs nanowires were transferred mechanically to the Si substrate. In the first step, 200 nm wide Ti/Al (5/150 nm thick) contact electrodes were defined with electron beam lithography. Figure 1a shows a scanning
Figure 1. (a) SEM image of a nanowire with superconducting electrodes separated by reasonably large distances. (b) SEM image of the same device with two more electrodes fabricated in between the already deposited electrodes. (c) SEM image of a suspended nanowire with a local gate. A simple schematic drawing of the current bias measurement is shown along with the SEM image.
electron microscope (SEM) image of the electrodes on the nanowire spaced intentionally at large distances. In the second step, we defined two more Ti/Al (5/150 nm thick) electrodes (also 200 nm wide) on the same nanowire in between the already deposited electrodes. A SEM image of the finished device is shown in Figure 1b. The double lift-off nanofabrication process offers the possibility to control the spacing between superconducting electrodes and, therefore, to make short nanowire devices that are beyond the limit of single-step e-beam lithography. In a single-step process, the distance is limited by the properties of the e-beam resist, and nanowire lengths are typically of the order of 100 nm. In our two-step process, the distance is instead limited by the alignment of the e-beam lithography patterns. The specified repeatability for our Joel 9300 e-beam writer is 25 nm. In practice, with carefully designed alignment marks, it can be made even smaller. Thus, we can with good reproducibility place source and drain electrodes at a distance of 30 nm from each other without getting short circuits between the electrodes. 5623
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(L ≪ ξ) and dirty (le ≪ ξ) limit. We measured an IcRn product of 128 μeV comparable to Δ ∼ 130 μeV. Even though this IcRn product is higher than what has been reported in similar devices, it is still a factor of 2 less than the expected value for short and dirty junctions.21 However, the maximum Ic, even for ideal short devices, is reduced due to an intrinsic Fermi-velocity mismatch at the NW-S interfaces which in turn lowers the IcRn product.22 At high bias, a linear fit of the IVC does not extrapolate to the origin, but rather to a finite excess current Iexc = 1.2 μA which is due to Andreev reflections. The interface transparency can be estimated from the extrapolated excess current and normal resistance.23 Using the values Δ ∼ 130 μeV and Rn = 165 Ω, we get eIexcRn/Δ ∼ 1.5 which corresponds to scattering parameter Z = 0.5 (see Figure 6 in ref 23). The transparency of the interfaces is therefore calculated to be T = 0.8, using the relation T = 1/(1 + Z2). We believe the estimated interface transparency will increase if the Fermi velocity-mismatch at the NW-S interfaces is taken into account. Hysteretic behavior was not observed in the IVC which indicates a junction with small normal resistance and small capacitance due to the lateral configuration of the junction with a significant distance between the superconducting electrodes. The junction dynamics can be explained by the resistively and capacitively shunted junction (RCSJ) model.24,25 From the geometry of our device, we estimate a capacitance of the order of 1fF, which results in a Stewart-McCumber parameter of β = 2eIcR2nC/ℏ ≈ 0.1 ≪ 1, from which we expect a nonhysteretic IVC consistent with what we observe. The magnitude of Ic as a function of temperature is plotted in Figure 2c. For temperatures below 300 mK Ic does not change significantly. Above 300 mK, Ic decreased monotonically. A complete suppression of the supercurrent was observed at Tc = 1.06 K. At the base temperature, we also measured IVCs as a function of magnetic field. The magnetic field was applied perpendicular to the leads and the nanowire conducting channel. As can be seen in Figure 2d, the magnitude of Ic decreased and was totally suppressed at a critical magnetic field of Bc = 40 mT. No Fraunhofer oscillations were observed in
Figure 2. (a) Current−voltage characteristic for a 30 nm long nanowire junction at temperatures of 15 mK (blue) and 1.5 K (red). (b) Differential resistance extracted from the current−voltage characteristic at 15 mK. Magnitude of the critical current as functions of temperature and magnetic field are shown in panels c and d, respectively.
interfaces. In all of our junctions, we observed many voltage steps at lower current bias, which are seen in Figure 2b as strong peaks in the resistance; these features are similar to those seen by Xiang et al.15 At the base temperature of 15 mK, the supercurrent branch showed a maximum critical current of Ic = 800 nA. This high value of Ic is attributed to the short channel length and the highly transparent interfaces. Considering the elastic mean free path of le ≈ 20 nm and the coherence length in the nanowire ξ = (ℏD/Δ)1/2 ∼ 200 nm, where Δ ∼ 130 μeV and the diffusion constant D = vFle/3 ≈ 60 cm2/s, the junction falls in the short
Figure 3. (a) An image plot of differential conductance for negative gate voltages near to pinch-off. (b) An image plot of differential conductance for intermediate gate voltages where we observe the interplay between Coulomb blockade and the supercurrent. (c) For higher positive gate voltages, the device shows more of superconducting behavior with enhanced conductance for Vds < 2Δ/e. (d) Differential resistance at Vg = 2.9 V. 5624
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important both for devices and in fundamental studies, for example, in the search for Majorana fermions. In addition, we have demonstrated widely tunable charge transport through a suspended sample. With a local gate voltage, the overall conductance of the device was tuned from a completely insulating to superconducting, combining different regimes of transport in a single device.
any of the devices, which is consistent with a suppression of superconductivity in the leads. This is also supported by the fact that the enhanced conductance at Vds < 2Δ/e decreased to the normal state conductance as the magnetic field was increased to Bc and above. Suspended samples, as shown in Figure 1c, were fabricated with an additional gate. These samples were substantially longer than the previously discussed samples. At zero gate voltage (Vg = 0), the room temperature resistances of the suspended junctions range from 1−10 kΩ, and most devices exhibited intrinsic n-type behavior such that the overall normal resistance monotonically decreased as the gate was stepped from negative to positive voltages. Here, we report on the device with the highest normal resistance of 10 kΩ and with a nanowire length of 300 nm. The IVCs for different gate voltages were taken at the base temperature of 15 mK. The differential conductance as a function of Vg and Vds exhibited different regimes of transport in the same device. At high negative gate voltages, Vg < −1.1 V, the nanowire was completely depleted of charge carriers. At Vg = −3 V, the device showed no electrical conductivity for |Vds| ≤ 0.5 V. At negative gate voltages close to the pinch-off, Vg = −1.1 V to −0.5 V, and near to Vds = 0 V, the device showed Coulomb-blockade diamonds. The Coulomb blockade, shown in Figure 3a, can be understood from the reduction in the carrier density in the wire, which increases the resistance of the barriers above the resistance quantum, resulting in charge quantization on the wire. For Vg ≈ −0.8 V, a charging energy of Ec = e2/2CΣ ≈ 3.5 meV can be estimated from the average size of the Coulomb-blockade diamonds, where CΣ is the total capacitance of the island, that is, the nanowire. Along the gate voltage axis, the period of the Coulomb-blockade oscillations is approximately δVg ≈ 0.1 V, which corresponds to a gate capacitance of Cg = e/δVg ≈ 1.6 aF. The differential conductance for intermediate positive gate voltages is plotted in Figure 3b. At low bias near to Vds = 0 V, the device transport behavior showed interplay between blocked states (deep blue) and supercurrent states (deep red) depending on the gate voltages. For Vds = 600 μV > 2Δ/e, the differential conductance is modulated by Vg on the order of one quantum of conductance (e2/h). For even higher positive gate voltages, the sample showed only superconducting behavior. A surface plot of the differential conductance, for Vg = 3 to 3.1 V, is shown in Figure 3c. From the color plot we can see that the conductance increases as the source-drain voltage goes below Vds ∼ 260 μV, similar to the situation for the short devices. At Vds = 0 V, we observe an Ic of 4 nA at Vg = 3.1 V (not shown here). The differential resistance at Vg = 2.9 V is plotted as a function of Vds in Figure 3d. We can clearly observe that the differential resistance decreases from a normal resistance Rn = 10 kΩ to a subgap resistance RSG = 5.2 kΩ. The ratio Rn/RSG ≈ 1.9 indicates that the interfaces are highly transparent, close to ideal, at the specified gate voltage. Also in this sample, we observe sub gap structures similar to those seen in the short devices. In conclusion, the double lift-off nanofabrication process enabled us to make very short nanowires contacted by superconducting electrodes. It was possible to fabricate devices as short as 30 nm with good Ohmic contacts. As a result, the magnitude of the critical current was increased by almost an order of magnitude compared to earlier reports. We achieved a maximum critical current of 800 nA. High critical currents are
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AUTHOR INFORMATION
Corresponding Author
*E-mail:
[email protected]. Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS We acknowledge fruitful discussions with Vitaly Shumeiko, Daniel Persson, Mikael Fogelström, and Lars Samuelsson. The work was supported by the Swedish Research council.
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REFERENCES
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