High-speed Charge-to-Count Data Domain Converter for Analytical Measurement Systems T. A. Woodruff and H. V . M a l m s t a d t l School of Chemical Sciences, University of Illinois, Urbana, 111. 67801
A new data domain converter is described that has important applications in atomic and molecular spectrophotometry, gas chromatography, mass spectrometry, polarography, and other analytical measurement systems where current or charge outputs from transducers need to be converted accurately to numbers. The new converter can be operated in a charge-to-digital count mode or a current-to-frequency mode. It achieves a large dynamic reserve which enables it to accept, without measurement error, transducer signals that have large amounts of inherent or external noise superimposed on the desired average signal. The technique allows measurements of subnanoampere currents to be made with a unique combination of speed, accuracy, and wide dynamic range. The converter has a maximum output frequency of 5 MHz and begins to produce the correct output frequency within 300 nsec after a step input. The basic principles, system design, and experimental data for the g-to-N and i-to-f converter are presented.
In scientific instruments, there are many transducers, such as photomultiplier tubes and flame ionization detectors, that convert information from the chemical or physical domains into related analog current or charge outputs ( I ) . The accurate conversion of these electrical current or charge signals into related numbers is obviously important and can be implemented in several ways. Each conversion method is subject to certain limitations, It is the purpose here to describe the design and performance characteristics of a new high-speed integrating analog current-to-frequency (i-to-f) or analog charge-to-digital count (q-to-N) converter. This new converter is especially well suited for the measurement of the current or charge outputs from transducers that have great utility in atomic and molecular spectrophotometry, gas chromatography, mass spectrometry, polarography, and other analytical measurement systems. It has been common practice to convert the transducer current or charge output into a proportional voltage which is then measured with a servo potentiometric recorder, a digital voltmeter (DVM), or other voltage measurement device. In some older models of DVM's (2-4) and in some very recent designs for DVM's (5-.7),various types of voltage-to-frequency (u-to-f) converters have been used enroute t o conversion of the input voltage to a number on a Send request for reprints to this author. (1) H . V. Malmstadt. C. G . Enke. and S. R. Crouch, "Analog Electronic Measurements and Transducers," W. A. Benjamin, Menlo Park, Calif., 1973, pp 28-36. ( 2 ) Heath Co , Benton Harbor, Mich., "Instruction Manual for the EU8 0 5 UDI.' 1968. (3) Hewlett-Packard, Palo Alto, Calif., "Selecting the Right DVM," Application Note 158. 1973. (4) Vidar, Mountain View, Calif , Bull No. 1 4 5 A , 1973 (5) N. Strong, Electronics. 45 ( 1 9 ) . 102 ( 1 9 7 2 ) . ( 6 ) R C. Kirne, Jr., Electronm. 46, ( 1 1 ) .9 7 (1973) ( 7 ) R . A. Pease. Electronics, 45 ( 2 2 ) . 127 ( 1 9 7 2 ) .
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digital readout device. The i-to-f or q-to-N converter described here is quite similar in principle to many u-to-f converter designs. A major advantage of the new converter is that charge or current transducer signals are converted to digital numbers without use of an intermediate i-to-u converter. It eliminates any errors that might be introduced when using a specific i-to-u or q-to-u converter, especially with respect to range-changing errors when measuring transducer signals over a wide dynamic range. By eliminating the intermediate analog data domain conversion, and instead immediately digitizing the transducer output, the new converter achieves a large dynamic reserve which enables it to accept, without measurement error, transducer signals that have large amounts of inherent or external noise superimposed on the desired average signal. The technique also allows measurements of subnanoampere currents to be made with a unique combination of speed and dynamic range. Several modular u-to-f converters have recently become commercially available ( & I O ) , some of which have an auxilliary current input (11, 12), but the current range is fixed a t a relatively insensitive value of typically 1 milliampere full scale. The converter described in this paper, however, has current ranges of 1, 10, 100, and 1000 nanoamperes, and additional ranges can easily be added of either greater or less sensitivity. The available c-to-f converters do not usually have the conversion rate or speed of response necessary for many analytical applications. For example, the fastest commerically available u-to-fs have a maximum output frequency of 1 MHz, allowing a maximum resolution for a 1-millisecond measurement of one part in a thousand. The converter described here, however, has a maximum output frequency of 5 MHz, and begins producing the proper output frequency within 300 nanoseconds (for the one hundred- and one thousand-nanoampere current ranges) after a step input; one of the commercial 1-MHz devices requires up to 10 microseconds settling time. The new converter also offers selectable full-scale output frequencies that enable an optimum tradeoff to be made between resolution and other characteristics such as linearity. For example, a t 1 MHz, nonlinearity is only about 0.005%. A feature inherent to the design of the converter is that its transfer function remains highly linear down to essentially zero input, even at of full scale or less. Some commercial devices have a limited useful dynamic range because of gross nonlinearity below about 1% full scale. For the new converter, as well as the commercial units, an output frequency of, for example, 1 MHz, measured for 1 second does not mean that a precision (repeatability) of 1 ppm will be obtained; noise sources in the instruments limit the maximum precision attained. This precision (8) Intech. Inc.. Santa Clara, Calif , A-843 V,'F Converter Bull., 1973. (9) Optical Electronics Inc., Tucson, Ariz., "Catalog 73." 1973. (10) Solid State Electronics Corp., Sepulveda. Calif , Series 300 VF Bull ( 1 1 ) Eleclronic Products, 16 ( 1 ) . 189 ( 1 9 7 3 ) . ( 1 2 ) Teledyne Philbrick. Dedham, Mass., Series 4705,'Ol Bull.. 1973.
A N A L Y T I C A L C H E M I S T R Y , VOL. 4 6 , NO. 9 , A U G U S T 1 9 7 4
specification with noise is usually not given for commercial u-to-f converters, except when incorporated in DVM's. The converter described here gives typically 0.00(I7% precision for a 1-second measurement (for inputs of 30% full scale up) and 0.002% in 100 milliseconds. At integration times of about 10 milliseconds and less (depending somewhat on full scale output frequency), the one-count uncertainty inherent in unsynchronized frequency measurements becomes a limiting factor. Since the new converter is a complete system which directly accepts and digitizes the output of many important analytical measurement transducers, the signal degradation inherent in analog signal processing due to noise pickup, drift, and inaccuracies, is minimized and the maximum errors to be expected are precisely defined. The converter provides an output proportional to the integral of the input signal over an interval that may be precisely and simply defined by using one logic gate to control the entry of converter output pulses into a digital counter. This provides both the maximum possible utilization of the information content of the transducer signal (maximizing signal-to-noise ratio), and an easily variable measurement interval. The same circuitry used for processing the digitizer output may be used with transducers operated in an event counting mode, for example in photon counting. In fact, a digital signal in the form of a pulse train is exceptionally convenient for subsequent data handling. The digital pulses produced by the digitizer can be easily and reliably transmitted through noisy environments over a two-wire cable, isolated with a single optoelectronic coupler, recorded on magnetic tape, etc. Scaling or normalizing (multiplying by a constant) of the frequency output may be easily achieved using a digital rate multiplier (13). As already mentioned, drift-free integration with respect to time is achieved by summing the pulses from the digitizer in a digital counter during the desired time interval. The result can be obtained in any number base, or several, by using counters of the appropriate modulus. By using up/down counters, successive signals may be subtracted from each other or differentiation performed ( 1 4 ) . Simple procedures for obtaining the ratio of two frequencies have also been described (15). Because of the convenience of the frequency output, an i-to-f or c-to-f converter is very easiiy adapted to bipolar operation and to automatic zeroing to eliminate any offset drift (57. BASIC PRINCIPLES The basic equations and diagrams are presented in this section so as to illustrate how the new converter operates as either a q-to-N or an i-to-f converter. These basic relationships are also used in subsequent sections to show how certain parameters are selected for implementation of the converter. Charge-to-Count Conversion. The new converter operates on the basis of' a servo charge comparison method, as illustrated in Figure 1. The output unknown charge q , from a transducer is fed into the input of a charge comparator. Small accurate increments of charge, q,, are fed into the charge comparator in opposition to the unknown charge 4,. A number nr of the accurate charge increments q r are fed to the comparator until the reference charge 4,. (which is q,n,) is equal to 4";in other words 9 , incremen113) "The TTL Data Book, Texas. 1973, p 248 (14) J D Ingle. J r . . and S. R (151 H. V. Malmstadt. C. G log Data Conversions,' Chapter 3 . '
1st ed
,
Texas Instruments lnc
,
Houston,
Crouch, Anal. Chem.. 42, 1055 (1970) Enke. and S R . Crouch. "Digltal and AnaW . A Benlamln. Menlo Park, Callf , 1973,
SIGNAL FOR T U R N I N G REFERENCE SOURCE ON AND O F F
uo2
I
SOURCE OF UNKNOWN CHARGE, q u , INCREMENTS
, TO BE MEASURED
COUNTER O F REFERENCE
Figure 1. Diagram illustrating general building blocks for the analog charge-to-digitalnumber (9-to-N) converter
tally follows q, so that 9 , = q , = qir',
(1)
and since the charge increments qr can be accurately preset and maintained a t a constant quantity k of charge, q, = hnr (2) Therefore, the unknown charge is converted directly to a number. The general method of implementing the electronic servo charge comparator is illustrated in Figure 2. The transducer input always remains connected to the summing point S of a F E T operational amplifier, OAl, which is wired as an integrator with a feedback capacitor, C. As the input charge q, charges C, the voltage output of OAl changes which causes the comparator output to switch to a logic 1 or Hi level. The output of the comparator is used to control a gate circuit. Whenever the input of the gate circuit is a logic 1, successive accurate time increments from a crystal clock oscillator appear a t the gate output terminal. These accurate time periods t , from the clock, control an analog high-speed switch S1. The switch S1 connects an accurate reference voltage V, to a resistor R, which is connected to the summing point of OAl. The accurate reference charge increments q, are thus provided by switching S 1 OS to give a current V ,/ R , for accurate time intervals t , so that
VI t:
q - = - = k
R,
(3)
Note that each feedback pulse of time t , is separated by a minimum time t,. Thus, a t most, one converter output pulse can appear in the time 2 t,, and the maximum rate of producing output pulses is the clock frequency, f c = I/z t, . An appreciation for the charge resolution is readily seen by substituting some typical values into Equation 3. For example, if V , = 4V, R , = 2 x IOs R and t , = 0.5 gsec (clock frequency = 1 MHz), then,
That is, each reference charge packet that is gated into coulomb. Therefore, the comparator contains 1 x the dynamic range with the given preset parameters would be from coulomb (the resolution) to any upper limit set by the counter capacity for n,. If the counter capacity is lo6 counts, then the upper charge limit is 10-8 coulomb; if 1OI2 counts, it is coulomb, etc. However, it is important to note that the average unknown input charge should not exceed the maximum rate of generating reference charge. This upper average rate of charge input is determined by the product of clock frequency and the value of k , and for the given example
A N A L Y T I C A L C H E M I S T R Y . V O L . 46, N O . 9, A U G U S T 1974
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1 '*$
CRYSTAL CLOCK OSCILLATOR
I
CONVERTER
nr or
fu
Figure 2. Diagram showing basic operation of the q-to-n and i-to-f converter
would be (1 x 106)(1x = 1x coulomb/sec. The peak input charge rate may exceed the maximum average rate by manyfold, the excess charge being temporarily stored in the integrator capacitor, providing the reference charge generator is allowed to catch up with the input in subsequent intervals. This gives the converter its large dynamic reserve. Current-to-Frequency Conversion. The same general diagram of Figure 2 can be used to illustrate the operation of the charge comparison system as an i-to-f converter. For discussion, it is assumed that the transducer input current i, is in the direction illustrated by the arrow (for example, this would be the case for a photomultiplier where the anode is connected to the charge comparator input terminal). The transducer is connected to the input continuously, but the digital counter is gated open for only a time tu so that the integrated current during the time the counter is ON is equal to q u = iutu. The analog switch S1 is closed for a total time t , = tgnr during the time tu. The analog switch S1 is open for a time tu - t,, and during this time the total charge q , ~from the transducer is: Y,
=
- t )
l"(fL,
= (Ir
-
l U )t ,
- t,)
= ( 1 , - 1,)
t,
(6)
and reducing Equation 6, 1,t"
=
I,t,
and substituting in Equation 7 for tgnr,it follows that 1164
17) 1,
(2) n,
=
kn,
0 1'.
where f u is the average frequency over the counter gate time tu. For example, if the reference voltage V, = 4 volts, the input resistor R , = 2 x 108 ohms, the clock oscillator frequency = 5 MHz ( t P = 0.1 psec), and the counter is gated open for t u = 1 sec. during which n, = 5 x lo6 counts, then from Equation 9 =
4 x 0.1 x 2 x 10'
(
5 x lo6 -
)7--
Thus with a 5-MHz full-scale output frequency and a 1 ampere full-scale input range, the current resolution is 2 x 10-15 ampere/count. Since the maximum frequency is the clock frequency f c t,, it can be seen by substituting into and because f, = Equation 9 that the full-scale current is
x
(10) That is, the full-scale current sensitivity is essentially independent of the clock frequency. However, the current resolution is influenced by the clock frequency.
(5)
The analog switch automatically opens and closes so that over a period of time t u the total charge q U l added during the time, t u - t , (switch open) is equal to the charge q , subtracted during the time t , (switch closed) so that, 1"(t"
=
(4)
For the total time t, that the switch S1 is closed, the reference current is applied to the charge comparison system but since the transducer input is also connected the charge delivered is:
4,
;,tu
= V , / R , and t, =
INSTRUMENT DESIGN
Each of the functional blocks illustrated in Figure 2 for the q-to-N and i-to-f converter is described in this section. The circuit details of the charge comparator are described, and then the details of the source of reference charge increments are presented. The schematic diagram is shown in Figure 3, but the details of the range switching and internal power supplies are presented elsewhere (16). The digital counter can be any of the inexpensive commercial counters with sufficient count capacity for the (16) T A Woodruff and H V Malmstadt to be submitted to Rev S o lnstrum
A N A L Y T I C A L C H E M I S T R Y , VOL. 46. NO. 9, AUGUST 1974
XI
-
r
Rr
CHAR= COMPARATOR
v-to-i CONVERTER > A I
4
.
FROM ENCODED FREQUENCY SELECT SWITCH.
A-
SPEED ANAIDG
I
SWITCH U IC9A
IC98
~ IC9C
U
I
IIC12D
I
OUTPUT, f p ,
-/r
RANGE
SiWITCH_ED
POTS
I + 15
I
L
REFERENCE VOLTAGE SOURCE
Figure 3. Schematic diagram of q - t o 4
nr
ALL CAPACITORS ARE DISK CERAMIC AND VALUES ARE IN PF, EXCEPT FOR POLARIZED UNITS WHICH ARE SOLID TA, VALUES IN fif. A L L FIXED RESISTORS ARE lYo, 1/2W, UNLESS OTHERWISE NOTED. ALL TRIMPOTS ARE BOURNS MODEL 3009P. C lOPF AT lO-’A, 200 PF AT lob A; POLYSTYRENE C 1 2-6.8pF, 6 V TA AND 2-0.01pF DISK, ALL IN RPRALLEL C2 6 8 p F , 6 V TA AND 0.1pF DISK IN W R A L L E L C3 2 - 6 8 p F , 6 V TA AND 2 - 0 . 0 1 p F DISK, ALL IN WRALLEL Dl-D3 1N914 0 4 - D 5 DIALIGHT 5 2 1 - 9 1 6 8 LED D 6 4 7 1N3066 D 8 - D 9 1N93 D10 1 N 4 0 0 1 IC1 SlGNETlCS N E 5 2 9 K I C 2 FAIRCHILD 733HC I C 3 74S112 IC4,8,9,12 74900, CERAMIC DIP I C 5 MOTOROLA M C 4 0 2 4 P I C 6 74153 I C 7 FAIRCHILD 723DC I C 1 0 , l l 7490 OA1 HARRIS HA-2055A, WAKEFIELD 209AB HEAT SINK OA2-5 EACH IS HLLLf OF A RAYTHEON RC4558DN OC1 GENERAL ELECTRIC H 1 5 A 1 OPTOISOLATOR 01,2 2 N 5 1 3 8 Q3,4 2 N 5 1 3 5 Q5 2N2905A X I JAN CRYSTALS, FORT MYERS, FLORIDA
converter
specific application, and with frequency response greater than the maximum converter count rate (which is 5 MHz at present). Charge Comparator. The charge comparator consists basically of an input F E T operational amplifier connected as an integrator and an integrated circuit voltage comparator as illustrated in Figure 2, but several other cornponents are needed as shown in Figure 3. The absolute value
of the feedback capacitor C for O A l is not important but it must be within a certain range of values for suitable operation with different full-scale current ranges. The basis of selecting C for different ranges is discussed in this section. OA Integrator. The input integrator circuit is shown in the charge comparator block of Figure 3. The operational amplifier O A l is a moderately priced (less than $20) inte-
A N A L Y T I C A L C H E M I S T R Y , VOL. 4 6 , N O . 9, A U G U S T 1974
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grated FET input OA providing a typical input bias current of l pA and a rise time of 25 nsec. It is used with a small heat sink, which minimizes the input bias current. Pin 8 on the OA is normally used for external frequency compensation if needed (for noise gain of less than three), but it is used here only to limit the maximum OA output voltage of *3 V. This protects the following voltage comparator stage, and is accomplished by the diode-resistor network shown connected to pin 8. The OA, and the “range switch” on which its feedback capacitor C and the resistor R, are mounted, are enclosed within a copper box and thus shielded from the remainder of the converter circuitry, except for the necessary interconnections. The entire instrument, including the internal shield, is housed within a small steel cabinet. Selection of Feedback Capacitor. It can be seen by the basic equations (Equations 3 and 9) for the 9-to-N or ito-f converter that the output is independent, in principle, of the value for the feedback capacitor C. However, there are some practical considerations in maintaining optimum performance of the system which require some gross changes in capacitor C as ranges are changed. These considerations are presented in this section. The OAl contains an internal 10-pF feedback capacitor so that no external feedback capacitor need be used for or 10-*-A current ranges. For the current rangthe es, lo-’ and A, additional, larger, external capacitors are switched into the feedback loop using a front panel “range“ switch. These capacitors are selected to be sufficiently small so that when an amount of charge 9, from one feedback pulse is added to the integrator, the resulting OAl output voltage swing is sufficient to drive the voltage comparator to change output state. This is necessary if measurements with a precision of one count are to be made. For the current ranges below l o t 6 A, the ratio of the feedback capacitance to the instrument input shunt capacitance is such as to give a noise gain of about three or greater, so that no OA compensation is needed. For the 10-6-A range, the larger feedback capacitor tends to decrease the noise gain. Rather than provide unity gain compensation for the OA for all current ranges (which might decrease performance on the lower ranges) or change the compensation for the 10-6-A range, an extra 390-pF capacitor is connected from one side of the feedback capacitor for this range to ground, such that when the feedback capacitor is switched into the circuit, the 390-pF capacitor is introduced between the summing point and ground. On the 10-6-A range, the use of a significantly larger feedback capacitor than that chosen would, in conjunction with the extra 390-pF capacitor, produce excessive phase shift in the OA output stage. The use of a smaller feedback capacitor than necessary would be undesirable as it would decrease the maximum integrator charge storage capability, equal to the product of the capacitance and the maximum OA output voltage. This would reduce the instrument’s dynamic reserve. A smaller capacitor would also increase the high frequency input impedance a t the OA summing point. Since the OA has a finite rise time, it cannot respond instantly to step current inputs; however, the small high-frequency impedances of the feedback capacitor, and instrument input shunt capacitance, provide paths to either the low impedance OA output or ground, respectively. For the 1-microampere current range, and especially for ranges greater than A, if it were desired to add them, it would probably be most desirable to use an OA for the integrator that was unity gain compensated (so that the extra shunt capacitor described above could be eliminated) and that also had an added booster output stage to 1166
ANALYTICAL CHEMISTRY, VOL. 46,
NO. 9 ,
maintain a relatively low amplifier output impedance and, hence, low high frequency input impedance. Voltage Offset Nulling. The capability of nulling the instrument input offset voltage is provided by slightly varying, from the nominal value of ground potential, the voltage applied to the non-inverting input of the FET OA. This voltage is generated by OA2 (Figure 3), which allows for coarse and fine adjustments of the offset and provides a low impedance source for driving some additional circuitry, as described in the analog switch section. Voltage Comparator. The OA integrator produces a voltage output that is proportional to the charge stored; the voltage comparator described in this section senses whether the integrator output voltage is above or below zero (ground potential) and, hence, whether the stored charge is plus or minus. By providing a logic level 0 or 1 output, the voltage comparator thus completes the circuit of the charge comparator. Referring again to Figure 3. the actual comparator, IC1, is preceded by a differential video amplifier (IC2) connected for a nominal gain of 100. The voltage comparator used has sufficient gain, considering the transfer function of the logic circuit driven by it, to theoretically resolve the sub-millivolt integrator output voltage swing that corresponds, for the 1- and 10-nanoampere current ranges. to the amount of charge in one feedback pulse. However, comparator response speed is maximized by providing a t least 1 mV of overdrive. Comparators also often oscillate if sufficient overdrive is not present to force them to one of their output limits. Consequently, the preamplifier was included, although some checks indicated that it could possibly be eliminated without significantly affecting instrument performance. This would certainly be true for the lo-’- and 10t6-Acurrent ranges. Transistors Q1-Q3 and associated components form two simple comparators which are also connected to the integrator output. Their purpose is to indicate. via front panel lights and a logic level signal, when the integrator output voltage exceeds h1.5 V, and thus may be limiting or approaching limit. The overrange light is activated when the charge input to the instrument is excessive, while the underrange light is activated when a large positive charge has been stored in the integrator. This could happen because of improper instrument offset adjustment. Extreme noise pickup, such as may occur when poor shielding practices are followed and current from the power lines is capacitively coupled onto a low level transducer signal, can cause both lights to appear activated as the integrator output swings rapidly between its positive and negative limits. Any of these conditions activates the common logic-level error indicator. Source of Reference Charge Increments. The method for generation of the reference charge increments is illustrated in principle in Figure 2 and in detail in Figure 3. A high-speed analog switch is turned ON and OFF so as to alternately connect and disconnect a very stable reference voltage V, across resistor of resistance R , . This provides a stable current it = V , / R , . Since the switch is driven by a very accurate crystal clock oscillator each ON period. t,, is accurate, and the charge content in each packet. qr! = i,t,, is also very reproducible and accurate. Gate. The output of the charge comparator is applied to an edge-triggered J K flip-flop (part of IC3. Figure 3) which forms a simple gating and pulse shaping circuit. The second flip-flop contained in IC3 is not used, except as a logic one level source. The frequency output from the crystal oscillator clock is applied to the toggle input of the flip-flop. While the period of the oscillator is highly stable, the waveshape is often not precisely defined or stable;
AUGUST 1974
consequently, the gate circuit was designed to produce output pulses of a duration equal to the oscillator period. Since a t least an equal interval is present between output pulses, the maximum output frequency from the gating circuit is one half of the input frequency. For convenience, the maximum flip-flop output frequency, which is also the full scale output frequency of the digitizer, is referred to throughout this paper as the “clock frequency.” T o begin the analysis of the gate circuit, consider the flip-flop Q output to be low. The negative-edge triggered flip-flop may be toggled on each logic 1 to logic 0 level transition of the clock, depending on the states of the flipflop J and K inputs. The K input is held continuously a t a logic 1 level. The flip-flop Q output will remain low if the J input is 0 at a 1 0 clock transition. If J is 1, the Q output will go to 1 and remain there until the next clock falling edge (or for one clock period), and then return to logic 0. At the next clock 1 0 transition, the Q output again can either remain a t 0 or go to a logic 1 for one clock period, depending on the state of the J input. Thus the flip-flop generates and gates pulses of a precisely known duration, the period of the crystal oscillator frequency, whenever the charge comparator output is high. A Schottky T T L flip-flop is used because it offers high switching speeds that are relatively insensitive to power supply and/or temperature variations. This is important because the frequency output obtained for a given input current is directly dependent on the length of the pulses produced by the flip-flop. The crystal controlled oscillator frequency is generated using standard TTL; three seriesconnected Schottky T T L inverters buffer the oscillator signal to ensure a fast clock transition a t the flip-flop input. This may also be expected to aid in achieving constant-length output pulses. Another inverter is used to buffer the output of the flip-flop. This logic circuitry is powered via a separate voltage regulator, as is described elsewhere ( I 6 ) , in order to ensure a stable 5-volt supply that will not be influenced by external factors. The gate which buffers the flip-flop output in turn drives gate IC4A, which provides the instrument back-panel output. This inverter is powered from the external 5-volt supply. Crystal Clock Oscillator. Figure 3 also shows the selectable frequency source used to set the feedback pulse width t , and digitizer full-scale frequency output. IC5, a TTL compatible multivibrator, is used with crystal control to provide a highly stable 10-MHz output frequency. The 10-MHz standard frequency may be divided in several stages to provide a range of frequencies down to 200 KHz. The corresponding converter output frequencies are, then, 5 MHz to 100 KHz. Any one of the 6 frequencies available may be selected through a multiplexer, IC6, which is controlled b y a front panel switch. The selected frequency is applied to the gating circuitry already discussed. An important consideration in designing this circuit was that, for any selected output frequency, only the divider stages necessary to produce that frequency be activated. Other stages, which would operate a t lower frequencies, should not be allowed to toggle. Allowing them to do so can cause a very slight jitter in the times of the logic level transitions for the selected frequency. This jitter would average out and be insignificant were it not for the fact that it is synchronized with the pulses produced by the gating circuit already discussed. If allowed to occur, this synchronized jitter degrades the instrument’s differential linearity. Reference Voltage Source. The reference potential for the digitizer is derived from a lightly loaded integrated +
+
circuit voltage regulator, IC7, having a typical temperature coefficient of 0.002% per degree C. This +7-V signal is inverted by OA3 to provide a -7-V reference. These two voltages are used with the instrument voltage and current offset circuitry, where H V is indicated in Figure 3. However, the chief importance of this reference source is in setting the instrument feedback reference voltage, V,, and hence controlling the scale factor. The -7-volt reference is applied through scale factor adjustment potentiometers to the summing point of OA4. OA4, with series pass transistor Q4 serving as a booster, provides a nominal +4 V which is used as V,, the voltage applied to the analog switch. Voltage V, may be varied slightly by varying the individual scale factor adjustment potentiometers for each current range. These are switched into the circuit by the “range” switch and were provided for several reasons. Feedback resistors R , in values greater than 10 or 100 megohms are difficult or impossible to obtain with accuracies significantly greater than 170, and further. often drift somewhat with time as well as with ambient temperature changes. A variable reference voltage provides a convenient means of compensating for these changes. Also, when the instrument clock frequency is changed, the apparent V, will vary slightly (less than 2.5% for all ranges and frequencies) with changes in clock frequencies because of slight deviations from the theoretical feedback pulse width, t,. High-speed Analog Switch. The analog switch is driven from the output of the flip-flop used in the gate circuit and switches the feedback reference voltage V,. A Schottky T T L gate with an active pullup output is used as the high speed analog voltage switch. There are a number of reasons for this novel choice: the device may be obtained for less than one dollar, is directly T T L compatible, can be used in a fashion that provides very acceptable analog switching accuracy, and most Important, provides faster switching than virtually any conventional precision analog voltage switch-switch driver combination. This high speed switching is vital if high clock frequencies are to be used, since the stability of the digitizer is dependent upon generating pulses that have a high relative stability, even though lasting for as little time as 100 nsec (for a 5-MHz clock). The normal output levels provided by a Schottky TTL gate are approximately 250 mV for a logic low, and 1.5 V less than the supply voltage for a logic one. These voltages are for 10-mA current sinking at a logic low or no load for a logic high, and are with respect to the integrated circuit ground pin. T o use the circuit as a precision analog switch, it is necessary to eliminate the 250-mV offset in the low output state, and bring the high output voltage up to precisely Vr. This is accomplished as follows: Gate 1 of the four gates in a package is used as a reference with the output kept continuously a t a logic low by applying a high logic level to the input of the gate, which is inverting. The voltage a t this output is adjusted to zero by taking the package ground to approximately -0.25 V; this adjustment is accomplished automatically using an O A feedback circuit. The other gate outputs will then have a logic output level of approximately zero volts. One of these other gates, gate 2 , may then be used as the analog switch, with an output of zero when a logic one is applied to the input of the gate. Shifting the circuit ground slightly does not significantly affect the driving of the circuit by normally connected logic. When the input to the gate being used as the analog switch goes low, the gate output is pulled up to about 3.5 V by the internal active pullup circuitry. A 400-ohm resistor connected between the gate output and the reference voltage V, completes bringing
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the analog switch output up to the value of V,, about 4 volts. So long as V, is greater than 1.5 V less than the gate supply voltage (or about 3.5 V), the steady-state current flow in the 400-ohm resistor is negligible. The complete characterization of the logic gate used a s an analog switch, and the procedures for selecting the best gates in a package to use for the various functions, are presented elsewhere (16). The third gate in the package has its output connected via a 400-ohm resistor to V, just as for the gate used as the analog switch, but the input to this third gate is inverted with respect to the input to the analog switch gate. The two gate outputs are thus always in opposite states. This allows the current drawn from V, and that sunk by the ground floating circuitry to be essentially constant, which minimizes the dynamic requirements placed on these sources and reduces any thermal duty cycle effects in the switch gate package. This gate output is brought into the shielded compartment containing R, along with the analog switch output, in order to minimize the effect of capacitance between the switch lead and the amplifier summing point. The fourth gate is not used, and its output is held continuously high to minimize power dissipation. It is necessary to compensate for any difference in the offset voltages of the gate used as the low output reference and the gate used as the switch, and to provide offset current adjustments for the converter. When the analog switch low output voltage is not exactly the same as the potential at the integrator summing point, a current will flow through R, to the integrator even when a feedback pulse is not being delivered. This is in addition to the normal input bias current of the FET OA. Both sources of offset current may be cancelled out by slightly changing the low state output voltage of the analog switch. Referring to Figure 3, OA5 with booster transistor Q5 serves to float the switch package (IC8) ground as described. Small adjustable currents are summed a t the inverting input of OA5 to slightly shift the switch package ground pin potential, and hence, the low level analog switch output voltage. Individual current offset adjustments are provided for each range by switching trimpots into circuit with the “range” switch. In order to prevent adjustments of the integrator input offset voltage from affecting the current offset as well, the noninverting input of OA5 is not tied to ground, but to the output of OA2; recall that OA2 drives the noninverting input of the integrator OA and provides the offset voltage adjustment. V-to-IConuerter. This final stage of the instrument consists of the precision resistor R, which converts the analog switch output voltage to a proportional feedback current supplied to the summing point of the charge comparator integrator stage. This V-to-I conversion deserves considerable discussion because, although it may appear simple, it is one of the most critical stages of the q-to-N converter as well as of the conventional feedback currentto-voltage amplifier. Separate resistors for each instrument current range are selected by the “range” switch (not shown in Figure 3). The switching circuitry is designed to minimize the capacitance between the analog switch input and the FET OA summing point; for this reason, the input side of all the resistors except the selected one is grounded. The resistors are selected for the desired current ranges in accordance with the equations given in the basic principles section, using 4 volts for VI. A comparison is made between the charge-to-count converter and the conventional feedback current-to-voltage amplifier to show how each is affected by the nonideal characteristics of the feedback resistor. The conventional 1168
circuit has serious response speed limitations when amplifying sub-microampere level currents, and a major cause of the response speed problem is the effective capacitance shunting the feedback resistor. Some capacitance is inherent in the resistor, and it is added to by stray wiring and switch capacitance. The value of the shunt capacitance due to the resistor may typically be on the order of only 0.2 pF, but for a 109-ohm resistor, the RC time constant is then 200 psecs. A frequency compensation technique is sometimes used for reducing the effect of this shunt capacitance through insertion of an auxilliary RC circuit in the feedback loop (17); however, one of the fastest available commercial current-to-voltage amplifiers, the Keithley model 427 ( l a ) ,achieves, for example, only a 220-microsecond rise time (10% to 90%) a t a gain of lo9 V/A A full-scale input for a 10-V full scale output). This is too slow for many analytical measurements and, although the response time may be improved by using smaller feedback resistors, this is often a t a sacrifice in signal/noise performance. In a current-to-frequency converter, the effect of this shunt capacitance, C, across R, is quite different. Each time the high-speed switch is activated, and V, is applied across capacitor C, (and R,), an amount of charge, q = C, Vr, is introduced into the integrator through C,. As the feedback pulse ends, and the voltage across C, returns to zero, an equal amount of charge is withdrawn from the integrator. These two transients thus cancel out, and the net charge transferred during the pulse is only the dc current through R, given by the equations in the basic principles section. By eliminating the effect of this shunt capacitance, the q-to-N converter achieves exceptionally fast response times. With the feedback resistor shunt capacitance effects largely eliminated. another effect has become noticeable on the one- and ten-nanoampere current ranges. This is the response time limitation posed by the capacitance between the resistor element and ground. The resistors presently being used in the instrument are of the conventional rather bulky type, which have a large area and, hence, a large capacitance to ground. However, miniaturized resistors are available which have no more shunt capacitance than the larger types, and more than an order of magnitude reduction in the area of the resistive element. In order to make the best of what was at hand, the resistor used for the one-nanoampere range. which actually consisted of two 1-G ohm resistors in series, had the middle junction point shielded by tube held. via a resistive divider, at one half of the voltage between the resistor input (from the analog switch) and ground.
RESULTS The testing of the q-to-N and z-to-f converter presents considerable problems because most commercially available test instruments do not have the precision. accuracy, programming speed. and other desired characteristics over the dynamic range that the converter is capable of operating. Therefore, special test devices and procedures were developed for the rigorous testing of the new converter, and these are presented elsewhere (16), together with the more complete characterization data for the converter. The data presented here are to illustrate some of the most important characteristics of the converter when it is used in analytical instrumentation. Test Instruments. A constant current source with a nonlinearity of 0.005% over five decades was constructed (17) P C a t h a n d A Peabody Ana/ Chem 43 (111: ;9 (18) Keithley Instruments Cleveland Ohio Catalog
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(19711 1973
Table I. Response of i-to-f Converter on 10-8-AFull Scale over Wide Dynamic Range of Input Current Input current, nA“
0.0001 0.0003 0.001 0,003 0.001 0.03 0.1 0.3 1.0
2.0 3.0 4.0 5.0 6.0 7.0 8.0
9.0 9.9
Average counts
8.9 28.8 100.4 296.6 998.0 2993.2 9994.7 29986.1 99972.0 199966 299964 399993 499991 600008 700006 799984 900013 990067
Precision, re1 std devb
18 10
4 0.7 0.3 0.06 0.015 0,010 0.003
0.0009 0.0016 0.0006 0.0005 0.0007 0,0008 0,0005 0,0004 0.0011
Accuracy,
% dev from
Clock freq, MHz
line
12 4 0.4
1 1
2.5 2.5 5 5
1.1
0.2 0.2 0.06 0.05
1 1
0.03
2.5 2.5 5 5
0.02 0.014 0.004 0.004 0.0010
1 1
0.0015
2.5 2.5
0.004 0.0009 0.004
5
‘Nanoampere source.
Table 11. Comparison of Converter Results in i-to-f and a-to-N Modes of Operation for 0.1-Sec Integiation
input currents to the converter from test instrument Based on averages of ten results.
and used to test the converter in the i-to-f mode. To generate known amounts of charge for testing the converter in the q-to-N mode, two different techniques were used. In one method, the reference source was switched ON and OFF with a series-shunt F E T analog switch. However, since this method is limited by resistor shunt capacitance at low currents, a second test circuit was devised consisting of a phototube. optical waveguide, and light-emitting diode which was pulsed ON and OFF (16). The converter pulses were counted in a modified UDI counter (Heath Co., Benton Harbor, Mich.) in which the BCD information held in the decade counting latches is brought out from the instrument on cables. Also, the signal used in the UDI to gate the information from the BCD counters into the latches is brought out as a “memory strobe” signal. The memory strobe signal from the UDI activated a teletype coupler so as to send out as ASCII code the BCD information newly entered into the latches. Rather than using the teletype as a simple data logger, the coupler and teletype were usually connected as a remote computer terminal with data logging through the teletype port of a DEC PDP-8/L minicomputer with a 4K word memory. Data points were taken about once per second, but the rate of collecting data was readily controlled by varying the setting of the UDI “Display Time” control. Ten data points were taken for every average count or frequency reported in the following tables. Linearity. One of ten i-to-f mode data sets collected for the A full-scale current range is shown in Table I. A 1-MHz clock frequency and a 1-second integration time were used so the full-scale current of A would give an output of lo6 counts/second, a 7-nA input current should give an output of 700,000 counts/sec., etc. From a quick comparison of the first two columns of Table I, it is apparent that the highly linear relationship between input current and output frequency holds over 5 decades down to essentially zero input current, even for this very sensitive current range. On the A range, the precision of the converter a t input currents which produce a small number of counts is limited by the F E T OA input noise. However, on this sensitive range, even a current of A (0.1% full scale) can be measured with a precision of 0.3%. The last column gives the percent deviation of each
5 1 1
2.5 2.5 5 5 1 1
2.5 2.5 5 5
Input Current, gA Charge, gC
Average counts
100.7 100.6 251.5 0,001 251.7 0.0001 496.8 0,001 501.5 0.0001 998.9 0.01 1000.0 0.001 2495.8 0.01 2497.4 0,001 4969.4 0.01 4971.8 0,001 9995.9 0.1 9995.8 0.01 24974.4 0.1 24973.9 0.01 49824.5 0.1 49811.9 0.01 29994.5 0.3 29993.7 0.03 74946.0 0.3 74942.8 0.03 149696.0 0.3 149661.0 0.03 90003.5 0.9 90002.6 0.09 225047 0.9 225049 0.09 450160 0.9 450151 0.09 0.001
0.0001
Std dev, c, counts
(,; Re1 std dev
0.7 0.5 0.7
0.6 0.7 0.9 0.7 2.5 2.3 0.6
0.7 0.5 0.3 0.4 0.2 0.4 0.06 0.07 0.04 0.03 0.05 0.05 0.006
0.8
0.008
1.6 1.9 6.0 5.1 0.8 0.7 2.2 2.3
0.006 0.008 0.012
1.1
1.2 1.8
8.1
9.6 0.7 0.7 2 .O 2.6 2.8 4.6
0.010
0.003 0.002 0.003
0.003 0.005 0.006 0.0008
0.0008 0.0009 0.0012 0.0006 0.0010
Table 111. Results for i-to-f and q-to-N Converter with 1-Millisecond Integration Input Clock freq., MHz
Current, PA
Charge, PC
Average counts
10.1 100 .o
Std dev, counts
1 Itel std dev
0.3
3 0.00
1 1
0.01
1 1
0.3
300 . O
0.0 0.0
0.9
900.3 9.6 99.7
0.5 0.5 0.5
300 . O
0.0
899.8 24.9 249.9 749.7 2250.3 24.7 249.7 750.2 2250.9 50.4 499 .O 1497.4 4499 .1 50 .O 499 . 0 1497.8 4501.1
0.4 0.3 0.3 0.5 0.5 0.5 0.5 0.4 0.9 0.5 0.7
0.1
1
10
1 1
100 300
900
1
2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 5 5 5 5 5 5 5 5
0.01 0.1 0.3
0.9 10 100
300 900 0.01 0.1
0.3 0.9 10 100 300
900
0.8
0.9 0.8 0.8
1.2 1.0
0.00 0.05 5 0.5 0.00
0.05 1.3 0.13
0.06 0.02 2 0.19 0.06 0.04 1.0 0.13 0.06 0.02 1.6 0.16 0.08 0.02
output value from the zero-based min-max line fitted to the data, which gives an indication of the accuracy of typical measurements, taking into account nonlinearity and noise, for ten averaged readings a t each input current. Data recorded for full-scale ranges of and A are equally as good or better than those shown in Table I.
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Comparison of i-to-fand q-to-N Modes. The number of counts produced over a selected constant integration period t u while continuous current is supplied to the converter (i-to-f mode), is compared with the number obtained when known charge packets are supplied to the input (qto-N mode). The data in Table I1 were obtained with the converter set to the 10-6-A range, and for input currents of to 10-6 A integrated for 0.1 sec, and charge input pulses of 10-10 to 10-7 coulombs. The results for the three clock frequencies of 1, 2.5, and 5 MHz indicate excellent agreement in the average counts column. The last two columns show the standard deviation and % relative standard deviation of ten results for each count value listed in Table 71
11.
The data in Table I11 were obtained with the same general conditions as for Table 11, but the integration time for the constant current was now only 1 millisecond, and the input charge packets were of only 1-msec duration. These data are particularly significant for our laboratory because they show the good precision that can be obtained with short information pulses which are characteristic of several spectrochemical applications. For example, a t 2.5-MHz clock frequency, a 1-msec charge packet of 9 X 10-lo coulomb is measured with a precision of 0.04%. Therefore, very reliable data can be obtained in only 1 msec or less. For the results presented in Table 111, the precision of the converter is limited by the 1-count uncertainty of unsyn-
chronized count measurements. The converter response A full scale is the same as a t A full time a t scale. At A full scale, the response time is about 1 ~ w c and , a t 10-9 the converter response is best described as having a rise time of about 100 psec, because of the factor discussed in the V-to-Iconverter section. Applications. The q-to-N converter has been used for almost one year with our automated AF/AE spectrometer (19). In the AF mode, the fluorescent radiation pulses are 10 msec duration and, between each pulse, the background is subtracted. This new converter works very well for this application in conjunction with a gated up/down counter that sums the radiation information from 10-20 fluorescent pulses. The converter has been used in the i-to-f mode in a UVVISIBLE absorption spectrophotometer measurement system. I t is also now being introduced into a high speed centrifugal analyzer. The converter data for these specific applications are included with data on the total analytical system performance for each application. Received for review December 26, 1973. Accepted April 22, 1974. One of the authors (T.A.W.) expresses his appreciation for a Mobil Foundation Fellowship for part of this work, and the authors are grateful for partial support of the work by the NSF under grant GP 18910. (19) R Spillman J Anal. Chem
Lowry, and H V
Malmstadt, to be submitted to
Simplex Optimization of Analytical Chemical Methods Stephen L. Morgan’ and Stanley N. Demingl , 2 Department of Chemistry, Emory University, Atlanta, G a . 30322
Single-factor methods and factorial designs are inadequate for multifactor experimental optimization of analytical chemical methods where complete knowledge of the response is not initially available. The ability of the sequential simplex method (an empirical feedback strategy) to successfully optimize multifactor systems is demonstrated using a manual colorimetric determination of cholesterol in blood serum. A combined absorbance and stability response is maximized as a function of solvent composition, dehydrating reagent concentration, color reagent concentration, and color development time. The simultaneous search for optimum levels of the four factors required only 26 experiments. The optima indicated by convergence of the simplex algorithm and by derivative plots are confirmed by mapping experiments and regression analysis. The efficiency and simplicity of the experimental designs used are attractive for the development of new analytical methods as well as the improvement of existing ones.
In a recent review of statistical and mathematical methods in analytical chemistry, Currie et al. ( I ) point
out that although the area of statistics dealing with experimental design and optimization “is extremely active and highly developed, there has been remarkably little use made of these techniques by English-speaking chemists.” Rubin et al. ( 2 ) , in a survey covering papers listed under the index heading of “statistics” in the major English language journals of analytical chemistry for the past 25 years, uncovered few papers in which experiments were statistically designed. A literature search ( 3 ) under the index heading “optim/” in Chemical Abstracts and Chemical Titles covering the past eight years has led us to the parallel conclusion that few optimizations were statistically designed or otherwise systematically achieved. This paper presents the results of a relatively new method of experimental design and optimization which could have broad applicability in analytical chemistry. Until the early 1920’s, experiments investigating the effects of several factors (variables) on a response were designed using the “one-factor-at-a-time’’approach. In these experiments, each factor but one is held at a low level. The response is then evaluated at the lower and at the upper level of the factor being tested. The prevailing idea was that if the factors were varied simultaneously, the effects of the factors would be hopelessly intermingled ( 4 ) .
C u r r e n t address, D e p a r t m e n t of C h e m i s t r y , U n i v e r s i t y of Houston, H o u s t o n , Texas 77004. A u t h o r t o whom correspondence s h o u l d be directed. ( 1 ) L. A. Currie. J. J. Filliben, and J. R . Devoe, Anal. Chem.. 44, 49713 (1972).
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I . B. Rubin, T. J. Mitchell, and G. Goldstein, Ana/. Chem.. 43, 717 (1971).
P. G. King, Emory University, Atlanta, Ga., personal communication, 1973. G. E. P. Box and K . 6 . Wilson, J. Roy. Statist. SOC.. B. 13, 1 (1951).
