pubs.acs.org/NanoLett
Integration of Nanowire Devices in Out-of-Plane Geometry P. Manandhar,† E. A. Akhadov,†,§ C. Tracy,‡ and S. T. Picraux*,† †
Center for Integrated Nanotechnologies (CINT), Los Alamos National Laboratory, Los Alamos, New Mexico 87545 and ‡ Arizona Institute of Nano-Electronics, Arizona State University, Tempe, Arizona 85287 ABSTRACT We report the fabrication of arrays of single and multiple out-of-plane nanowire devices on a single substrate, an important step for the fabrication of novel three-dimensional devices and the integration of individually addressable nanowires onto current Si planar technology platforms. Vertical nanowire device fabrication can greatly increase device densities; however integrating such devices into arrays with registry to the substrate requires precise control over the number and position of the nanowires. Here we report the directed assembly of gold nanoparticle seeds into patterned arrays for the growth of nanowires using chemical recognition and electrophoretic methods. Chemical recognition provides highly reproducible control of the position and number of nanoparticles per pattern element and is shown to be in good agreement with a simple electrostatic model. Individually addressed out-of-plane, vapor-liquid-solid grown Ge nanowires with single and multiple nanowires per element are fabricated and electrically characterized. KEYWORDS Nanowires, integration, vertical devices, germanium, directed assembly
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of lateral nanowires to reduce contact areas,1,16,17 and stacking of multiple layers of lateral nanowires by transferring nanowires from a growth substrate to rigid18,19 or flexible20,21 substrates for 3D device integration. Such nanowire devices are of interest for special applications such as chemical and biological sensing, photodetection, optical imaging, and integration of dissimilar materials in electronic applications.15,19-21 However, given the density of current planar technology, the appreciable area required by lateral nanowire makes this approach not well matched for integration on top of current Si integrated circuit technology. In contrast, out-of-plane nanowire device architectures offer lateral densities consistent with current integrated circuit technology and provide geometries required for novel 3D circuit approaches. The integration of vertical nanowire devices by bottomup synthesis holds potential interest for electronic-based applications such as programmable switching of CMOS, addressable memories, and compact sensor arrays. Practical application of such approaches requires engineering challenges such as manufacturability and reliability to be addressed while maintaining device performance consistent with current Si technology. Reasonable control over morphology, orientation, and size can be obtained for nanowires grown epitaxially on substrates using a vapor-liquid-solid (VLS) technique.22-24 However, patterning, spatial registry, and contacting of vertical nanowire arrays is also important, including the location and number of nanowires, and the fabrication of contacts to individual or predefined groups of nanowires for vertical devices. Previously, lithographic techniques combined with Au deposition and lift-off have been used to form regular arrays of Au catalytic seeds for VLS growth. Vertical nanowire arrays have been demonstrated, for example, by photolithography for Si nanowires,25 by
s device sizes continue to shrink in the nanometer domain, semiconductor nanowires emerge as important structures for basic research as well as for potential applications in new three-dimensional (3D) circuit architectures. Many prospective uses of these nanostructures in nanoelectronics,1,2 optoelectronics,3,4 and energy-based applications5-7 have been explored in the earlier literature, with the emphasis primarily on individual devices rather than on integration. There has been particular interest in fabricating nanowire devices from the group IV semiconductors due to their compatibility for integration with current Si technology.1 However, while many efforts have focused on the fabrication and study of nanowire devices deposited on surfaces in a lateral geometry, there have been far fewer studies aimed at out-of-plane integration of nanowire devices with Si technology.8 Semiconducting nanowires can be fabricated by either top-down9 or bottom-up1 methods. A particular advantage of the bottom-up approach is the ability to synthesize novel group IV or III-V nanowire heterostructures and potentially even combine group IV and III-V materials,2,10,11 something not possible by top-down technology alone. To exploit this capability for integration into 3D circuits, methods to combine bottom-up nanowire growth with top-down processes on a single platform are needed. Currently most progress for such integration has been concentrated on lateral nanowire structures,12-15 usually by transferring the nanowires after growth to the device substrate. Examples include multiplexing and demultiplexing contacts to parallel arrays
* To whom correspondence should be addressed,
[email protected]. § Present address: Sandia National Laboratories, Albuquerque, NM 87185. Received for review: 03/02/2010 Published on Web: 05/12/2010
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electron beam lithography for InP nanowires,26 and by nanoimprint lithography for InP nanowires using metal deposition and lift-off,27 and also for GaAs nanowires using electron beam lithography patterning followed by Au galvanic deposition.28 These techniques have good spatial registry, but they allow the formation of only a single nanowire per array element. Good spatial registry can enable the facile incorporation of nanowire devices with prefabricated electrode designs and individually addressable nanowire device integration with current planar technologies at needed densities. Previously, integration of out-of-plane nanowire devices on Si platforms has received relatively limited attention although there is growing interest in the area of 3D circuit architectures. Several field effect transistor (FET) devices have been reported for out-of-plane configurations for Si,29-32 InAs,32 ZnO,33 and In2O334 nanowires. Efforts have focused on fabricating individual nanowire device elements on a substrate with single29-31,33,34 or multiple32 nanowires. To our knowledge there has been only one out-of-plane study for Ge nanowires, in that case for 100s of doped or undoped Ge nanowires which were randomly positioned and contacted simultaneously.35 Extending these efforts to integrate single and multiple nanowires into patterned out-of-plane device arrays with high precision on Si platforms will open up new device opportunities. Here we report the integration of vertical Ge nanowire arrays positioned with high registry onto a Si substrate with control of the number and diameter of nanowires per array element. We use electron beam lithography to achieve good nanowire spatial registry and reproducibility as with previous deposition and lift-off approaches, but by combining electron beam lithography with the directed assembly of Au colloids we also achieve good control over the number of nanowires in each pattern element. In addition, we demonstrate individually addressed top-contacts to single and multiple nanowires in the array elements to show vertical device integration. The assembly of the Au nanoparticles that seed the nanowire growth into lithographically defined patterns is found to be a critical feature of our approach to nanowire device integration, because it enables the size, position, and number of epitaxial nanowires to be predetermined. Two different directed assembly techniques, chemical recognition36,37 and electrophoretic assembly,38-40 were investigated for forming ordered pattern arrays of gold nanoparticle catalytic seeds for VLS nanowire growth. Our chemical recognition approach for various pattern element sizes provides highly reproducible control, extending from 1 to 250 nanoparticles per array element for nanoparticles from 40 to 150 nm in diameter, and is well described by a simple electrostatic charge balance model. Using SiO2 fill and chemical-mechanical polishing (CMP), contacts to predefined individual and groups of vertical nanowires are demonstrated to give consistent electrical response, allowing single or clusters of nanowires to be individually addressed. © 2010 American Chemical Society
FIGURE 1. Schematic diagrams of device fabrication process: (a) pattern fabrication using electron beam lithography (EBL) and Au nanoparticles assembly; (b) doped Ge nanowire growth using the vapor-liquid-solid (VLS) growth technique; (c) nanowire encapsulation with SiO2 followed by chemical-mechanical polishing (CMP) and HF etch to expose nanowire tips; and (d) top contact metal deposition.
In combination with lithographic patterning, this approach can enable the vertical integration of multiple nanowire devices with prefabricated structures and circuits in the future. Also, the low temperatures (380 °C) required for heteroepitaxial VLS Ge nanowire synthesis makes the process suitable for integrating out-of-plane devices onto preexisting CMOS platforms. The fabrication sequence is schematically illustrated in Figure 1. Highly doped n-type (111) Si substrates were used as the surface for Au nanoparticle assembly and epitaxial nanowire growth in all of the experiments.41 Electron beam lithography (EBL) patterns with openings of varying area on 600 nm thick poly(methyl methacrylate) (PMMA) layers were used as the template for assembly of Au nanoparticles for both electrophoretic and chemical recognition techniques. The size and location of the patterns were precisely controlled by EBL, as is schematically illustrated in Figure 1a. Gold nanoparticles of a fixed diameter ranging from 40 to 150 nm were then assembled into the EBL patterns using either electrophoretic or chemical recognition methods. During electrophoretic assembly charged particles diffusing in solution by Brownian motion are directed into the open patterned regions by the dc electric field. This technique has often been used to assemble two- and threedimensional layers on surfaces.38 There have been fewer attempts at understanding electrophoretic assembly on patterned substrates.38,39 Field-directed assembly has been used to successfully demonstrate the introduction of dense assemblies of colloidal nanoparticles from solution into trenches.39 Also the internal alternating electric field of ∼100 nm wide periodic Au and SiO2 stripes functionalized to be positive and negative, respectively, has been used to assemble Au colloids from solution into single rows of particles on the surface in a process termed electrostatic funneling.40 In the present studies a dc electric field was applied between the sample substrate and a counter electrode to drive the Au nanoparticles into EBL generated resist patterns of circular holes of varying diameter. A cell volume of ∼100 µL was fabricated using poly(dimethylsiloxane) of lateral area 7 × 7 mm2 with a gold counter electrode embedded in the cell. The cell was filled with Au colloidal solution, and the EBL-patterned sample was brought into contact with the cell such that patterned regions contacted the solution and were enclosed within the cell volume as shown in Figure 2a. 2127
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number of assembled Au nanoparticles per patterned array element as a function of the patterned element area. The number of Au nanoparticles is found to increase with increasing patterned element area as expected. However the number per array element is observed to be nonlinear, increasing more slowly as the size of the pattern area was increased. The standard deviation in the number of assembled nanoparticles per element and run-to-run variations were relatively high, thus limiting the ability to reproducibly achieve a predetermined number of nanoparticles per pattern element. These variations also restricted the ability to reliably assemble single nanoparticles per element. To overcome these limitations chemical recognition was investigated for the directed assembly of the Au nanoparticle growth seeds. The use of surfaces functionalized with selfassembled monolayers of silane molecules for the directed assembly of various organic and inorganic entities is wellknown.36,37,40 In our studies, silanization of the Si(111) surface was used to form an amine-terminated monolayer which provided for the stable assembly of Au nanoparticles within the EBL patterns. The EBL-patterned Si substrate was functionalized with a molecular monolayer of (3-aminopropyl)triethoxysilane (APTES). Substrates were placed in a 2 mM APTES aqueous solution for 2 h followed by sonication in deionized water to remove nonspecifically physisorbed APTES. The silanization process was characterized on reference Si substrates by contact angle measurements, with the water contact angle for a cleaned Si(111) sample of 50° decreasing to 26° after silanization. Since the APTES chemically binds only to the exposed Si regions within the EBL patterns, this provides for the assembly of APTES molecules with the chemically active functional amine end group only in the patterned regions as illustrated in Figure 3a. Functionalized samples were immersed in an as-received Au colloidal solution of a specific colloidal size and constantly agitated using a shaker for uniform assembly of Au nanoparticles. Negatively charged citrate-terminated Au nanoparticles bind with the positive terminal amine group on the APTES molecules to give stable assembly of Au nanoparticles onto the exposed pattern regions on the Si(111) substrate as shown schematically in Figure 3b. We provided ample time for the electrostatic interaction-based assembly process to go to completion during this process by incubating the patterned sample in the Au colloidal solution overnight on a shaker. Poly-L-lysine has also been used for functionalizing Au colloids to Si surfaces for Si nanowire growth; however, control of the number of Au nanoparticles per element was not investigated in those studies.42 SEM images of assembled Au nanoparticles in a 3 × 3 patterned section of a larger 10 × 10 array are shown in parts c and d of Figure 3 for two different EBL pattern sizes. The white dots in the images are the Au nanoparticles. The insets show enlargements of a single pattern element with the red dotted circle outlining the patterned hole to aid visualization. The results in parts c and d of Figure 3 are for
FIGURE 2. (a) Schematic diagram of electrophoretic directed assembly of Au nanoparticles. (b) SEM image of one to three 40 nm diameter Au nanoparticles assembled in 3 × 3 EBL patterned openings with diameters 170 nm. White dots are Au nanoparticles and the inset shows an enlarged view of an opening with two nanoparticles. (c) SEM image as in (b) with 440 nm diameter openings. (d) Graph of the number of Au nanoparticles vs area of the EBL-patterned openings for 40 nm Au nanoparticles.
Assembly of Au colloids from the solution is observed when the driving field is between 1 and 6 kV/m. Although a field of 1 kV/m is sufficient to produce nanoparticle assembly, this low value did not result in reproducibility in the number of Au colloids contained in each pattern. Increasing the field to values above 6 kV/m gave bubble formation in the cell due to dissociation of water molecules, hindering the assembly process. We note that these fields are average values over the area of the cell, and the field inside the patterned hole will be higher due to local field enhancement.39 Assembly times ranging between 1 and 30 min were studied with saturation in the number of assembled nanoparticles being reached within 5 min. A driving field of 2 kV/m for 5 min was selected for the assembly studies. When the electric field is applied between the samples and the counter Au electrode as shown in Figure 2a, the negatively charged citrate-coated nanoparticles are driven from the colloidal solution to the positive potential of the exposed Si patterned surface. Parts b and c of Figure 2 show scanning electron microscopy (SEM) images of assembled 40 nm diameter Au nanoparticles in arrays after removal of the PMMA for 170 and 440 nm patterned holes, respectively. In Figure 2d, the electrophoresis results are shown for the © 2010 American Chemical Society
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surface. To fully characterize the assembly process, we varied both the size of the circular patterned holes within arrays and the diameter of the Au nanoparticles being assembled. Figure 3e shows results for the number of assembled nanoparticles ranging from 1 to 250 which were very reproducible. The lines are best fits through the respective data points for the chemical assembly of 40, 80, and 150 nm diameter Au nanoparticles. The linear behavior indicates the number of assembled particles depends on the area of the patterned element with the slopes corresponding to the number of nanoparticles assembled per unit pattern area. The results of Figure 3e can be understood from the chemical assembly process. The process takes place in two steps: in the first the long-range electrostatic double-layer interaction in the solution drives the citrate-coated nanoparticles to the APTES-functionalized surface, and in the second step the Au colloids chemically bind to the APTES. The electrostatic interaction is due to the negative citrateterminated Au nanoparticles in solution and the positive amine-terminated APTES molecules on the surface. Previous studies for citrate-coated Au nanoparticles interacting with APTESsubstrateshaveestimatedthelong-rangenanoparticle-substrate interaction distance in solution to be ∼270 nm, based on the distance at which the interaction energy drops to the thermal energy of the particles.40 This distance is about half the PMMA layer thickness used here in the EBL patterning. Thus, when a Au nanoparticle diffuses into the pattern and comes within this interaction range, the electrostatic attraction will facilitate assembly and binding of the Au nanoparticle to the APTES molecules. Each nanoparticle assembled into an EBL pattern reduces the electrostatic field due to APTES molecules in the patterns. Thus the assembly process should cease when nanoparticles in the pattern completely compensate the electrostatic field due to the APTES on the surface, providing for a well-defined limiting number of assembled nanoparticles. By equating the charge due to the negative citrate-functionalized Au nanoparticles to the amine charge in the patterned hole, we can estimate the dependence of the assembled number of nanoparticles, N, on the particle diameter, d, and pattern element surface area, AS
FIGURE 3. (a) Schematic diagram of chemical recognition assembly between citrate-coated Au nanoparticles and the APTES-functionalized patterned Si surface. (b) Representation of the chemical assembly process; gold-colored balls represent the Au nanoparticles. (c, d) SEM images of assembled 40 nm diameter Au nanoparticles in EBL patterned openings of diameter 80 and 240 nm, respectively, for a 3 × 3 section of a 10 × 10 array. The dotted red circles in the enlarged insets show the APTES-functionalized openings in which the nanoparticles are assembled; white dots are individual Au nanoparticles. (e) The average number of Au nanoparticles per pattern element for 40, 80, and 150 nm diameter nanoparticles as a function of the area of the EBL-patterned openings. Error bars are shown or correspond to the size of the data points, illustrating good reproducibility over the length scales of our assembly process. The standard deviation for the number of assemble nanoparticles in the smallest patterns (0.04, 0.07, and 0.34 µm2) for the three Au nanoparticles sizes (40, 80, and 150 nm) were 1.7, 0.8, and 0.6, respectively. The inset shows the number of nanoparticles per individual patterned element area versus the inverse of the nanoparticle surface area for 40, 80, and 150 nm diameter Au nanoparticles (all areas are in µm2); the linear behavior is consistent with a charge balance between the functionalized patterned surface and nanoparticle as given by eq 1.
πd2NcNP ) AScS
where cNP and cS are, the surface charge per unit area on the nanoparticles and the patterned surface, respectively. From eq 1 the number of nanoparticles in a patterned element is predicted to depend linearly on the surface area of the pattern element, and this behavior is observed in Figure 3e to be followed closely over the assembly range of 1-250 nanoparticles for a wide range of patterned areas (0.005-2 µm2) and for various nanoparticle sizes. From eq 1 the number of nanoparticles per unit pattern area (slopes of plots in Figure 3e) should be proportional to the reciprocal of the
40 nm diameter Au nanoparticles assembled into EBLpatterned openings of 80 and 240 nm diameters, illustrating the placement of both single and multiple nanoparticles within array elements. For example, in Figure 3d for 240 nm diameter pattern elements, the mean number of particles per element is 8.2 with a standard deviation of 1.3. This statistical variation may be due in part to the precision of the patterns or some charge on the adjacent PMMA © 2010 American Chemical Society
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nanoparticle surface area. This behavior is also observed experimentally, as shown by the inset in Figure 3e. The slope of the inset plot can be used to estimate the ratio of the charge density on the amine- to citrate-functionalized surfaces (cS/cNP) which from the inset of Figure 3e is ∼0.6. These results suggest that chemical recognition provides a welldefined and reproducible method for the directed assembly of nanoparticles into patterned surfaces. The ability to assemble Au nanoparticles with high specificity and registry demonstrated above is a key step for outof-plane nanowire device integration, since this allows one to exploit the bottom-up epitaxial growth of nanowires by the VLS technique. With the chemical recognition approach for Au nanoparticle placement, the VLS growth of Ge nanowires from the patterned arrays was investigated. Although there have been many studies of nanowire growth from Au nanoparticle seeds, growth of Si or Ge vertical nanowires from Au nanoparticles localized in well-ordered arrays with spatial registry has not previously received attention. After chemical assembly of the Au nanoparticles and removal of the PMMA layer by the same process as used for electrophoretic assembly, the samples were dipped in 1% HF (diluted in deionized water) for 1 min to remove the native oxide layer from the substrate and then were immediately loaded into a cold wall low pressure chemical vapor deposition (CVD) reactor for nanowire growth. We verified in separate SEM measurements that there was no loss of Au colloids from the surface for these short times in dilute HF. Phosphorus (P) doped Ge nanowires were grown using a two-step process, where the initial nucleation step is carried out at a higher temperature than the growth step to obtain a high nucleation yield of nanowires while minimizing nanowire tapering due to vapor-solid sidewall growth at higher temperatures.22,24 The nucleation step was carried out at 380 °C for 60 s and the growth at 270 °C, resulting in 900 nm long P-doped Ge nanowires with an average growth rate of ∼120 nm/min. The phosphorus to germanium atom ratio was maintained at 1.33 × 10-4 for a 30% GeH4 gas flow of 300 sccm and 100 ppm phosphine, both diluted in hydrogen with the total pressure maintained at 3 Torr. A high nanowire yield was obtained for nucleation at 380 °C and uniform nanowires with minimal sidewall growth resulted for growth at 270 °C (
