Linear Increases in Carbon Nanotube Density Through Multiple

Apr 6, 2011 - Small 2013 9 (10.1002/smll.v9.24), 4142-4148 ... Jie Zhang , Albert Lin , Nishant Patil , Hai Wei , Lan Wei , H.-S. Philip Wong , Subhas...
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LETTER pubs.acs.org/NanoLett

Linear Increases in Carbon Nanotube Density Through Multiple Transfer Technique Max M. Shulaker,* Hai Wei, Nishant Patil, J. Provine, Hong-Yu Chen, H.-S. P. Wong, and Subhasish Mitra Department of Electrical Engineering, Stanford University, Stanford, California 94305, United States

bS Supporting Information ABSTRACT: We present a technique to increase carbon nanotube (CNT) density beyond the as-grown CNT density. We perform multiple transfers, whereby we transfer CNTs from several growth wafers onto the same target surface, thereby linearly increasing CNT density on the target substrate. This process, called transfer of nanotubes through multiple sacrificial layers, is highly scalable, and we demonstrate linear CNT density scaling up to 5 transfers. We also demonstrate that this linear CNT density increase results in an ideal linear increase in drain source currents of carbon nanotube field effect transistors (CNFETs). Experimental results demonstrate that CNT density can be improved from 2 to 8 CNTs/μm, accompanied by an increase in drain source CNFET current from 4.3 to 17.4 μA/μm. KEYWORDS: Carbon nanotubes, density, multiple transfer

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hile advances in traditional silicon-based complementary metal-oxide-semiconductors (Si-CMOS) continue to be made, alternative technologies are currently being explored. It has been shown that carbon nanotube field effect transistors (CNFETs) have the capability of outperforming Si-CMOS,1 4 thus staging CNFETs as a possible complement to Si-CMOS in the future. However, several significant hurdles in CNFET technology must be overcome before CNFETs can be used in practical applications. One of the challenges facing CNFETs is low CNT growth densities. Patil et al. estimated that for CNFETs to surpass Si-CMOS, the density must be on the order of 250 CNTs/μm.5,6 Yet the highest reliable growths for horizontally aligned CNT growth densities reach an average of ∼10 CNTs/μm,7 while typical growths reach 1 5 CNTs/μm. One way to increase CNT density is by performing multiple transfers, which combines CNTs from several growth sources onto the same target area, thereby increasing CNT density. Today there exist several transfer techniques, such as those detailed by Pike et al.8 and Kang et al.9 These techniques have been shown to be able to perform one transfer while maintaining CNT growth alignment and have shown the ability to perform two transfers at offsetting angles, such as grid patterns. However, previous transfer techniques have not shown the ability to perform multiple transfers while maintaining parallel CNT alignment and no previous transfer technique has shown the ability with scaling CNT density to scale CNFET current handling capabilities. We present a multiple transfer method that demonstrates linear increase of CNT density and likewise an ideal linear increase in CNFET drain source current. This multiple transfer method, which we call transfer of nanotubes through multiple sacrificial layers (TNT-MSL), is highly scalable. It readily scales to full-wafer processes, and we demonstrate the scalability of TNT-MSL for many transfers with results for up to 5 transfers. The TNT-MSL Process. To demonstrate both linear CNT density scaling and resulting linear increase in CNFET currents, r 2011 American Chemical Society

we used highly aligned horizontal CNTs for creating back-gated CNFET devices. Our CNTs are grown on 4 in. quartz wafers, using the same growth method that has been detailed in ref 10. A major advantage pertaining to this transfer technique is that ideal growth substrates can be used, because we transfer the CNTs from this growth substrate onto our final target substrate for device fabrication. We use quartz substrate for our CNT growth because its crystalline structure yields angle-dependent van der Waals interactions between CNTs and the substrate which results in extremely highly aligned CNTs.11 To transfer the CNTs from the quartz wafer to the target substrate (p-doped Æ100æ Si wafer with doping density between 1.7  1016/cm3 and 2.5  1017/cm3 with 110 nm of thermal SiO2), we use the single transfer method as described in ref 10. We first use electron beam evaporation to coat our CNTs with a 150 nm protective layer of gold. Thermal release tape is then applied to the gold and peeled, removing with it the gold with CNTs embedded. This structure, that is, thermal release tape consisting of gold with embedded CNTs, is then placed on top of the target substrate and is heated to 125 C to remove the tape. van der Waals forces cause the CNTs and gold structure to adhere to the surface of the wafer. A timed oxygen plasma etch is used to clean and remove any residue left from the tape. A timed argon plasma sputter etch is then used to etch away the bulk gold covering the CNTs. This etch is timed such that a 20 nm sacrificial layer of gold is left covering the CNTs. This same process is repeated multiple times, each time transferring the new CNTs on top of the remaining 20 nm gold sacrificial layer from the previous transfer. Alignment of the multiple transfers is currently achieved through optical alignment marks and manual placement. While Received: October 15, 2010 Revised: March 28, 2011 Published: April 06, 2011 1881

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Figure 1. Schematic of TNT-MSL process ( A) Highly aligned CNTs grown on quartz substrate . (B) Electron beam evaporation of 150 nm of Au onto CNTs and application of thermal release tape . (C) Peel off thermal release tape (and with it Au with embedded CNTs). ( D) Transfer tape with Au with embedded CNTs onto target substrate. (E) Heat to 125 C to release tape. O2 plasma etch cleans residue from tape. Ar plasma sputter etch removes bulk Au covering CNTs, leaving a thin sacrificial layer of Au covering CNTs . (F) Perform (A E) multiple times, each time transferring new CNTs onto sacrificial Au layer left from previous transfer . (G) Pattern photoresist to expose metal contact areas for source and drain and etch Au in exposed regions. ( H) Electron beam evaporation of Ti/Pd for metal contacts. Lift-off to remove resist and excess Ti/Pd. ( I) Etch remaining gold. After all processing, CNTs are found to conform to with 5 nm of wafer surface.

our results show high alignment based on this method (Figure 4), large-scale scalability could be achieved with a system similar to that currently used for wafer bonding. Such systems are capable of achieving rotational alignments of within 1.64 μrad12 (translational alignment is irrelevant for parallel CNTs), well within the necessary accuracy to perform multiple transfers. After the desired number of transfers has been performed, we pattern photoresist on top of the gold in order to expose only the designated source and drain contact regions of the CNFETs. A gold etchant that does not affect CNTs (Transcene Corp. KI/I2) is used to etch the gold in the exposed patterned regions. Using electron-beam evaporation, we deposit a 1.2 nm titanium adhesion layer followed by a 35 nm layer of palladium to act as our source drain contact metal to form p-type FETs.3,13,14 The rest of the gold on the wafer is then etched, leaving the CNTs on the surface of the wafer with our patterned source drain contacts. The p-doped silicon wafer functions as a back gate with the silicon dioxide as the back-gate oxide (Figure 1). A completed wafer with patterned CNFETs is shown (Figure 2). Scanning electron microscopy (SEM) results show that CNT density increases linearly with increasing number of transfers. We observe average CNT density increase by 1, 2, 2.9, and 3.9 with 1, 2, 3, and 4 transfers, respectively (Figure 3). The reason why multiple transfers can be performed is due to the sacrificial gold layer

Figure 2. Optical micrograph of whole 4 in. wafer, individual die, and individual CNFET, respectively. CNFETs were measured arbitrarily across the area of the transfer region (which spanned several dies). Thus, linear increase of CNT density and CNFET current occurs uniformly across the entire transfer region.

left between transfers. This sacrificial layer was found to be the key enabler for performing multiple transfers. Without this sacrificial layer, adhesion of further transfers was drastically reduced; when all of the gold was etched away between transfers, future transfers do not reliably adhere to the surface of the wafer. Two possible reasons for the decrease of adhesion are (1) increased contamination on the surface of the wafer due to the transfer process and (2) CNT-to-substrate adhesion overwhelmed by increasing CNT-to-CNT interactions. Both of 1882

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Figure 3. SEM of 1, 2, and 4 transfer regions (showing a linear increase in CNT density with increasing number of transfers).

Figure 4. Comparison of multiple transfer with and without sacrificial layers. (Left) With no sacrificial layer between transfers, CNTs aggregate when immersed in liquid due to capillary forces, as shown in SEM below. This sample has two transfers. (Right) SEM confirms sacrificial layers used in TNTMSL prevent aggregation and maintain good alignment of CNTs after multiple transfers (four transfers in this SEM). Compare this sample with just two transfers and no sacrificial layer (left).

these explanations amount to decreased van der Waals forces between the CNTs and the surface of the wafer, which is the dominant force responsible for the adhesion. The sacrificial layer serves to separate the CNTs and provides a clean surface for the next transfer, enabling many transfers. Electron beam evaporated gold, titanium, tungsten, and silicon have been successfully used as sacrificial layers to enable multiple transfers (see Supporting Information). Gold was chosen as our final material due to the ease of processing as gold is already used to coat the tubes for the initial transfer, and the gold etchant does not affect the quality of the CNTs. In addition to linear increase in CNT density, a transfer technique should maintain high alignment of the CNTs, because aggregation of CNTs leads to increased screening between the CNTs and thus nonideal scaling of CNFET on current even with linear scaling of CNT density.15 With no sacrificial layer separating transfers, during the gold wet etch to remove the gold covering the CNTs, the CNTs layered on top of each other “zip” together due to capillary forces (Figure 4). Similar bundling of CNTs has been found for vertically aligned CNTs.16 However, the sacrificial layers covering previous transfers act to anchor the CNTs already transferred onto the wafer, thus preventing aggregation (Figure 4). Furthermore, after all transfers have been completed, only the sacrificial gold in the source drain contact regions is removed, leaving the rest of the sacrificial layers to maintain alignment of the CNTs. After the metal contacts are deposited, the rest of the gold is removed. Aggregation of the CNTs is again avoided, since our metal contacts act as “anchors” for the CNTs crossing in the channel region (Figure 5). The definition of the source to drain separation of the CNFET is maintained even during the isotropic gold wet etch of the contact regions preceding the deposition of the anchors (source drain metal), due to the high

Figure 5. SEM shows patterned metal contacts acting as anchors for CNTs crossing in channel region of CNFET.

aspect ratio of the 1.5 μm channel length versus 20 nm thick sacrificial layers of gold which are etched. For scaled CNFETs, to maintain the source to drain separation of the CNFET during the isotropic gold etch, anchors can be defined apart from the source drain regions, which can later be defined and deposited. SEM images show near perfect alignment of CNTs is maintained for all transfers after the entire fabrication process (Figure 4). It is important to note that though the CNTs are initially separated by sacrificial layers, after CNFET fabrication is completed, atomic force microscopy (AFM) shows CNTs conform against the surface of the wafer, as all transfers lie within 5 nm of the wafer surface (see Supporting Information). Thus gate control of upper transfers does not diminish due to height separation between 1883

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Figure 6. Electrical characterization for CNFETs with 1, 2, 3, and 4 transfers. Results show ideal linear scaling of Ion, constant Ion/Ioff ratio, and decreasing variations of Ion with increasing CNT transfers. CNFET characteristics: channel length = 1.5 μm; channel width = 50 μm; gate-oxide thickness = 110 nm. Vds = 1 V; Vgs = 5 V. Variation estimated by calculated coefficient of variation (=standard deviation/mean). Theoretical decrease of coefficient of variation is by a factor of the square root of the number of transfers performed.

Figure 7. Electrical characterization for CNFETs with 1, 2, 3, 4, and 5 transfers. Results show ideal linear scaling of Ion, constant Ion/Ioff ratio, and decreasing variations of Ion with increasing CNT transfers. CNFET characteristics: channel length = 1.5 μm; channel width = 50 μm; gate-oxide thickness = 110 nm, Vds = 1 V; Vgs = 5 V. Variation estimated by calculated coefficient of variation (=standard deviation/mean). Theoretical decrease of coefficient of variation is by a factor of the square root of the number of transfers performed.

the CNTs and the wafer substrate for our back-gated CNFETs, allowing ideal scaling of the CNFET current. Thus the gate control of upper-transfer layers is maintained irrespective of the number of transfers able to be performed. Linear CNFET current increases are thus achieved by linearly increasing CNT density and ensuring that device performance is not degraded due to CNT bundling. We observe repeatable

4 increases in CNFET current for 4 transfers (Figure 6) and have shown scalability of this method for up to 5 transfers (Figure 7). This increase is due to the increase in CNT density and not due to gold left in the channel; X-ray photoelectron spectroscopy confirms less than 1 part per 10 000 of gold on the surface of the wafer, and Ion can be modulated by gate voltage. Moreover, TNT-MSL does not degrade CNFET performance, as Ion/Ioff 1884

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Nano Letters ratios remain constant over multiple transfers (Figures 6 and 7). As expected, the variation of CNT density decreases by a factor of the square root of the number of transfers performed, which fits the observed data (Figures 6 and 7). Initial growth density should not significantly affect the transfer method due to the separation and thus limited interaction between CNTs due to the sacrificial layers. CNFETs were measured across the entire transfer region, showing the increase in CNT density and CNFET current occurs uniformly across the entire area of the transfer region (Figure 2). Furthermore, it is important to note that CNFET current increases do not appear to be tapering off, suggesting truly ideal linear increases. A CNT can be either metallic (m-CNT) or semiconducting (s-CNT) depending on its chirality.17 m-CNTs have zero or nearzero bandgap and, hence, their conductivity cannot be controlled by the gate. The existence of m-CNTs inside CNFETs creates source-todrain shorts. After multiple transfers, the CNFETs can still successfully undergo the process of electrical breakdown18 20 to achieve ideal CNFET characteristics, such as high Ion/Ioff ratio. In electrical breakdown, s-CNTs are switched off using gate voltage and a large voltage bias is applied across the source and drain of the CNFET. Large currents flow through the m-CNTs inducing self-heating, causing them to break down through oxidation. After electrical breakdown, our CNFETs achieve high Ion/Ioff ratios over 1000, irrespective of the number of transfers performed. Because of the nature of electrical breakdown removing CNTs, Ion decreases from its pre-electrical breakdown value. However, CNFET current increases due to multiple transfers remain even after burning. Observed hysteresis for devices with multiple transfers is also similar with hysteresis reported for similar back-gated CNFET devices.21,22 The above results can all be found in the Supporting Information. In conclusion, we have successfully demonstrated a multiple transfer technique, TNT-MSL, capable of (a) linearly increasing CNT density (b) maintaining high alignment of CNTs, and (c) linearly increasing CNFET current. This is achieved by sacrificial layers and patterned anchors that adhere the aligned CNTs to the wafer. This technique can be potentially extended by performing more transfers and thus enabling ultrahigh density aligned CNTs for use in devices. Moreover, TNT-MSL can potentially be combined with other techniques to increase CNT density, such as high density growth23 and multiple growth,7 allowing for even higher CNT density increases. This highly aligned, high CNT density is useful for the advancement of CNFETs and other CNT applications requiring high density. Specifically, the higher CNT densities achieved by TNT-MSL is scalable to full-wafer, VLSI-scale processing. This brings us one step closer to realizing the exciting potential of CNFETs6,24 as a digital VLSI technology.

’ ASSOCIATED CONTENT

bS

Supporting Information. Additional results include the following: AFM showing CNTs conform against the surface of the wafer, electrical breakdown and hysteresis of CNFETs after multiple transfers, and results using other sacrificial layers. This material is available free of charge via the Internet at http://pubs.acs.org.

’ AUTHOR INFORMATION Corresponding Author

*E-mail: [email protected].

’ ACKNOWLEDGMENT We thank FCRP C2S2, FENA, NSF, and Stanford UAR grant for support. We thank Arash Hazeghi, Kibum Lee, Albert Lin,

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Nathan Klejwa, and Cara Beasley for fruitful collaborations. This work was performed in part at the Stanford Nanofabrication Facility (a member of the National Nanotechnology Infrastructure Network) supported by the National Science Foundation.

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