Localized Electrothermal Annealing with Nanowatt Power for a Silicon

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Localized Electrothermal Annealing with Nano-Watt Power for a Silicon Nanowire Field-Effect Transistor Jun-Young Park, Byung-Hyun Lee, Geon-Beom Lee, Hagyoul Bae, and Yang-Kyu Choi ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.7b17794 • Publication Date (Web): 11 Jan 2018 Downloaded from http://pubs.acs.org on January 11, 2018

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ACS Applied Materials & Interfaces

Localized Electrothermal Annealing with NanoWatt Power for a Silicon Nanowire Field-Effect Transistor Jun-Young Park1, Byung-Hyun Lee1,2, Geon-Beom Lee1, Hagyoul Bae1, and Yang-Kyu Choi1*

1

School of Electrical Engineering, KAIST, 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea

2

Department of Memory Business, Samsung Electronics, 1-1 Samsungjeonja-ro, Hwasung-si 18448, Republic of Korea.

*

Contact for corresponding author - Phone: +82-42-350-3477 - Email: [email protected]

Key words: Nanowire, annealing, dopant activation, dopant control, Joule heat, p-i-n diode, heat treatment, tunneling field-effect transistor

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ABSTRACT

This work investigates localized electrothermal annealing (ETA) with extremely low power consumption. The proposed method utilizes, for the first time, tunneling current-induced Joule heat in a p-i-n diode, comprised of p-type, intrinsic, and n-type semiconductors. The consumed power used for dopant control is the lowest value ever reported. A metal-oxidesemiconductor field-effect transistor (MOSFET) composed of a p-i-n silicon nanowire, which is a sub-structure of a tunneling FET (TFET), was fabricated and utilized as a test platform to examine the annealing behaviors. A more than twofold increase in the on-state (ION) current was achieved using the ETA. Simulations are conducted to investigate the location of the hot spot, and how its change in heat profile activate the dopants.


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1. INTRODUCTION Thermal annealing, one of the most important semiconductor industry processes, is widely used for dopant activation, diffusion, lattice crystallization, and thermal oxidation. Traditionally, a tube type furnace with the ability to anneal a large number of wafers in a single process has been used for thermal annealing. However, the furnace has inherent technical limitations which make it inappropriate for fabricating modern metal-oxidesemiconductor field-effect transistors (MOSFETs). For example, it requires significant time, totaling tens of tens of minutes to hundreds of minutes with ramp-up and ramp-down. To fabricate an extremely scaled MOSFET with high packing density, the diffusion length of the implanted dopants needs to be precisely controlled to reduce the junction depth, to form abrupt junctions, and to reduce short-channel effects. Rapid thermal annealing (RTA) was developed with these requirements in mind. RTA utilizes high energy light emitted from a lamp to ramp up the temperature in a short period of a few seconds, which minimizes the unwanted diffusion of dopants during annealing1. Both the furnace and RTA annealing methods are global thermal annealing processes, which anneal the entire volume of the wafer in a single process. However, as the scaling of the MOSFET reaches the physical limits of atomic scale, even the few seconds of annealing time required by RTA is becoming impractical. A novel annealing method with much faster operation and much higher temperature than RTA is needed to fabricate the modern MOSFET and keep Moore’s law alive. In contrast to global thermal annealing, localized thermal annealing selectively anneals a targeted, localized area in a wafer, rather than annealing the entire wafer in a single process. Laser annealing (LSA), for example, one of these localized processes, uses a moving laser 3 ACS Paragon Plus Environment


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beam to crystalize and to anneal the silicon2. Recently, another localized thermal annealing method, so-called electrothermal annealing (ETA), has emerged as an alternative to LSA. Both the high temperature of the ETA process, which is near or above the melting point of the silicon, and the ETA’s time requirement, are comparable to that of LSA. However, the operating principle of the ETA process is quite different from that of LSA. The heat in the ETA process is generated by current flowing through two electrodes which have been integrated into the MOSFET. The resulting Joule heat can be intrinsically concentrated at a specific nanoscale spot without the aid of the external heating system that must be used for global thermal annealing. The use of this confined heat can improve the reliability and performance of the MOSFET3-6. In addition, the position of the hot spot created by the Joule heat can be engineered by positioning a heat sink, and changing the geometric structure, as well as the material, of the device. Relevant details will be covered later in this paper. Compared to LSA, ETA has several notable advantages, as follows. First, LSA requires much a longer processing time, proportional to the size of the wafer, because the beam size of the laser is limited to less than a few centimeters. Second, with LSA, it is impossible to avoid variations in annealing, because of interference between the laser beams2. When a device is located at the boundary of the laser beam, the number of exposures is different. This problem does not exist with ETA. Third, as summarized in Table S1, the power consumption and thermal budget of the ETA process is also very small compared to LSA. This is because the ETA process does not anneal unnecessary areas of the wafer. Hence, the time requirement for cooling is also negligible. Moreover, ETA has excellent position selectivity in a wafer. Different temperatures and times can be individually applied for each device in a wafer without affecting the other unselected devices. 4 ACS Paragon Plus Environment

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However, while tETA is attractive for improving device performance and reliability, it still suffers from a high level of power consumption when the consumed power is normalized by the number of devices in a wafer. The ETA process using Joule heat is based on flowing current, which in a conductive material such as heavily doped silicon or metal is mostly governed by the drift mechanism. Thus, high power consumption cannot be avoided. For this reason, an ETA process with low power consumption, employing a different current mechanism, would be highly beneficial. The feasibility of such a process has not yet been proven and related research is still modest. In the present study, an ETA method with low power consumption is demonstrated for the first time. In this design a tunneling current flowing through a p-i-n diode, which consists of p-type, intrinsic, and n-type semiconductors, is utilized instead of drift current to generate Joule heat, to activate the p-type and n-type dopants (boron and arsenic). To evaluate the process a number of test platforms with both a p-i-n diode and wrapped gate electrode, a socalled tunneling field-effect transistor (TFET), were fabricated. Then, representative device parameters were characterized to investigate the activation of the dopants implanted in the source and drain. In parallel, numerical simulations were performed to support the measured results of the ETA for thermal engineering.



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2. EXPERIMENTAL SECTION 2.1. Fabrication of the platform device Figure S1 shows the fabrication process flow and images taken of the device. A TFET structured platform which included a 2-terminal (source and drain) p-i-n diode was built on a silicon nanowire (SiNW), and an additional gate electrode straddling the SiNW was fabricated. To fabricate the TFET, first, a suspended SiNW was patterned on a bulk-Si wafer for the 2-terminals of the p-i-n diode on a bare p-type, which corresponds to the intrinsic (i) region. A triangular shaped SiNW was carved using the reactive ion dry etching method known as the Bosch process7-8. Then, tetraethyl orthosilicate (TEOS) was deposited by lowpressure chemical vapor deposition (LPCVD) for device-to-device isolation. Afterwards, it was planarized and recessed by wet etching until the SiNW became a suspended structure. After formation of the SiNW, dry oxidation was carried out to thermally grow a gate dielectric of 5 nm, and n+ poly-crystalline Si (poly-Si) was deposited by LPCVD for the control gate electrode. After gate patterning, a photoresist (PR) was patterned to mask the drain region, and boron was implanted into the source region. After the source formation, the source region was masked, and arsenic was implanted into the drain region. Then, RTA (1000 °C, 3 sec) was carried out to activate the dopants. 2.2. Electrical measurements, and numerical simulations After the device fabrication, a semiconductor parameter analyzer (HP 4155B) was used at room temperature for electrical measurements. Numerical simulations using the 3dimensional heat transfer module in COMSOL and 2-dimensional ATLAS in SILVACO, were carried out to investigate the temperature of the hot spot and its location.


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3. RESULTS AND DISCUSSION 3.1. Electrothermal Annealing of a Silicon Nanowire using Nano-Watt Power

Figure 1. Operating principle of ETA, and bias schematic for low power consumption. (a) Operating principle of ETA. (b-c) Bias schematics of the fabricated TFET with 2-terminal operation to generate



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the tunneling current-induced Joule heat. (d) Measured and extracted power consumption as a function of VETA.

After the device fabrication, ETA was carried out to anneal the dopants as shown in Figure 1a. Figure 1b-c show schematics of the p-i-n diode used to generate the Joule heat with low power consumption. Since the two heavily doped electrodes, the source (p+) and drain (n+), are reversely biased, a few tenths of nA current flows from the source to drain or vice versa, as shown in Figure 1d. This current is based on a tunneling mechanism via the potential barrier of the p-i-n structure. During the ETA process, the potential of the gate electrode (VG) was floated to prevent a parasitic field effect, and the potential of the source (VS) was grounded, and the drain electrode (VD) was reversely biased (VD = VETA). The measured tunneling current under the reverse bias and extracted power consumption (P = tunneling current × VETA) during ETA are shown in Figure 1d. Although the applied reverse bias was sufficiently high (VETA = 8 V), the consumed power was less than 400 nW due to the inherent low magnitude of the tunneling current, as expected.


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3.2. Annealing behaviors and enhanced electrical characteristics in TFET

c

10

b

-9

VTH - 1

10

Cumulative Distribution (%)

10

VD = 0.05 V

VTH

VTH + 1

-10

-11

Fresh After 6V of ETA After 8V of ETA

d

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 Gate Voltage, VG (V)

On-State Current, ION (nA)

10

8

100 80

Fresh After 8V of ETA

60

26 Devices

40

VG = 0, 1 V VD = 0.05 V

20 0 10

-13

10

ION @ VG = VTH + 1 V

4

2 0.0

Fresh After 6V of ETA After 8V of ETA 0.2 0.4 Drain Voltage, VD (V)

0.6

-9

-7

10 10 10 Gate Leakage, IG (A/µm)

10

ION @ VG = VTH + 1 V 8 IOFF @ VG = VTH - 1 V

6

-5

10

-3

Ambipolarity 10

1

VD = 0.05 V

0.1

4 0.01 2

0

e 6

-11

Unipolarity

Threshold Voltage, VTH (V)

Drain Current, ID (A)

10

-8

On-State Current, ION (nA)

a

2 4 6 8 10 Voltage for ETA, VETA (V) Unipolarity

0.0

12

Off-State Current, IOFF (nA)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Ambipolarity

-0.4 -0.8 -1.2 -1.6 -2.0

VD = 0.05 V 0

2 4 6 8 10 Voltage for ETA, VETA (V)

12

Figure 2. Measured and extracted electrical characteristics after ETA. (a) Measured ID-VG characteristics before and after ETA. (b) Extracted ION after ETA. (c) IG distribution of 26 devices used to confirm reliability following ETA. (d) ION increment with various VETA. (e) Shift of VTH beyond critical VETA point. The VTH was extracted by using the constant current method, i.e., VTH is VG to produce normalized ION by DNW of 10 nA/µm. Unipolar I-V characteristics were observed below the critical VETA of 9V, whereas ambipolar ones were seen above the VETA of 9V.



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After an ETA of 8V corresponding to 370 nW was applied to the drain, the TFET was measured with 3-terminal operation with the aid of the gate electrode, which served as the control electrode to turn the TFET on and off. The drain current (ID), which represents the current flowing from the drain to the source under the varying VG and fixed VD, was measured to investigate the annealing behavior of the dopants electrically. Then, based on the measured

ID, the threshold voltage (VTH), which is the criterion point of VG used to determine the onstate and off-state of the TFET, was extracted using the constant current method9. Then the on-state current (ION) and off-state leakage (IOFF) of the TFET were extracted as ID at VG =

VTH + 1 V and ID at VG = VTH - 1 V respectively. In a fresh device immediately after RTA treatment, the measured ID exhibits a unipolar characteristic, which has a negligible IOFF due to insufficient dopant activation at the drain, as shown in Figure 2a. At the same time, the ION includes noise current, because RTA is unable to fully activate the dopants implanted in the source. However, after ETA, the ION noise was clearly reduced, because the ETA activated more dopants. The ION increased by 2.26 times compared with the initial fresh state, without noticeable degradation of the other parameters, such as VTH, IOFF, and subthreshold swing (SS), which represents the slope in the plot of ID-VG, as shown in Figure 2a-b. If ion migration or diffusion at the source and drain is more dominant than the dopant activation, a leftward shift of VTH, and increase SS should be observed during the ETA process. In particular, although the consumed power measured in this work was the smallest value ever reported in a MOSFET device3-6, the ETA efficiently activated the dopants, resulting in performance enhancement. Moreover, after ETA, the improvement in ION device performance remained, and the annealing effect is considered to be a permanent. (Supporting Information Figure S2) 10 ACS Paragon Plus Environment

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It is notable that the more than twofold increase in ION following the ETA process is superior to that achieved by the conventional strained technology used to boost ION which has been widely used by major industries10-11. Until now, increasing the ION of the TFET has been considered one of the most challenging problems. There has been a consensus that employing a low bandgap material, e.g. Si1-xGex, or forming an abrupt junction by utilizing an epitaxy process at the source, will be necessary12. However, the abovementioned methods inevitably require increased fabrication complexity with high cost. Hence, the proposed ETA method can be considered one of the better options to replace the currently used strained technology. From the viewpoint of device reliability, ETA does not result in an increase in gate leakage current (IG), which indicates gate dielectric breakdown-related device degradation, as shown in Figure 2c. Consequently, ETA is an attractive approach for enhancing device performance without sacrificing cost and reliability. In addition, as the VETA increases, the degree of ION increment is raised, as shown in Figure 2d. However, when VETA exceeds a critical point (VETA = 9 V), IOFF increases due to the enforced ambipolar characteristic, and a large VTH shift caused by IOFF begins, as shown in Figure 2e. (Supporting Information Figure S3)



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3.3. Investigation of hot spots and thermal characteristics during ETA

Figure 3. Simulated heat distribution profile during ETA. (a) Simulated hot spots and heat confinement effect in the TFET. (b) Cross-sectional thermal profile of Figure 3a along the a-a´ direction. (c) Extracted relative temperature along the SiNW. The temperature is normalized by the minimum temperature in the SiNW. (d) Extracted temperature of the hot spots with various κG. (e) Heat distribution profile with κG = 1 W/m·K. This image indicates that the location of the hot spot moves from the source and drain to the intrinsic region, compared to Figure 3a.


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Figure 3a-b shows the simulated heat distribution profile in the TFET after the ETA process, with the aid of a COMSOL simulator. In general, the Joule heat is concentrated in the middle of the conductor. However, in this case, the n+ poly-Si gate electrode served as a heat sink. Since the thermal conductivity of the gate (κG = 31 W/m·K) was high enough, most of the heating during ETA was confined near the source and drain, which are not covered by the gate, as shown in Figure 3c. Experimental verification of the hot spots in this structure was already reported in our previous work6. Figure 3d shows the temperature of the hot spots with various κG. As the κG decreases, the gate cannot dissipate the generated heat efficiently, hence the temperature of the source, drain, and intrinsic region are increased. In addition, the location of the hot spot depends on the selected gate material. As the κG decreases, the hot spots are spread away from the source and drain to the intrinsic region, as shown in Figure 3e. Hence, a proper selection of κG determines the heat confinement region. After the localized dopant activation at the source and drain, parasitic series resistance (RSD = RS + RD) which includes resistance of the source (RS) and drain (RD), is extracted, as shown in Supporting Information Figure S4. As the VETA increases, the RSD is reduced by the additional dopant activation at the source and drain.



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3.4. Dopant activation by the localized Joule heat

Figure 4. Analyses of dopant activation during ETA. (a) A pristine device without any applied electrical signals before ETA. (b-c) Dopant activation at the source and drain, VETA < 9V and VETA > 9 V, respectively. (d-e) Simulated energy band diagram with different source and drain doping concentrations to compare the width of the tunneling barrier.

Based on the aforementioned electrical and simulation results, it can be concluded that the dopants were activated, even though the phenomenon of annealing dopants at low temperature has not been reported until now. Figure 4a-c shows the schematics of dopant activation by the tunneling current-induced localized Joule heat. In a fresh device before applying ETA, there is no additional dopant 14 ACS Paragon Plus Environment

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activation, as shown in Figure 4a. However, as the temperature of the source and drain elevates due to the localized Joule heat, as indicated in Figure 3, the dopants at the source and drain are activated (Figure 4b-c). It can be observed that the dopant activation first starts at the source under the low temperature ETA condition (VETA < 9 V), and occurs later at the drain at high temperature (VETA > 9 V). Because of the drain’s lower activation energy (As :3.6 eV)13 compared to the source (B: 4.7 eV)13, the dopants at the drain were already more activated than the dopants at the source following the 3s of RTA, which was carried out during the device fabrication. Hence, at VETA < 9 V, the dopants activation at the source is dominant, and the increase in ION is boosted, while IOFF is barely changed, as shown in Figure 2a, d. However, at VETA > 9 V, the generated heat becomes high enough to anneal the inactivated dopants at the drain, which had not been activated by the RTA, which leads to a high IOFF, due to the ambipolar characteristic and a large shift in VTH. The aforementioned results and the annealing behaviors were further analyzed using numerical simulations, with the assumption that the doping concentrations of the source and drain are different after the ETA process, as shown in Figure 4d-e. As the source becomes more activated at VETA < 9 V, the width of the tunneling barrier between the source and the intrinsic region becomes narrowed, due to the modified built-in potential14. In similar way, as the drain becomes more activated at VETA > 9 V, the tunneling efficiency of the electrons, which governs IOFF flow between the intrinsic region and drain, is increased (Figure 4e), i.e., the ambipolar current in the off-state leakage is enforced.

4. CONCLUSION 15 ACS Paragon Plus Environment


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In conclusion, dopant activation by Joule heating with low power consumption was demonstrated and examined for the first time. The localized Joule heat was generated by tunneling current flowing through the built-in p-i-n diode. This heat effectively activated the implanted dopants in a short time (100 µs). It is noteworthy that the power consumed by the proposed ETA was only hundreds of nW, which is very tiny compared with previously reported works. More impressively, the on-state current was doubled by the electrothermal annealing. The effects of the annealing were validated by analyzing the electrical parameters, such as ION, VTH, and IOFF, in the fabricated TFET platform. In addition, numerical simulations were carried out to validate the conclusion and to investigate the mechanism of the abovementioned results. Finally, the application of ETA including this work is considered suitable for some critical devices which are exposed to harsh bias conditions, or highly iterative operating conditions. ETA is also useful for enhancing the performance of a specific transistor without affecting the performance of other devices. If all the devices in a wafer were annealed by ETA, the process complexity and cost could be a concern. In addition, while we have suggested a representative application of the proposed ETA process to enhance device performance (ION), other applications, such as gate oxide annealing and improving device reliability, are possible by utilizing the other diodes that exist in a MOSFET15.

ASSOCIATED CONTENT 16 ACS Paragon Plus Environment

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Supporting Information

Schematics of the fabrication process flow, and taken images, the comparison of the various kinds of annealing; dopant activation-induced ambipolar characteristics at the drain; extracted resistance of the source and drain before and after the ETA; are available free of charge via the Internet at http://pubs.acs.org.

AUTHOR INFORMATION Corresponding Author *

Yang-Kyu Choi. Email: [email protected]

ACKNOWLEDGEMENT This work was sponsored by the Center for Integrated Smart Sensors funded by the Ministry of Science, ICT & Future Planning as Global Frontier Project (CISS-2011-0031848). This work also partially sponsored by the Global Ph. D. Fellowship Program (2017H1A2A1042274 and 2014H1A2A1022137) through the National Research Foundation (NRF) of Korea funded by the Ministry of Science and ICT.



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Localized Electrothermal Annealing with Nanowatt Power for a Silicon

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