pubs.acs.org/NanoLett
Low Operating Bias and Matched Input-Output Characteristics in Graphene Logic Inverters Song-Lin Li,† Hisao Miyazaki,†,‡ Akichika Kumatani,† Akinobu Kanda,‡,§ and Kazuhito Tsukagoshi*,†,‡ †
International Center for Materials Nanoarchitectonics (MANA), National Institute for Materials Science, Tsukuba, Ibaraki 305-0044, Japan, ‡ Core Research for Evolutional Science and Technology (CREST), Japan Science and Technology Agency, Kawaguchi, Saitama 332-0012, Japan, and § Institute of Physics, University of Tsukuba, Tsukuba, Ibaraki 305-8571, Japan ABSTRACT We developed a simple and novel method to fabricate complementary-like logic inverters based on ambipolar graphene field-effect transistors (FETs). We found that the top gate stacks (with both the metal and oxide layers) can be simply prepared with only one-step deposition process and show high capacitive efficiency. By employing such a top gate as the operating terminal, the operating bias can be lowered within 2 V. In addition, the complementary p- and n-type FET pairs can be also simply fulfilled through potential superposition effect from the drain bias. The inverters can be operated, with up to 4-7 voltage gains, in both the first and third quadrants due to the ambipolarity of graphene FETs. For the first time, a match between the input and output voltages is achieved in graphene logic devices, indicating the potential in direct cascading of multiple devices for future nanoelectronic applications. KEYWORDS Graphene, alumina dielectric, logic gate, inverter, nanoelectronics
G
efficiency top gate (TG) stacks with natural thin alumina as dielectric layer. The stacks are simpler in fabrication, employing only a one-step metal deposition in vacuum and a consequent metal passivation in the atmosphere,13 but show even higher capacitive efficiency than that of popular TGs.14-16 In contrast to the conventional silicon BG (insulated by 300 nm thick SiO2), the improved structure can lower the operating bias within a practical bias level of 2 V. Furthermore, owing to the lowering of operating bias, substantial potential superposition effect from the drain bias (VDD) is observed, which is employed to fulfill the complementary condition between the FET pairs. The inverters can be used under both the positive and negative VDD (the first and third quadrants), due to the ambipolar characteristic of graphene FETs. Enhanced voltage gain up to 6 is achieved when VDD ) 2 V and VBG ) 0. Most importantly, a match between the output- and input-voltage levels is realized. The issue of cascading between devices confronted in BG-based graphene inverters11 is also resolved. The graphene flakes were prepared by mechanical cleavage method from natural graphite and transferred onto silicon wafers with a 90 nm SiO2 layer.17 The layer number was discerned by optical microscopy.18 After patterning FET channels by electron beam lithography and oxygen plasma etching, Au (50 nm)/Ti (5 nm) source and drain electrodes were defined by vacuum thermal evaporation. Afterward, a 30 nm thick Al TG metal was directly evaporated between the source and drain.13 A detailed fabrication process can be found in the Supporting Information. It is important to note that, in striking contrast to conventional TG stacks
raphene-based electronic devices are very attractive for next-generation nanoelectronics,1 because of its unique physical properties, such as high carrier mobility,2-4 possibility of large-area synthesis,5-7 and compatibility with CMOS lithography process. After realization of high-speed basic circuit components, such as gigahertz graphene field-effect transistors (FETs),8,9 the next challenge in developing graphene nanoelectronics is to construct highperformance digital units and to fulfill various logic operations.10-12 Recently, graphene-based complementary-like logic inverters have been experimentally demonstrated.11 One of the main issues in such devices is the high operating bias of about 10 V and the low voltage gain of only 0.044, due to the operation through conventional silicon bottom gate (BG, with 300 nm SiO2 dielectric). From the point of view of engineering, the output voltage of the BG-based inverters, ranging from 1.60 to 1.75 V, is also too narrow and too low to match the operating bias, which may restrain the future direct cascading of multiple devices in integrated circuits. For practical use, optimization of the operating bias, the voltage gain, and the cascading characteristic is strongly required. In this paper, we report the significant reduction of operating bias and improvement of voltage gain in the single-layer graphene (SLG) inverters, operated through high-
* To whom correspondence should be addressed, TSUKAGOSHI.Kazuhito@ nims.go.jp. Received for review: 01/5/2010 Published on Web: 06/02/2010 © 2010 American Chemical Society
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fabrication, no dielectric layer between the Al and graphene layer was intentionally deposited in our method. After the device was exposed to air for hours, a 4-8 nm (see Supporting Information for thickness estimation) passivation layer was naturally formed not only at the TG surface but also, surprisingly, at the interface of TG and graphene. We attribute this interfacial passivation process to the diffusion of atmospheric oxygen into the Al/gaphene contact, due to the weak physical interaction.19 Once the interfacial passivation layer was formed, the leakage current from the TG to graphene could be hardly detected, typically less than 0.2 nA, indicating an excellent insulating property of the natural passivation layer. We note that despite the simple fabrication process, the formation of such a TG dielectric layer is highly reliable and the yield can be higher than 80%, if regarding the samples with leakage higher than 1 nA as failure devices.13 We also note that the breakdown voltage of this natural passivation layer is about 2.4-2.8 V. Before breakdown the TG leakage would show a drastic increase due to the enhanced charge tunneling, which can be used to monitor and prevent TG breakdown. In quasi-static measurement, all dc biases were generated by Agilent 3245A universal sources and measured by 34410A multimeters. For dynamic measurement, periodic square signals were produced by a 32120A function generator and the response was recorded by a 54830B oscilloscope. Throughout the measurement, the devices were immersed in liquid nitrogen (77 K) to eliminate gate hysteresis. Figure 1a shows the schematic diagram for the complementary-like graphene inverters. The inverter is comprised of a pair of ambipolar FETs: the drain-connected p-FET and the ground-connected n-FET. The FET pair shares a common Al TG, a same heavily doped silicon BG, and a public output terminal. The common TG is used as the input terminal for the inverter. Parts b and c of Figure 1 display typical optical microscopy images for a graphene device before and after electrode metallization. Seven FET channels were arranged in parallel on a graphene flake. An advantage of the parallelFET configuration is that even if one or two FETs are damaged, inverters can still be combined through the surviving FETs. In the seven FETs, Five of them (FET1FET5) were etched from the SLG portion with channel width ∼250 nm and length ∼1.5 µm. Since all the SLG FETs were fabricated with the same dimensions, the electrical characteristics for each of them would be nearly identical if no VDD was applied. By randomly combining two out of the five FETs, 10 inverters can be then obtained. Parts d and e of Figure 1 depict the experimental data for a combined inverter consisting of FET2 and FET3. Note that the resistance peak in each FET corresponds to a charge neutrality point (CNP), the majority carriers to the left and right sides of which are therefore electrons (n-type) and holes (p-type), respectively. By connecting FET2 to VDD (biased at 2 V) and FET3 to the ground (floating other FETs), a CNP splitting forms along the axis of input voltage (VIN), and the © 2010 American Chemical Society
FIGURE 1. (a) Schematic diagram for the complementary-like SLG inverter. (b) and (c) Typical optical microscopy images for an etched graphene flake and the corresponding FET array. The arrows in (b) indicate the boundaries for SLG, bilayer (BLG), and trilayer graphene (TLG) sheets. Seven graphene FETs are defined in the flake with public top gate and output terminals. A merit of this configuration is that even if one of the FETs is damaged, inverters can still be combined through the surviving FETs. (d) and (e) The operating principle for the inverter consists of FET2 and FET3. Once a CNP splitting between the FET pair is produced along the input voltage axis, voltage inversion can be achieved in the region of CNP splitting.
complementary configuration is then achieved within the region of CNP splitting. Since the two FETs are connected in series between the drain and ground terminals, the output voltage (VOUT), i.e., the voltage drop on the grounded FET3, would vary with the resistance changes in both FETs, following the relation
VOUT ) VDD
( R2 R3+ R3 )
The characteristics of voltage inversion can be then obtained as shown in Figure 1e. One of the issues for the conventional BG-driven graphene inverters is the high operating bias and the consequent low voltage gain.11 A significant improvement in this study is the substitution of high capacitive efficiency TG stacks for the silicon BG as the operating terminal, for the purpose of reduction of operating bias. The capacitive coupling ability of the new structure is rather high. The effect of bias change of 2-2.4 V on the Al TG is equivalent to that of 200 V on the conventional 300 nm SiO2 BG (equivalently, 60 V on the 90 2358
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FIGURE 2. Effect of potential superposition from VDS (VDD) bias on an individual FET (FET pairs in inverters). (a) The IDS minimum shift under different VDS for an individual FET. (b) The corresponding magnitude of the shift versus VDS, with a slope of 1/2 at low VDS regime. (c-e) Schematic charge distributions for the FET channel under varied VDS and VTG conditions. (f) The resistance behavior for two FETs (involved in an inverter) under different VDD. (g) The corresponding CNP positions and the resulting CNP splitting as a function of VDD. The lines are guides for the eye.
the effect of potential superposition from VDS on the drain-source current (IDS) for an individual FET. For small VDS ) 10 mV, the IDS minimum (i.e., CNP) is located at the global neutrality point around VTG ≡ 0.1 V. As VDS is increased from 0.1 to 0.5 V, the current minimum shifts from 0.15 to 0.42 V accordingly. Such a coupling arises from the large channel superposition potential from VDS and can be understood as follows. At VDS ) 0, the channel can be simultaneously neutralized by VTG (Figure 3c). When VDS is increased, the potential of the channel increases and the effective potential difference between TG and channel decreases. As a result, the channel deviates from the neutrality condition, and additional positive charges are induced (Figure 3d). To introduce charges with opposite polarity and reneutralize the channel (Figure 3e), the VTG should be increased by about 1/2VDS (Figure 3b), behaving as a positive shift of IDS minimum along the VTG axis. Thus, the position of IDS minimum can be tuned by VDS in an individual FET. Figure 2f shows the resistance behavior at different VDD for two FETs in an inverter. When positive VDD biases are applied, both resistance curves of the FET pair shift positively along the VIN axis, in response to the additional superposition potential. Importantly, the shift of FET2 is always larger than that of FET3, since FET2 is located upstream in the inverter loop and senses higher superposition potential from VDD. By utilizing such an asymmetric shift, we can then control the
nm SiO2 in Figure S2a of Supporting Information), indicating an 80-100 times enhancement of coupling ability shown in ref 11. The capacitance of the natural alumina dielectric is estimated to be 0.92-1.2 µF cm-2, also higher than the popular on-top-deposited high-κ HfO2 or SiO2 TG dielectrics,14-16 which often show nonuniformity and large leakage at fewnanometer thickness and should be thicker than 10-20 nm to prevent leakage. With the high-efficiency alumina dielectric, the operating bias (VIN) in our device can be lowered within the practical CMOS bias level of 2 V. At 77 K the hole and electron mobilities are still about 1300 and 2300 cm2/ (V s) (Figure S3c, Supporting Information), showing no considerable mobility degradation underneath the alumina layer. As mentioned, a CNP splitting between the FET pair is indispensible to fulfill the voltage inversion behavior. In the previous report,11 to obtain such a splitting between the otherwise identical FET pairs, an electrical annealing process is employed to remove the doping source (air contamination) on one of the FETs. However, such an annealing process may be difficult to control, due to the uncertainty in the degree of contamination and possible varied thermal response to current. In this study, the realization of lowering VIN to a comparable range with VDD (or VDS for an individual FET) allows us to observe a sizable coupling between them and to directly tune the CNP shift by VDD. Figure 2a reveals © 2010 American Chemical Society
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FIGURE 3. Quasi-static transfer characteristics for the ambipolar SLG inverter under varied VBG biases. (a) The first-quadrant behavior at VDD ) 2 V. (b) The third-quadrant behavior at VDD ) -2 V. (c and d) The corresponding voltage gains. For each curve, the input voltage is scanned forward and backward to check the gate hysteresis.
CNP splitting electrically, which is verified to be a more effective and controllable way. Figure 2g summarizes the CNP shifts and the resulting CNP splitting as a function of VDD. When VDD is changed from 0.01 to 2 V, the CNPs for the both FETs vary roughly in a linear fashion with different slopes, giving rise to a linear relation with slope ∼1/4 for the resulting splitting with respect to VDD. The ability to electrically tune the CNP splitting enables better control on the inverters. One of the typical features for ambipolar-FET-based inverters is the ability of operation in both the first and third quadrants.20,21 Parts a-d of Figure 3 show the quasi-static transfer characteristics of the inverter under VDD of 2 and -2 V for the first and third quadrants, respectively. In both cases, VBG is changed from -8 to 8 V and the input voltage is scanned forward and backward to check the hysteresis of each curve. The variation of VBG shifts the output curve linearly due to the shifting of CNP positions of the FET pair. Sharp output inversions are observed, irrespective of VBG. The inversion ranges from about 0.5 to 1.5 V in the first quadrant when VDD ) 2 V (Figure 3a) and about -1.5 to -0.5 V in the third quadrant when VDD ) -2 V (Figure 3b). The inversion amplitudes are around 50% of VDD in the both cases. The corresponding voltage gain, defined as -dVout/ dVin, is plotted in parts c and d of Figure 3. Voltage gains of 4-7 are reproducibly achieved under different VBG in the both quadrants. Note that all the voltage gains at the inversion center are larger than 1, indicating a Real gain of the VOUT from the VIN. Besides, the gain nearly reaches 6 in the © 2010 American Chemical Society
FIGURE 4. Typical dynamic response of the SLG inverters under a 10 kHz square-waveform stimulus at VDD ) 2 V. Matched high/low levels between the output and input voltages are obtained. This means that an output from the preceding device can be used to drive the next device, reflecting a good direct cascading characteristic for future integration.
first quadrant as VBG ) 0, which is not only >100 times enhancement to the previous graphene inverters10-12 but also superior to the carbon nanotube counterparts.22 The significant performance improvement demonstrates again the merit of the one-step-deposited TG stacks. Figure 4 shows the dynamic response of the inverters under a 10 kHz square-waveform stimulus. When a square waveform with a high voltage level (VH) of 1.5 V and a low voltage level (VL) of 0.5 V is input, a square response with VL 2360
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) 0.6 V and VH ) 1.5 V is detected accordingly. In particular, the VH and VL of VOUT are close to those of VIN, indicating a match on the voltage levels. This is a very important factor for logic applications, implying that the output can be used as a direct drive for next devices in a same chip, and showing the possibility for large-scale integration. For graphene, one of the most attractive applications is for high-frequency devices, due to its high carrier mobility and low resistivity. The potential of direct cascading is expected to be utilized in the fabrication of complicated high-frequency units, such as ultra-high-frequency ring oscillators.22 The achievement of >1 voltage gain,
