Low Voltage, Hysteresis Free, and High Mobility Transistors from All

Mar 2, 2012 - High-mobility solution-processed all-inorganic solid state nanocrystal (NC) transistors with low operation voltage and near-zero hystere...
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Low Voltage, Hysteresis Free, and High Mobility Transistors from AllInorganic Colloidal Nanocrystals Dae Sung Chung,† Jong-Soo Lee,† Jing Huang,† Angshuman Nag,† Sandrine Ithurria,† and Dmitri V. Talapin*,†,‡ †

Department of Chemistry and James Frank Institute, University of Chicago, Chicago, Illinois 60637, United States Center for Nanoscale Materials, Argonne National Lab, Argonne, Illinois 60439, United States

‡

S Supporting Information *

ABSTRACT: High-mobility solution-processed all-inorganic solid state nanocrystal (NC) transistors with low operation voltage and near-zero hysteresis are demonstrated using highcapacitance ZrOx and hydroxyl-free Cytop gate dielectric materials. The use of inorganic capping ligands (In2Se42‑ and S2‑) allowed us to achieve high electron mobility in the arrays of solution-processed CdSe nanocrystals. We also studied the hysteresis behavior and switching speed of NC-based field effect devices. Collectively, these analyses helped to understand the charge transport and trapping mechanisms in all-inorganic NCs arrays. Finally, we have examined the rapid thermal annealing as an approach toward high-performance solution-processed NCs-based devices and demonstrated transistor operation with mobility above 30 cm2/(V s) without compromising low operation voltage and hysteresis. KEYWORDS: Semiconductor nanocrystals, inorganic ligands, charge transport, electron mobility, field-effect transistor

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devices was their switching reversibility or hysteresis that could be defined as bistability in the current−voltage relations during off-to-on and on-to-off sweeps of the gate voltage. In FETs and integrated circuits, any hysteretic response must be avoided because it leads to additional energy dissipation. On the other hand, bistability could be useful in nonvolatile memory devices. Enabling the operation of NC transistors at low voltages and minimal hysteresis without sacrificing high mobility requires the understanding of charge transport and trapping in NC devices and finding optimal materials combinations and device geometry. In this work, we used In2Se42− and S2− capped CdSe NCs that have shown the highest electron mobility among series of CdSe NCs capped with MCCs and with metal-free inorganic ligands, respectively.9−11 We also studied two different transistor geometries, bottom-gated FET with high-capacitance ZrOx metal oxide dielectric layer and top-gated FET with hydroxyl free polymer dielectric layer. These geometries were employed to optimize low voltage operation and low hysteresis operation, respectively. As a result, we demonstrated for the first time solution-processed low voltage (15 cm2/ (V s)) electron mobility in semiconductor nanocrystal arrays while preserving quantum-confinement in individual nanocrystals .10 The improvements of charge carrier mobility observed in the transistors on colloidal NCs are encouraging. Nevertheless, the operating voltages required to achieve good performance of reported solid state NCs transistors were high (at least 20−40 V)6−12 in comparison to best organic field-effect transistors (FETs)13 and FETs using a-Si/H.14 These voltages were also too high for practical applications of NC FETs in circuitry and portable electronics. Another poorly investigated side of NC © 2012 American Chemical Society

Received: November 9, 2011 Revised: January 16, 2012 Published: March 2, 2012 1813

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the NC-FETs. Because of high mobility and low hysteresis in our devices, switching speed over 10 kHz was demonstrated even for devices with 150 μm long channels. In addition, the use of rapid thermal annealing enabled us to demonstrate the highest mobility from solution processed NCs based devices, 38 cm2/(V s). CdSe NCs Synthesis and Exchange of Original Capping Ligands with In2Se42− and S2−. Wurtzite phase 4.8 nm CdSe NCs with the first excitonic peak at 586 nm were synthesized following established methods.15 As-synthesized CdSe NCs were capped with octadecyl phosphonic acid and dissolved in nonpolar organic solvents such as toluene or hexane. Molecular metal chalcogenide complex (N2H4)2(N2H5)2In2Se4 was synthesized by dissolving stoichiometric amounts of γ-In2Se3 and Se in hydrazine at room temperature16 and (NH4)2S solution (40−48 wt % in water) was purchased from Sigma Aldrich. For the ligand exchange with In2Se42−, 63 μL of 0.25 M (N2H4)2(N2H5)2In2Se4 solution in hydrazine were mixed with 1.5 mL of N2H4. Toluene (1.5 mL) containing 6.25 mg of CdSe NCs was added on top of the hydrazine phase and the resulting solution was stirred for 4−6 h until complete transfer of NCs from toluene phase to polar N2H4 phase. The hydrazine phase was further purified by triple washing with toluene and filtered through a 0.2 μm PTFE filter. Any MCC ligands not bound to the NC surface were eliminated by precipitating the NCs with anhydrous acetonitrile. After centrifugation, the NCs capped with In2Se42− were dispersed in anhydrous N2H4 at 25 mg/mL concentration. For the ligand exchange with S2−, 20 μL of (NH4)2S solution was added to 1 mL of formamide (FA) and mixed with 1 mL of NC dispersion in toluene (5 mg/mL). The mixture was stirred for about 5−10 min for a complete phase transfer of CdSe NCs from toluene to FA phase. FA phase was washed three times with toluene and filtered through a 0.2 μm PTFE filter. Minimum amount of acetonitrile was added to precipitate the NCs, followed by redispersion of NCs in neat FA (∼25 mg/ mL). To form the FET channel, In2Se42− or S2− capped NCs were deposited by spin-coating onto the dielectric layer. Because of the high boiling point of FA (210 °C) which is a processing solvent for S2− capped NCs, we have used a 500 W infrared lamp to maintain substrate and solution temperature around 80 °C during the spin-coating process. As-deposited NC films were dried at 80 °C for 30 min, followed by annealing. Unless otherwise stated, we annealed the NC films at 200 °C on a hot plate for 30 min. Such annealing process helped to get rid of the solvent and generated all-inorganic NCs films. At the same time, 200 °C annealing did not induce sintering of CdSe NCs. Figure 1a,b shows the absorption spectra for the films of CdSe NCs capped with In2Se42− and S2− ligands, respectively, before and after the annealing process. The excitonic peaks are clearly observed in the absorption spectra after annealing at 200 °C for 30 min. A small red shift observed after the annealing could originate from strengthening of the electronic coupling between individual NCs as well as from the changes in the NC dielectric environment.17 Low-Voltage FETs Using All-Inorganic NCs. Lowvoltage operation of an FET requires a strong capacitive coupling between the channel and the gate. This is typically achieved by using very thin layers of gate dielectric or by using materials with high dielectric constant. We selected sol−gel processed ZrOx (ε ∼ 9) as the dielectric layer. To form a continuous 6 nm thick ZrO x layer, a zirconium(IV)

Figure 1. Absorption spectra measured using an integrating sphere for thin films of (a) In2Se42− and (b) S2− capped CdSe NCs before (black lines) and after (red lines) annealing at 200 °C for 30 min.

acetylacetonate solution in N,N-dimethylformamide (DMF) was spin-coated onto a heavily doped Si wafer and cured under high temperature (400 °C) for 1 h as described in a previous report.18 Post annealing of spin-coated ZrOx films at 400 °C was found to be the optimal condition for both high areal capacitance (550 nF/cm2) and low gate leakage current (∼10−7A/cm2) through dielectric layer (see details in Supporting Information, Figure S1). The cured film was passivated with pure hexamethyldisilazane (Aldrich) deposited by spin-coating and postannealed at 200 °C for 20 min to further decrease the leakage current and to minimize the concentration of surface hydroxyl groups (Supporting Information, Figure S2). In2Se42− or S2− capped NCs were spin-coated onto ZrOx dielectric layer followed by drying and annealing. Typical thickness of the NC layer was about 30 nm. Source and drain Al (∼600 Å) electrodes were directly patterned on top of the annealed NC films using a shadow mask. Figure 2a shows schematic image of the bottom gate−top electrode device configuration used in this work. Figure 2b,c shows typical output characteristics of NC FETs operating at low voltages ( 20 μm, while transistor-transistor logic (TTL) signal protocol defines VD = 2−5 V. To overcome these limitations, one has to introduce printable semiconductors with high carrier mobility. In addition to transit times, the input and feedthrough capacitances limit the switching speed of FETs in real circuits.31 In highly disordered semiconductors, trapping and detrapping of the charge carriers often determine device response time.32 The hysteresis in transfer characteristic also introduces additional energy dissipation and generates nonlinear response, which is especially detrimental for analog circuits. To the best of our knowledge, previous studies focused on the static output and transfer curves of NC FETs, whereas their switching characteristics have not been studied. To estimate the switching speed of our FET devices, we have measured the time response of the channel current as shown in Figure 4. The drain−source current was modulated by applying square or sinusoidal voltage signal between source and gate electrodes at different frequencies. Measured 3 dB frequency cut-offs of low voltage FETs were 2200 and 4700 Hz for In2Se42− and S2− capped CdSe NCs, respectively. The f value obtained from carrier transit time for a transistor made of S2− capped CdSe NCs is ∼4000 Hz, assuming the mobility of ∼1 cm2/(V s) and saturation source−drain voltage of 1 V. This is very similar to the 3 dB value obtained above. However, this relation was not observed for the transistors using In2Se42− capped CdSe NCs. Although the transistor using In2Se42− capped CdSe NCs showed almost ten times higher mobility, observed 3 dB frequency cutoff was about two times lower than in the transistors using S2− capped CdSe NCs. We suggest that the presence of larger hysteresis in the transistor of In2Se42− capped CdSe NCs is limiting the FET switching speed because of slow detrapping of charge carriers. This explanation is supported by results from the hysteresis-free Cytop transistor. The theoretical f value of Cytop transistor is ∼13 000 Hz assuming the mobility of ∼1 cm2/(V s) and saturation source− drain voltage of 3 V for both In2Se42− and S2− capped CdSe NCs. This value was very consistent with measured 3 dB cutoffs as shown in Figure 4f. These results show that the essential criteria for real applications of NCs transistors is not only high mobility but also their hysteresis free operation. Here we have shown that smart materials design and optimal device geometry enable the NCs transistor to provide both high carrier mobility and high switching speed. Rapid Thermal Annealing. In this work, as mentioned above, we have limited the annealing temperature of semiconductor layer to 200 °C to prevent any sintering of NCs. As shown in Figure 5a, annealing at 300 °C for 30 min results in significant sintering of In2Se42− capped NCs, leading to the loss of quantum confinement in the absorption spectra. Recently, the rapid thermal annealing (RTA), which enables hightemperature treatment in a time scale of seconds, has been applied to NCs to minimize sintering while taking advantage of the thermal treatment.33,34 In this work, we have employed RTA (ULVAC-RIKO, MILA-5000) to further enhance the performance of NC-based transistors. Figure 5a shows the absorption spectra of RTA-treated CdSe NCs capped with In2Se42− at various temperatures for 5 s. As the temperature increases, the signs of sintering, broadening of the excitonic peaks, and red shift of the absorption edge become more pronounced. The temperatures higher than 400 °C resulted in featureless absorption spectra. At the same experimental conditions, we have also fabricated FETs on SiO2 (100 nm) substrate to study the relationship between RTA temperature,

Figure 5. (a) Thin film UV−vis absorption spectra measured for In2Se42− capped CdSe NCs after various rapid thermal annealing (RTA) conditions. (b,c) Dependence of the FET linear range mobility and on/off ratio for transistors using CdSe NCs capped with In2Se42− as the semiconductor channel and 100 nm thick layer SiO2 as the gate dielectric on (b) RTA temperature and (c) RTA time. (d, e) Output characteristics for RTA processed devices with (d) bottom-gated FET with ZrOx gate dielectric and (e) top-gated FET with Cytop gate dielectric (L = 150 μm, W = 1500 μm). (f,g) The transfer characteristics for devices shown in panels d and e with linear mobility of 33 cm2/(V s) and 5.1 cm2/(V s), respectively.

time, and transport characteristics (Figure 5b,c and Figure S8 of Supporting Information) After rapid thermal annealing at 300 °C for 5 s, the charge carrier mobility of resulting transistors increased to a value higher than 30 cm2/(V s), which was about two times higher compared to the best previously reported devices annealed on a hot plate. The mobility further increased with the maximum temperature applied during RTA process while the on/off ratio decreased with annealing temperature due to a dramatic increase of off current after high-temperature anneals. Similar trends (increase of mobility and off-current) were observed with increasing the annealing time for RTA process from 5 to 30 s. In other words, short time (5−10 s) RTA process at 300 °C provided optimal condition for both high mobility and high on/off ratio devices. Figure 5d−g shows the application results of this technique to low voltage and low hysteresis transistors. For bottom-gated FETs with ZrOx gate dielectric, the highest mobility of devices with In2Se42− capped CdSe NCs reached 33 and 38 cm2/(V s) for the sweep range of 1 and 2 V, respectively. The Cytop top-gated devices showed 1818

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mobilities up to 5.1 cm2/(V s) and almost zero hysteresis in both transfer and output characteristics shown in Figure 5f,g. These results suggest that RTA can be a very powerful technique for making high-performance solution-processed NC devices. Generally speaking, switching from conventional hot plate or furnace annealing to RTA can help to improve the electronic coupling between the NCs while minimizing sintering of individual NCs. The improvement of the electronic coupling between the NCs occurs primarily due to the chemical transformation of MCC ligand into the inorganic conductive “bridge” between NCs.9 An example of such reaction is (N2H5)2In2Se4 → N2H4+2H2Se + In2Se3. This reaction takes place in a very thin layer between NCs upon annealing. We found that annealing at temperatures below 200 °C cannot provide high FET mobility (Supporting Information Figure S9). The reaction rate rises exponentially with temperature. At the same time, NC sintering requires atom diffusion over distances comparable with the NC sizes, following the ⟨x⟩ = (Dt)1/2 relation, where ⟨x⟩ is the mean diffusion distance, D is the diffusion coefficient, and t is time. A short high-temperature spike results in a prompt decomposition of the MCC ligands, whereas fast cooling should minimize atom diffusion and NC sintering. In summary, we fabricated and characterized field-effect transistors from In2Se42− and S2− capped CdSe NCs with two different device geometries: ZrOx bottom-gate dielectric and Cytop top-gate dielectric. The high-capacitance ZrOx devices enabled low voltage operation of high-performance transistors and the hydroxyl-free Cytop devices enabled hysteresis-free FETs with high switching speed (>10 kHz) without compromising high charge carrier mobility. From a systematic study of hysteresis and switching speed of these transistors, we suggest that metal-free capping ligands such as S2− could be a better choice for reliable operation of NC-based electronics. In addition, by employing RTA technique we demonstrated that transistors with field-effect mobility exceeding 30 cm2/(V s) greatly surmounted the previous limitations of solution processed NC-based field-effect devices. We also believe that colloidal nanocrystals should be considered for a broad range of potential applications beyond FETs. They can combine high electron mobility with efficient light absorption, luminescence, or thermoelectric properties and introduce a lower cost alternative to various traditional semiconductor technologies.

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was supported by the U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357.

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ASSOCIATED CONTENT

S Supporting Information *

Additional experimental details and figures. This material is available free of charge via the Internet at http://pubs.acs.org.

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REFERENCES

AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS We thank James Kurley for help with RTA measurements. This work was supported by the Office of Naval Research under Award Number N00014-10-1-0190 and by NSF CAREER under Award Number DMR-0847535. The work also used facilities supported by NSF MRSEC Program under Award Number DMR-0213745. The Center for Nanoscale Materials 1819

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